WO2011153721A1

WO2011153721A1 - Method and apparatus for adjusting frequncies

Info

Publication number: WO2011153721A1
Application number: PCT/CN2010/074667
Authority: WO
Inventors: 郑伟
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-06-10
Filing date: 2010-06-29
Publication date: 2011-12-15
Also published as: CN102281063A

Abstract

A method and an apparatus for adjusting frequencies are provided, which relate to the field of digital products to resolve the technical problem in the prior art that the clock source frequencies can not be dynamically adjusted. The method includes: a frequency synthesis module outputs a first clock of the last sampling cycle, a control module receives a reference clock of the last sampling cycle and the first clock of the last sampling cycle and outputs the time length of a adjustment cycle generated according to the reference clock and the first clock; a phase-locked loop module receives a source clock of the current sampling cycle, and outputs a second clock of the current sampling cycle according to a predetermined frequency-doubling coefficient, the second clock contains a predetermined total number of shunts and there are predetermined phase differences among all the shunts; the frequency synthesis module receives the second clock, and selects each shunt of the second clock in turn, carries out frequency synthesis according to the time length of the adjustment cycle and a predetermined frequency synthesis coefficient, outputs the first clock of the current adjustment cycle. The method and the apparatus can dynamically adjust the frequencies of the clock source.

Description

Method and device for adjusting frequency

Technical field

The present invention relates to the field of digital products, and more particularly to a method and apparatus for adjusting frequency.

Background technique

Clock signals are found in almost all digital products. Depending on the requirements and application scenarios, the requirements for performance specifications such as clock accuracy and stability are also different. In most applications, the device's local clock source does not need to be functioning externally, and the clock's performance metrics can meet the demand. In contrast, the industrial measurement and communication field requires high performance specifications for clocks. In most cases, it is necessary to use an auxiliary means to calibrate the clock, for example, using a cesium atomic clock or satellite timing as a reference to adjust the clock frequency.

In a clock system, the clock source sends the clock to the phase-locked loop and adjusts the output to the desired frequency. Most phase-locked loops can adjust the frequency of the clock source to a preset value and output multiple clocks of the same frequency and different phases. However, this method cannot dynamically adjust the clock source frequency.

Summary of the invention

The technical problem to be solved by the present invention is to provide a method and apparatus for adjusting the frequency, which can dynamically adjust the frequency of the clock source.

In order to solve the above technical problem, the embodiments of the present invention provide the following technical solutions:

In one aspect, a method of adjusting a frequency is provided, including:

The frequency synthesizing module outputs a first clock of the last sampling period, the control module inputs a reference clock of the last sampling period and a first clock of the last sampling period, and outputs the reference clock according to the reference clock and the first clock The length of the generated adjustment period;

The phase-locked loop module inputs a source clock of the current sampling period, and outputs a second clock of a current sampling period according to a preset multiplication factor, and each branch has a predetermined phase difference;

The frequency synthesis module inputs the second clock, sequentially selects each branch of the second clock, performs frequency synthesis according to the duration of the adjustment period, a preset frequency combination coefficient, and outputs a current adjustment week. The first clock of the period.

And outputting, by the frequency synthesizing module, a first clock of the last sampling period, the control module inputs a reference clock of the last sampling period and a first clock of the last sampling period, and outputs the reference clock according to the reference clock Before the step of adjusting the duration of the first clock, the method further includes: the control module configuring a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock;

The control module configures a total number of branches of the second clock and a phase difference between each branch of the second clock according to an accuracy requirement of a frequency of the first clock;

The control module configures a frequency combining coefficient of the frequency synthesizing module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop.

The frequency synthesizing module inputs the second clock, sequentially selects each branch of the second clock, performs frequency synthesis according to the duration of the adjustment period, a preset combining frequency coefficient, and outputs a first clock of the current adjustment period. The steps include:

Step 31: The frequency synthesizing module receives the duration of the adjustment period from the control module. Step 32: The frequency synthesizing module determines whether the branch of the second clock selected in the last adjustment period is the last one, if The branch of the second clock selected in the last adjustment period is the last one, and step 33 is performed. If the branch of the second clock selected in the previous adjustment period is not the last one, proceed to step 34;

Step 33, switching to the first branch of the second clock, frequency synthesis by the first branch of the second clock of the current adjustment period, and then proceeding to step 35;

Step 34, switching to the next branch of the second clock, performing frequency synthesis by the next branch of the second clock of the current adjustment period, and then performing step 35;

Step 35: After the duration of the adjustment period, enter a next adjustment period.

The step of performing frequency synthesis by the first branch of the second clock of the current adjustment period includes:

Outputting a square wave, when the number of rising edges of the first branch of the second clock of the current adjustment period reaches a reciprocal of the combining coefficient, triggering a high level of the square wave; when the current adjustment period is The number of falling edges of the first branch of the second clock reaches the reciprocal of the combining coefficient Triggering a low level of the square wave;

The step of performing frequency synthesis by the next branch of the second clock of the current adjustment period includes:

Outputting a square wave, when the number of rising edges of the next branch of the second clock of the current adjustment period reaches a reciprocal of the combining coefficient, triggering a high level of the square wave; when the current adjustment period is When the number of falling edges of the next branch of the second clock reaches the reciprocal of the combining coefficient, the low level of the square wave is triggered; the reciprocal of the combining coefficient is a natural number.

And the step of the control module inputting the reference clock of the last sampling period and the first clock of the previous sampling period, and outputting the duration of the adjustment period generated according to the reference clock and the first clock,

The control module calculates an absolute value of a difference between a frequency of a reference clock of the last sample period and a frequency of a first clock of the last sample period to generate a frequency difference value;

The control module generates and outputs an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock.

The duration T of the adjustment period is l/(| R - D | x /R x N), where R is the frequency of the reference clock of the last adjustment period, and D is the first period of the previous adjustment period The frequency of the clock, M is the frequency of the second clock, and N is the total number of branches of the second clock.

The phase difference between the n-1th branch and the nth branch of the second clock is π /Ν, where η is the branch number of the second clock, 0≤n<N, and Ν is the second clock The total number of branches.

In another aspect, an apparatus for adjusting a frequency includes: a control module, a phase locked loop module, and a frequency synthesizing module; wherein

The control module is configured to: input a reference clock of the last sample period and a first clock of the last sample period output by the frequency synthesis module, and output an adjustment period generated according to the reference clock and the first clock Length of time;

The phase-locked loop module is configured to: input a source clock of a current sampling period, and output a second clock of a current sampling period according to a preset multiplication factor, and each of the branches has a predetermined phase difference; and

The frequency synthesis module is configured to: input the second clock, and select the second clock in sequence Each of the branches, and frequency synthesis according to the duration of the adjustment period and the preset frequency coefficient, and outputs the first clock of the current adjustment period.

The control module is further configured to: configure a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock; configured to configure the frequency according to an accuracy requirement of a frequency of the first clock a total number of branches of the second clock and a phase difference between the branches of the second clock; and configuring the combination of the frequency synthesis module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop Frequency factor.

The frequency synthesis module includes:

a receiving submodule, configured to receive a duration of the adjustment period from the control module; and a determining submodule configured to determine whether the branch of the second clock selected by the last adjustment period is the last path, and generate a determination result ;

a switching sub-module, configured to switch to the first branch of the second clock when the determination result is that the branch of the second clock selected by the last adjustment period is the last one, when the determination result Switching to the next branch of the second clock when the branch of the second clock selected for the last adjustment period is not the last one;

a frequency synthesizing subunit, configured to: when the judging result is that the branch of the second clock selected in the last adjustment period is the last one, the frequency is performed by the first branch of the second clock of the current adjustment period Synthesizing; when the result of the determination is that the branch of the second clock selected in the previous adjustment period is not the last one, the frequency is synthesized by the next branch of the second clock of the current adjustment period; the timing sub-module, It is set to enter the next adjustment period after the duration of the adjustment period. The frequency synthesizing subunit is further configured to output a square wave;

When the result of the determination is that the branch of the second clock selected in the last adjustment period is the last one, the number of occurrences of the rising edge of the first branch of the second clock of the current adjustment period reaches the sum Triggering the high level of the square wave; when the number of falling edges of the first branch of the second clock of the current adjustment period reaches the reciprocal of the combining coefficient, triggering the Square wave level;

When the result of the determination is that the branch of the second clock selected in the last adjustment period is not the last one, when the rising edge of the next branch of the second clock of the current adjustment period occurs, the number of occurrences reaches a high level of the square wave when the reciprocal of the frequency combining coefficient is reached; when the number of falling edges of the next branch of the second clock of the current adjustment period reaches a reciprocal of the combining frequency coefficient, Triggering a low level of the square wave; the reciprocal of the combining frequency coefficient is a natural number.

The control module includes:

a phase detector module configured to calculate an absolute value of a difference between a frequency of a reference clock of the last sample period and a frequency of a first clock of the last sample period to generate a frequency difference value;

The adjustment submodule is configured to generate and output an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock. Embodiments of the present invention have the following beneficial effects:

In the above solution, according to the difference between the frequency of the first clock outputted by the previous cycle and the frequency of the reference clock, the frequency of the first clock of the output of the current adjustment period is adjusted, and the output frequency can be dynamically adjusted, which is relatively simple.

BRIEF abstract

1 is a schematic flow chart of an embodiment of a method for adjusting a frequency according to the present invention;

2 is a schematic flow chart of another embodiment of a method for adjusting a frequency according to the present invention; FIG. 3 is a schematic structural diagram of an embodiment of a frequency adjustment device according to the present invention; FIG. 5 is a schematic flow chart of an application scenario of the frequency adjustment device illustrated in FIG. 4;

Preferred embodiment of the invention

The technical problems, the technical solutions, and the advantages of the embodiments of the present invention will be more clearly described in the accompanying drawings.

As shown in FIG. 1 , an embodiment of a method for adjusting a frequency according to the present invention includes: Step 11: A control module configures the phase lock according to a frequency of the reference clock and a frequency of the source clock. The multiplication factor of the ring module;

Step 12: The control module configures the foregoing according to an accuracy requirement of a frequency of the first clock a total number of branches of the second clock and a phase difference between the branches of the second clock;

Step 13: The control module configures a frequency combining coefficient of the frequency synthesizing module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop.

Step 14. The frequency synthesizing module outputs a first clock of the last sampling period, and the control module inputs a reference clock of the last sampling period and a first clock of the previous sampling period, and outputs the reference clock according to the reference clock. The length of the adjustment period generated by the first clock;

Step 15. The phase-locked loop module inputs a source clock of the current sampling period, and outputs a second clock of a current sampling period according to a preset multiplication factor, and each branch has a predetermined phase difference; and then respectively jumps Go to step 16 and step 14; in step 14, start the loop from the next sample cycle; step 16, the frequency synthesis module inputs the second clock, and sequentially selects each branch of the second clock, according to the The duration of the adjustment period and the preset combination coefficient are used for frequency synthesis, and the first clock of the current adjustment period is output.

The duration T of the adjustment period is l/(| R - D | x /RxN), where R is the frequency of the reference clock of the last adjustment period, and D is the first clock of the previous adjustment period Frequency, M is the frequency of the second clock, and N is the total number of branches of the second clock. Among them, the last adjustment period is the previous sampling period.

The phase difference between the n-1th branch and the nth branch of the second clock is π /Ν, where η is the branch number of the second clock, 0≤n<N, and Ν is the second clock The total number of branches. As shown in FIG. 2, another embodiment of a method for adjusting a frequency according to the present invention includes: Step 21: A control module configures the lock according to a frequency of the reference clock and a frequency of the source clock. a multiplication factor of the phase loop module, the multiplication factor being a positive integer;

Step 22: The control module configures a total number of branches of the second clock and a phase difference between each branch of the second clock according to an accuracy requirement of a frequency of the first clock.

Step 23: The control module configures a frequency combining coefficient of the frequency synthesizing module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop, where the combining frequency coefficient is a reciprocal of a positive integer.

Step 24: The control module inputs a reference clock of the last sample period and a first clock of the last sample period output by the frequency synthesis module, and outputs a duration of the adjustment period generated according to the reference clock and the first clock;

Step 25: The phase-locked loop module inputs a source clock of the current sampling period, and outputs a second clock of a current sampling period according to a preset multiplication factor, and each branch has a predetermined phase difference; and then respectively jumps Go to step 26 and step 24; in step 24, start the loop from the next sample cycle; step 26, the frequency synthesis module receives the duration of the adjustment period from the control module; step 27, the frequency synthesis The module determines whether the branch of the second clock selected in the last adjustment period is the last one, if yes, proceed to step 28, otherwise proceed to step 29;

Step 28: Switch to the first branch of the second clock, perform frequency synthesis by the first branch of the second clock of the current adjustment period, and then proceed to step 210; Step 29, switch to the second clock The next branch, the frequency is synthesized by the next branch of the second clock of the current adjustment period, and then proceeds to step 210;

Step 210: After the duration of the adjustment period, enter the next adjustment period, and then jump to step 26. In step 26, the loop begins from the next adjustment period.

The step of performing frequency synthesis by the first branch of the second clock of the current adjustment period is specifically:

Outputting a square wave, when the number of rising edges of the first branch of the second clock of the current adjustment period reaches the frequency combination coefficient, triggering a high level of the square wave; when the current adjustment period is When the number of falling edges of the first branch of the second clock reaches the reciprocal of the combining coefficient, triggering the low level of the square wave; The step of performing frequency synthesis by the next branch of the second clock of the current adjustment period is specifically:

Outputting a square wave, when the number of rising edges of the next branch of the second clock of the current adjustment period reaches the combined frequency coefficient, triggering a high level of the square wave; when the current adjustment period is When the number of falling edges of the next branch of the second clock reaches the reciprocal of the combining coefficient, the low level of the square wave is triggered; the reciprocal of the combining coefficient is a natural number.

The application scenario of the method for adjusting the frequency according to the present invention is described below. 4: The frequency of the source clock output from the clock source is S Hz, the phase-locked loop outputs the second clock with the frequency of N, and the frequency of the adjusted first clock generated according to the second clock with the frequency of MHz is D. Hz, the preset frequency of the reference frequency is RHz. The method includes the following steps:

Step 1: Adjust the phase and frequency of the second clock whose output frequency is the MHz of the phase-locked loop to be an integer multiple of the frequency of the reference clock, and the clock phase of the first branch of the second clock is 0 degrees. The clock phase of the second branch is π/Ν, the clock phase of the third branch is 2π/Ν... and so on, and the clock phase of the second branch is (Ν-1) π/Ν. First using the first shunt clock to generate a first clock with a frequency of D Hz;

Step 2: Perform phase discrimination with the first clock of the adjusted D Hz using a reference clock with a preset frequency of R Hz, and obtain a frequency difference (RD) Hz of the two clocks; calculate according to the frequency difference (RD) Hz The compensation value of the first clock D Hz, the compensation formula is as follows: The number of compensations per second | ?-/)|>^/^ , the frequency difference of each compensation R / (MxN) Hz; The frequency difference of each compensation indicates the adjustment frequency Accuracy; Step 3, smooth transition to the next shunt clock count to output the first clock with a frequency of D Hz, if the current N-th branch clock counts, jump to the first shunt clock for counting;

Step 4. Repeat step 3 after adjusting the period l/(|R-D|x /RxN) seconds.

As shown in FIG. 3, a frequency adjustment device according to the present invention includes: a control module 31, a phase locked loop module 32, and a frequency synthesizing module 33.

The control module 31 is configured to: input a reference clock of the last sample period and a first clock of the last sample period output by the frequency synthesis module, and output an adjustment period generated according to the reference clock and the first clock duration;

The phase locked loop module 32 is configured to: input a source clock of the current sampling period, according to a preset multiple a frequency coefficient, a second clock that outputs a predetermined total number of branches and each of the branches has a predetermined phase difference of the current sampling period;

The frequency synthesizing module 33 is configured to: input the second clock, sequentially select each branch of the second clock, perform frequency synthesis according to the duration of the adjustment period, a preset combining frequency coefficient, and output current adjustment The first clock of the cycle.

The control module 31 is further configured to: configure a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock; configured to configure the frequency according to a frequency accuracy requirement of the first clock a total number of branches of the second clock and a phase difference between the branches of the second clock; and configuring the combination of the frequency synthesis module according to a frequency of the reference clock and a frequency multiplication coefficient of the phase locked loop Frequency factor.

The control module 31 includes:

The adjustment submodule is configured to generate and output an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock. The frequency synthesis module 33 includes:

a switching sub-module, configured to switch to the first branch of the second clock when the determination result is that the branch of the second clock selected by the last adjustment period is the last one, when the determination result Switching to the next branch of the second clock when the branch of the second clock selected for the last adjustment period is not the last one; the frequency synthesizing subunit, which is set to be the last adjustment when the judgment result is The first branch of the second clock of the current adjustment period when the branch of the second clock of the period selection is the last one Performing frequency synthesis; when the result of the determination is that the branch of the second clock selected in the last adjustment period is not the last one, the frequency is synthesized by the next branch of the second clock of the current adjustment period; The module is set to enter the next adjustment period after the duration of the adjustment period. The frequency synthesis subunit is also arranged to output a square wave. Specifically, when the determining result is that the branch of the second clock selected in the last adjustment period is the last one, when the rising edge of the first branch of the second clock of the current adjustment period occurs, the number of occurrences reaches a high level of the square wave when the reciprocal of the frequency combining coefficient is reached; when the number of falling edges of the first branch of the second clock of the current adjustment period reaches a reciprocal of the combining frequency coefficient, Triggering a low level of the square wave; when the determining result is that the branch of the second clock selected in the last adjustment period is not the last one, when the next branch of the second clock of the current adjustment period When the number of rising edges of the rising edge reaches the reciprocal of the combining frequency coefficient, the high level of the square wave is triggered; when the falling edge of the next branch of the second clock of the current adjustment period occurs, the number reaches When the reciprocal of the combining coefficient is used, the low level of the square wave is triggered; the reciprocal of the combining coefficient is a natural number.

4 is a schematic structural diagram of another embodiment of the apparatus for adjusting frequency according to the present invention; in the apparatus for adjusting frequency according to the present invention, the phase detecting sub-module 41 is configured to perform phase-collection statistics on the synthesized frequency and the reference clock. The adjustment sub-module 42 initializes the phase-locked loop module, sends configuration information (such as a multiplication factor, etc.) to the phase-locked loop, and dynamically adjusts the adjustment information of the frequency synthesis module according to the phase-detection result (for example, a frequency-combination coefficient, etc.); The ring module 43 is for multiplying the source clock of the clock source to a higher frequency; the frequency synthesis module 44 is configured to generate the second clock of the high frequency to generate the first clock of the low frequency. FIG. 5 is a schematic flow chart of an application scenario of the device for adjusting frequency according to FIG. The following description describes the application scenario of the frequency synthesizing apparatus according to the present invention with reference to Figs. 4 and 5.

Step 51: Configure the second clock outputted by the phase-locked loop module 43 to be 200 MHz according to the reference clock 5.0000001 MHz, so that the second clock is a common multiple of the reference clock and the source clock. (In this application scenario, the integer bit of the reference clock frequency is selected. ), configuring the input and output points of the frequency synthesis module 44 Don't be 200MHz and 5MHz, 5ΜΗζ is first generated by the first branch count of the second clock. There are 4 second clocks for adjustment; that is, the multiplication factor is 20 and the combining frequency is 1/40.

Step 52, the phase detector sub-module 41 performs phase-collecting statistics on the 5 MHz first clock and the reference clock 5.0000001 MHz output by the frequency synthesizing module 44;

Step 53: The adjustment sub-module 42 processes the phase-detection value, and calculates the compensation times per second and the compensated frequency difference of the frequency synthesis module 44 according to the above, which are 16 times and 0.00625 Hz respectively; Step 54 The sub-module 42 sends the adjustment information to the frequency synthesis module 44, and updates in real time according to the latest preset reference clock;

Step 55, the frequency synthesis module 44 according to the adjustment information to obtain an adjustment interval of 0.0625 seconds; Step 56, determine whether the current 5MHz is the fourth clock count, if yes, proceed to step 57, otherwise proceed to step 58;

Step 57, the 5MHz clock is switched from the second clock count to the first split clock count, and step 59 is performed;

Step 58, the 5MHz clock is switched from the second clock count to the next split clock count, and step 59 is performed;

Step 59: After adjusting the period of time, proceed to step 55.

The present invention provides a method and apparatus for adjusting a frequency that dynamically adjusts the clock source frequency.合成 Combine high frequency clocks with multiple different phases to synthesize low frequency clocks. Not only can high-precision frequency synthesis be achieved, but also low-frequency fine-tuning can be achieved. It can effectively improve the performance and performance indicators such as the accuracy and stability of the output clock, reduce the overall cost of the clock system, and can be used in various clock frequency recovery applications, with a strong versatility. In the above embodiment, H has no clock source of 10 MHz, and the clock source has an adjustment range of 10 MHz ± 50 Hz, and when 10 MHz + 60 Hz is desired. Due to the limited adjustment range of the clock source itself, this frequency is not achieved, and the common phase-locked loop corresponds to an input frequency of 10 MHz ± 50 Hz. In the above way, it is easy to implement.

The frequency multiplication coefficient of the phase locked loop is a ratio between the frequency of the output clock of the phase locked loop and the frequency of the input clock, and may be a positive integer; the frequency combining coefficient of the frequency synthesizing module is the output clock of the frequency synthesizing module. The ratio between the frequency and the frequency of the input clock can be the reciprocal of a positive integer. The method embodiment is corresponding to the device embodiment, and the portion not described in detail in the method embodiment may refer to the description of the relevant part in the device embodiment, and the partial reference method not described in detail in the device embodiment. The description of the relevant parts in the embodiment can be.

It will be understood by those skilled in the art that all or part of the steps of the foregoing embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium. When executed, the method includes the steps of the foregoing method embodiment, such as: a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (No. RAM) and so on.

In the method embodiments of the present invention, the sequence numbers of the steps are not used to limit the sequence of the steps. For those skilled in the art, the steps of the steps are changed without any creative work. It is also within the scope of the invention.

The above is a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It should be considered as the scope of protection of the present invention.

INDUSTRIAL APPLICABILITY The method and apparatus for adjusting a frequency provided by the present invention can dynamically adjust a clock source frequency. 合成 Combining a plurality of high-frequency clocks of different phases to synthesize a low-frequency clock can realize not only high-precision frequency synthesis but also low frequency. The fine adjustment can effectively improve the performance and performance indexes of the output clock, reduce the overall cost of the clock system, and can be used in various clock frequency recovery applications, and has strong versatility.

Claims

Claim

1. A method of adjusting frequency, including:

The frequency synthesizing module inputs the second clock, sequentially selects each branch of the second clock, performs frequency synthesis according to the duration of the adjustment period, a preset combining frequency coefficient, and outputs a first clock of the current adjustment period. .

2. The method of adjusting a frequency according to claim 1, wherein the frequency synthesizing module outputs a first clock of a last sampling period, and the control module inputs a reference clock of the last sampling period and the previous one The first clock of the sample period, before the step of outputting the length of the adjustment period generated according to the reference clock and the first clock, the method further includes:

The control module configures a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock;

The method for adjusting a frequency according to claim 1, wherein the frequency synthesizing module inputs the second clock, and sequentially selects each branch of the second clock, according to the duration of the adjustment period, preset The frequency combining coefficient performs frequency synthesis, and the steps of outputting the first clock of the current adjustment period include:

Step 31: The frequency synthesizing module receives the duration of the adjustment period from the control module. Step 32: The frequency synthesizing module determines whether the branch of the second clock selected in the last adjustment period is the last one, if The split of the second clock selected in the last adjustment period is the last one Then proceed to step 33, if the branch of the second clock selected in the last adjustment period is not the last one, proceed to step 34;

4. The method of adjusting a frequency according to claim 3, wherein

Outputting a square wave, when the number of rising edges of the first branch of the second clock of the current adjustment period reaches a reciprocal of the combining coefficient, triggering a high level of the square wave; when the current adjustment period is The low level of the square wave is triggered when the number of falling edges of the first branch of the second clock reaches the reciprocal of the combining frequency coefficient;

The method for adjusting a frequency according to claim 3, wherein the control module inputs a reference clock of a last sampling period and a first clock of the last sampling period, and outputs according to the reference clock and the The steps of the duration of the adjustment period generated by the first clock include:

6. The method of adjusting a frequency according to claim 5, wherein a duration of the adjustment period T is l/(| R - D | xMRxN) , where R is the frequency of the reference clock of the last adjustment period, D is the frequency of the first clock of the last adjustment period, and M is the second The frequency of the clock, N is the total number of branches of the second clock.

The method for adjusting a frequency according to claim 3, wherein a phase difference between an n-1th branch and an nth branch of the second clock is π /Ν, where η is a second clock The serial number of the branch,

0<n<N, Ν is the total number of branches of the second clock.

8. A device for adjusting a frequency, comprising: a control module, a phase locked loop module, and a frequency synthesizing module; wherein

The frequency synthesizing module is configured to: input the second clock, sequentially select each branch of the second clock, perform frequency synthesis according to the duration of the adjustment period, a preset frequency combination coefficient, and output a current adjustment period. The first clock.

The apparatus for adjusting a frequency according to claim 8, wherein the control module is further configured to: configure a frequency multiplication coefficient of the phase locked loop module according to a frequency of the reference clock and a frequency of the source clock Configuring a total number of branches of the second clock and a phase difference between the branches of the second clock according to an accuracy requirement of a frequency of the first clock; and according to a frequency of the reference clock and the The multiplication factor of the phase locked loop, and the frequency combining coefficient of the frequency synthesis module is configured.

10. The apparatus for adjusting a frequency according to claim 8, wherein the frequency synthesizing module comprises:

a switching submodule, configured to be the second selected when the determination result is the last adjustment period When the branch of the clock is the last one, switching to the first branch of the second clock, when the result of the determination is that the branch of the second clock selected in the previous adjustment period is not the last one, switch to the a next branch of the second clock; a frequency synthesizing subunit configured to be configured by the current adjustment period when the branch of the second clock selected by the determination result is the last one of the last adjustment period The first branch of the second clock performs frequency synthesis; when the result of the determination is that the branch of the second clock selected in the previous adjustment period is not the last one, the next clock of the current adjustment period is next The frequency division performs frequency synthesis; the timing sub-module is set to enter the next adjustment period after the duration of the adjustment period.

11. The apparatus for adjusting a frequency according to claim 10, wherein the frequency synthesizing subunit is further configured to output a square wave;

When the result of the determination is that the branch of the second clock selected in the last adjustment period is the last one, the number of occurrences of the rising edge of the first branch of the second clock of the current adjustment period reaches the sum Triggering the high level of the square wave; when the number of falling edges of the first branch of the second clock of the current adjustment period reaches the reciprocal of the combining coefficient, triggering the Square wave low level;

When the result of the determination is that the branch of the second clock selected in the last adjustment period is not the last one, the number of occurrences of the rising edge of the next branch of the second clock of the current adjustment period reaches the sum Triggering the high level of the square wave; when the number of falling edges of the next branch of the second clock of the current adjustment period reaches the reciprocal of the combining coefficient, triggering the The low level of the square wave; the reciprocal of the combined frequency coefficient is a natural number.

12. The frequency adjustment apparatus of claim 10, wherein the control module comprises: a phase discrimination sub-module configured to calculate a frequency of the reference clock of the last sample period and the previous sample Generating a frequency difference value by the absolute value of the difference between the frequencies of the first clock of the cycle;

The adjustment submodule is configured to generate and output an adjustment period according to the frequency difference, the frequency of the second clock, the total number of branches of the second clock, and the frequency of the reference clock.