WO2011118308A1 - Élément de condensateur, substrat avec condensateur intégré, feuille d'élément, et procédés de fabrication de ceux-ci - Google Patents

Élément de condensateur, substrat avec condensateur intégré, feuille d'élément, et procédés de fabrication de ceux-ci Download PDF

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Publication number
WO2011118308A1
WO2011118308A1 PCT/JP2011/053640 JP2011053640W WO2011118308A1 WO 2011118308 A1 WO2011118308 A1 WO 2011118308A1 JP 2011053640 W JP2011053640 W JP 2011053640W WO 2011118308 A1 WO2011118308 A1 WO 2011118308A1
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Prior art keywords
layer
electrode layer
metal
dielectric layer
capacitor
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PCT/JP2011/053640
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English (en)
Japanese (ja)
Inventor
仁志 野口
直樹 田中
達也 仲村
賢一 江崎
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三洋電機株式会社
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Publication of WO2011118308A1 publication Critical patent/WO2011118308A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/10—Metal-oxide dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/236—Terminals leading through the housing, i.e. lead-through
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672—Superposed layout, i.e. in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points

Definitions

  • the present invention relates to a capacitor element, a capacitor-embedded substrate including the capacitor element, an element sheet that can be used for manufacturing the capacitor-embedded substrate, and a method for manufacturing these.
  • capacitors are provided at a plurality of locations in a surface region (305) (upper surface in FIG. 36, hereinafter referred to as “upper surface”) on which a semiconductor element such as a CPU is mounted.
  • a ground terminal (306) and a power supply terminal (307) to which both electrode layers (301) and (302) of the element (300) are to be electrically connected are formed.
  • the capacitor element (300) is embedded in the insulating substrate (304) so that both electrode layers (301) and (302) are substantially parallel to the upper surface (305) of the insulating substrate (304).
  • the first electrode layer (301) and each ground terminal (306) are electrically connected to each other through conductive vias (308) and (309) formed in the insulating substrate (304).
  • the second electrode layer (302) of (300) and each power supply terminal (307) are electrically connected to each other through a conductive via (310) formed in the insulating substrate (304).
  • the dielectric layer (303) is formed on the first electrode layer (301) by using various known film forming methods such as a sol-gel method, a sputtering method, and a vacuum deposition method (for example, Patent Document 2). reference).
  • film forming methods such as a sol-gel method, a sputtering method, and a vacuum deposition method (for example, Patent Document 2). reference).
  • a sol-gel method for example, a sputtering method
  • a vacuum deposition method for example, Patent Document 2). reference.
  • pinholes and cracks are likely to occur in the dielectric layer (303). Therefore, when the second electrode layer (302) is formed directly on the dielectric layer (303), part of the metal constituting the second conductive layer (302) penetrates into the pinhole or crack, As a result, the electrical insulation resistance between the electrode layers (301) and (302) may be significantly reduced.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas. Therefore, when the dielectric layer (303) is formed on the first electrode layer (301) using the powder spray coating method, the powdered dielectric material collides with the surface of the first electrode layer (301), As a result, the surface of the first electrode layer (301) is damaged.
  • the film thickness of the dielectric layer (303) becomes non-uniform. Accordingly, the film thickness is remarkably reduced in a part of the dielectric layer (303), or a part of the first electrode layer (301) is exposed on the surface of the dielectric layer (303), so that both electrode layers (301 ) (302), there is a risk that the electrical insulation resistance will be significantly reduced.
  • the first electrode layer (301) and the second electrode layer (302) of the capacitor element (300) have the same shape. For this reason, among the electrode layers (301) and (302), the electrical connection between the second electrode layer (302) close to the upper surface (305) of the insulating substrate (304) and each power supply terminal (307) While only one conductive via (310) needs to be formed, the electrical connection between the first electrode layer (301) far from the upper surface (305) of the insulating substrate (304) and each ground terminal (306). It was necessary to form two conductive vias (308) and (309).
  • one conductive via (308) is electrically connected to the lower surface (312) of the first electrode layer (301) and the other conductive via (308).
  • the via (309) is electrically connected to the ground terminal (306) on the insulating substrate (304), and both conductive vias (308) and (309) extend to the lower surface (311) of the insulating substrate (304). Thus, they are electrically connected to each other by connection terminals (313) formed on the lower surface (311).
  • the capacitor built-in substrate an electrical path is formed between the ground terminal (306) and the power supply terminal (307) via the capacitor element (300).
  • the first electrode layer (301) and the ground terminal (306) of the capacitor element (300) are connected to the two conductive vias (308) and (309) and the connection terminal (313). ) And had to be electrically connected.
  • the conventional circuit board with a built-in capacitor has a long electrical path, and as a result, the inductance generated in the circuit board with a built-in capacitor is large.
  • an object of the present invention is to provide a capacitor element in which the electrical insulation resistance between two electrode layers is not easily lowered, a capacitor built-in substrate provided with the capacitor element, an element sheet that can be used for manufacturing the capacitor built-in substrate, It is to provide a manufacturing method.
  • the capacitor element according to the present invention includes a first electrode layer, a dielectric layer formed on the first electrode layer, and a second electrode layer formed on the dielectric layer.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • the powdered dielectric material violently collides with the metal layer, while the first electrode layer is protected from the collision of the dielectric material by the metal layer. become. Therefore, the surface of the first electrode layer is hardly damaged, and unevenness is hardly formed on the surface of the first electrode layer.
  • the metal layer is not easily damaged by the collision of the powdery dielectric material. Therefore, it is difficult for irregularities to be formed on the surface of the metal layer, and as a result, the electrical insulation resistance between the first electrode layer and the second electrode layer is difficult to decrease.
  • an oxide film is interposed between the metal layer and the dielectric layer. Therefore, even when pinholes or cracks are generated in the dielectric layer, the oxide film prevents electrical breakdown between the first electrode layer and the second electrode layer. Even when unevenness is formed on the surface of the metal layer by forming the dielectric layer using the powder spray coating method, the electrical film between the first electrode layer and the second electrode layer is formed by the oxide film. Therefore, a proper dielectric breakdown is prevented.
  • an oxide film of a metal layer containing aluminum, tantalum, niobium, or nickel as a main component has high insulating properties.
  • the first electrode layer includes copper as a main component
  • the metal layer includes nickel as a main component.
  • the metal layer can be easily formed on the surface of the first electrode layer using plating.
  • the adhesion between the first electrode layer and the metal layer is improved.
  • nickel has a particularly good insulating property of its oxide film compared to other metals.
  • Another capacitor element according to the present invention includes a first electrode layer, a dielectric layer formed on the first electrode layer, and a second electrode layer formed on the dielectric layer.
  • the first electrode layer includes, as a main component, one or more metals selected from the group consisting of aluminum, titanium, tantalum, niobium, nickel, and copper, and between the first electrode layer and the dielectric layer. Intervenes an oxide film formed by oxidizing the surface of the first electrode layer on the dielectric layer side.
  • a film forming method such as a sol-gel method, a sputtering method, a vacuum deposition method, or a powder injection coating method is used.
  • a dielectric layer is formed using a sol-gel method, a sputtering method, or a vacuum evaporation method, pinholes and cracks are likely to occur in the dielectric layer.
  • an oxide film is interposed between the first electrode layer and the dielectric layer. Therefore, even when pinholes or cracks are generated in the dielectric layer, the oxide film prevents electrical breakdown between the first electrode layer and the second electrode layer.
  • the oxide film forms the first electrode layer and the second electrode layer. Electrical breakdown between them is prevented.
  • the oxide film of the first electrode layer containing aluminum, tantalum, niobium, or nickel as a main component has high insulating properties.
  • Still another capacitor element according to the present invention includes a first electrode layer, a dielectric layer formed on the first electrode layer, and a second electrode layer formed on the dielectric layer.
  • a metal layer containing at least one metal selected from the group consisting of aluminum, titanium, tantalum, niobium, nickel, and copper as a main component is interposed between the first electrode layer and the dielectric layer.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • the powdered dielectric material violently collides with the metal layer, while the first electrode layer is protected from the collision of the dielectric material by the metal layer. become. Therefore, the surface of the first electrode layer is hardly damaged, and unevenness is hardly formed on the surface of the first electrode layer.
  • the metal layer is not easily damaged by the collision of the powdery dielectric material. Therefore, it is difficult for irregularities to be formed on the surface of the metal layer, and as a result, the electrical insulation resistance between the first electrode layer and the second electrode layer is difficult to decrease.
  • the first electrode layer includes copper as a main component
  • the metal layer includes nickel as a main component. According to the metal combination of copper composing the first electrode layer and nickel composing the metal layer, the metal layer can be easily formed on the surface of the first electrode layer using plating. In addition, the adhesion between the first electrode layer and the metal layer is improved.
  • the first electrode layer is partially covered by the second electrode layer, and the first electrode layer is formed of a metal foil.
  • the second electrode layer is formed of a metal thin film or a metal foil.
  • a substrate with a built-in capacitor in which the capacitor element is built in the insulating substrate has been manufactured.
  • a conductive via electrically connected to a surface of the second electrode layer opposite to the first electrode layer is formed on the insulating substrate, and the conductive via is formed on the surface of the insulating substrate.
  • it extends toward the surface region on the second electrode layer side of the capacitor element, and the tip end portion of the conductive via extending from the second electrode layer is exposed in the surface region.
  • a region not covered with the second electrode layer is formed on the surface of the first electrode layer on the second electrode layer side. Therefore, in the capacitor built-in substrate, a conductive via electrically connected to the region is formed, and the conductive via is not in electrical contact with the second electrode layer. Extending toward the surface region on the second electrode layer side (that is, the same region as the surface region where the tip of the conductive via extending from the second electrode layer is exposed) The leading end of the extended conductive via can be exposed.
  • a capacitor-embedded substrate manufactured as described above using the capacitor element according to the present invention has a conventional capacitor-embedded substrate, specifically, a conductive via to be electrically connected to the first electrode layer is formed on the insulating substrate.
  • the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced.
  • the first electrode layer is provided with a second electrode layer via the dielectric layer at a plurality of locations on the surface on the second electrode layer side, The second electrode layers are separated from each other.
  • the capacitor built-in substrate according to the present invention includes any of the capacitor elements described above and an insulating substrate, and the capacitor element is embedded in the insulating substrate by embedding the capacitor element in the insulating substrate.
  • a method of manufacturing a capacitor element according to the present invention includes a first electrode layer, a dielectric layer formed on the first electrode layer, and a second electrode layer formed on the dielectric layer.
  • a method for manufacturing an element which includes a metal layer forming step, a dielectric layer forming step, and an electrode layer forming step.
  • a metal layer containing as a main component one or more metals selected from the group consisting of aluminum, titanium, tantalum, niobium, nickel, and copper is formed on the first electrode layer.
  • the dielectric layer forming step the dielectric layer is formed on the metal layer using a powder spray coating method.
  • the electrode layer forming step the second electrode layer is formed on the dielectric layer.
  • the dielectric layer is formed on the metal layer in the dielectric layer forming step.
  • the powder spray coating method used for forming the dielectric layer forms a thin film on the target by spraying various powders mixed in the gas onto the target using the flow of the gas. This is a film forming method. Therefore, in the dielectric layer forming step, the powdery dielectric material collides with the metal layer and is crushed, and the powdery dielectric material collides with the metal layer and is crushed. As a result, the metal layer On top of this, a fine dielectric material is densely deposited to form a dielectric layer.
  • the powdery dielectric material violently collides with the metal layer, while the first electrode layer is protected from the collision of the dielectric material by the metal layer. Therefore, the surface of the first electrode layer is hardly damaged, and unevenness is hardly formed on the surface of the first electrode layer.
  • the metal layer is not easily damaged by the collision of the powdery dielectric material. Therefore, it is difficult for irregularities to be formed on the surface of the metal layer, and as a result, the electrical insulation resistance between the first electrode layer and the second electrode layer is difficult to decrease.
  • the manufacturing method includes performing a chemical conversion treatment or a heat treatment on the surface of the metal layer after performing the metal layer forming step of forming the metal layer. It further has an oxidation treatment step of oxidizing the substrate to form an oxide film.
  • an oxide film is interposed between the first electrode layer and the dielectric layer in the manufactured capacitor element. Therefore, even when unevenness is formed on the surface of the metal layer by forming the dielectric layer using the powder spray coating method, the oxide film causes a gap between the first electrode layer and the second electrode layer. Electrical breakdown is prevented.
  • an oxide film of a metal layer containing aluminum, tantalum, niobium, or nickel as a main component has high insulating properties.
  • the method for manufacturing a capacitor-embedded substrate according to the present invention includes an element sheet manufacturing step, a pasting step, an etching step, and a laminating step.
  • the capacitor-embedded substrate includes one or a plurality of capacitor elements having a dielectric layer interposed between the first electrode layer and the second electrode layer, and an insulating substrate, and the capacitor element is embedded in the insulating substrate.
  • a capacitor element is built in the insulating substrate.
  • using metal foil, aluminum, titanium, tantalum, niobium, nickel on one or a plurality of predetermined regions to be the first electrode layer of the one or more capacitor elements in the metal foil.
  • a metal layer containing one or more metals selected from the group consisting of copper as a main component By forming a second metal layer to be the second electrode layer on the body layer, a predetermined region of the metal foil, a metal layer formed on the predetermined region, and a metal layer formed on the metal layer
  • An element sheet having one or a plurality of element portions each including a dielectric layer and a second metal layer formed on the dielectric layer is produced.
  • the element sheet is affixed on one insulating base material among the two insulating base materials constituting the insulating substrate.
  • the metal foil is etched to leave the one or more predetermined regions on the one insulating base material, so that one or more elements of the element sheet are formed on the one insulating substrate.
  • the one or a plurality of capacitor elements each having a portion are formed.
  • the insulating substrate is formed by laminating the other insulating base material on the one insulating base material.
  • the capacitor element is mounted at a predetermined position on the insulating substrate.
  • the dielectric layer is formed using a powder spray coating method.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • a dielectric layer having a desired film formation area and / or a desired thickness is formed in a predetermined region regardless of whether or not the surface of the metal foil or metal layer is masked. Is possible. Therefore, even when a dielectric layer is formed on a plurality of predetermined regions of the metal foil, the film formation area and / or thickness dimension of the dielectric layer can be changed for each predetermined region, and the change can be easily performed. Can be done. Further, according to the powder spray coating method, the type of dielectric material sprayed for each predetermined region can be changed, and the change can be easily performed.
  • a capacitor element having a desired capacitance can be mounted at a predetermined position on the insulating substrate. For this reason, even when the design related to the capacitance of the capacitor element is changed, at least one of the type of dielectric material constituting the dielectric layer, the film formation area of the dielectric layer, and the thickness dimension of the dielectric layer is changed. There is no need to redesign the arrangement of the capacitor elements.
  • the dielectric layer can be formed without masking the metal foil or the metal layer, and therefore the yield of the capacitor built-in substrate can be improved.
  • the dielectric layer is formed on the metal layer using the powder spray coating method in the dielectric layer forming step.
  • a body layer is formed. Therefore, in the dielectric layer forming step, the powdery dielectric material collides with the metal layer and is crushed, and the powdery dielectric material collides with the metal layer and is crushed. As a result, the metal layer On top of this, a fine dielectric material is densely deposited to form a dielectric layer.
  • the powdery dielectric material violently collides with the metal layer, while the first electrode layer is protected from the collision of the dielectric material by the metal layer. Therefore, the surface of the first electrode layer is hardly damaged, and unevenness is hardly formed on the surface of the first electrode layer.
  • the metal layer is not easily damaged by the collision of the powdery dielectric material. Therefore, it is difficult for irregularities to be formed on the surface of the metal layer, and as a result, the electrical insulation resistance between the first electrode layer and the second electrode layer is difficult to decrease.
  • the capacitor element mounted on the insulating substrate in the above manufacturing method has a small thickness dimension and is in the form of a sheet.
  • Such a capacitor element requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements on the insulating base material becomes complicated.
  • the capacitor element is formed by performing the etching process, and the capacitor element is handled as an element sheet until the etching process is performed. Therefore, it is not necessary to handle the capacitor elements individually, and the process of mounting the capacitor elements on the insulating substrate is simplified.
  • the metal layer, the dielectric layer, and the second metal layer of the element portion to be the capacitor element are formed on the metal foil.
  • an element sheet is produced. Therefore, it is not necessary to form the metal layer, dielectric layer, and second metal layer of the element portion on the insulating base material. Therefore, there is no possibility that the dielectric material or the metal material for forming the dielectric layer and the metal layer is mixed into another component such as an insulating base material. Further, even when it is necessary to perform a heat treatment to form the capacitor element, there is no possibility that the heat treatment adversely affects another component.
  • the surface of the metal layer is oxidized by subjecting the surface of the metal layer to chemical conversion or heat treatment. To form an oxide film.
  • the oxide film is interposed between the first electrode layer and the dielectric layer. Therefore, even when unevenness is formed on the surface of the metal layer by forming the dielectric layer using the powder spray coating method, the oxide film causes a gap between the first electrode layer and the second electrode layer. Electrical breakdown is prevented.
  • an oxide film of a metal layer containing aluminum, tantalum, niobium, or nickel as a main component has high insulating properties.
  • the element sheet according to the present invention has one or a plurality of element portions to be one or a plurality of capacitor elements in which a dielectric layer is interposed between the first electrode layer and the second electrode layer.
  • the element sheet is formed on a metal foil and one or more predetermined regions of the metal foil that serve as a first electrode layer of the one or more capacitor elements, and includes aluminum, titanium, tantalum, and niobium.
  • a second metal layer serving as a second electrode layer, and the element portion includes a predetermined region of the metal foil, the metal layer formed on the predetermined region, and the metal layer formed on the metal layer. It consists of a dielectric layer and the second metal layer formed on the dielectric layer.
  • the element sheet can be used as an element sheet manufactured in an element sheet manufacturing step included in the method for manufacturing a capacitor-embedded substrate.
  • an oxide film formed by oxidizing the surface of the metal layer on the dielectric layer side is interposed between the metal layer and the dielectric layer.
  • the element sheet manufacturing method produces an element sheet having one or more element portions to be one or more capacitor elements in which a dielectric layer is interposed between the first electrode layer and the second electrode layer. And a metal layer forming step, a dielectric layer forming step, and a second metal layer forming step.
  • a metal layer forming step using metal foil, aluminum, titanium, tantalum, or the like on one or more predetermined regions to be the first electrode layer of the one or more capacitor elements in the metal foil.
  • a metal layer containing as a main component one or more metals selected from the group consisting of niobium, nickel, and copper is formed.
  • a dielectric layer is formed on the metal layer using a powder spray coating method.
  • a second metal layer to be the second electrode layer is formed on the dielectric layer.
  • the element portion is formed on the predetermined region of the metal foil, the metal layer formed on the predetermined region, the dielectric layer formed on the metal layer, and the dielectric layer. And the second metal layer.
  • the element sheet manufacturing method can be used as an element sheet manufacturing step included in the capacitor-embedded substrate manufacturing method.
  • the capacitor-embedded substrate including the capacitor element, the element sheet that can be used for the manufacture of the capacitor-embedded board, and the manufacturing method thereof Insulation resistance is difficult to decrease.
  • FIG. 1 is a cross-sectional view showing a capacitor built-in substrate according to a first embodiment of the present invention.
  • FIG. 2 is a plan view of the capacitor element built in the capacitor built-in substrate as viewed from the second electrode layer side.
  • FIG. 3 is an enlarged cross-sectional view of a region near the interface between the first electrode layer and the dielectric layer of the capacitor element.
  • FIG. 4 is a diagram showing impedance characteristics of the capacitor built-in substrate.
  • FIG. 5 is a perspective view used for explaining the metal layer forming step in the method of manufacturing the capacitor element.
  • FIG. 6 is a perspective view used for explaining the dielectric layer forming step of the capacitor element manufacturing method.
  • FIG. 7 is a diagram showing a film forming apparatus used in the aerosol deposition method.
  • FIG. 1 is a cross-sectional view showing a capacitor built-in substrate according to a first embodiment of the present invention.
  • FIG. 2 is a plan view of the capacitor element built in the capacitor built-in substrate
  • FIG. 8 is a diagram showing a film forming apparatus used in the powder jet deposition method.
  • FIG. 9 is a perspective view used for explaining the annealing step in the method of manufacturing the capacitor element.
  • FIG. 10 is a perspective view used for explaining the resist forming step in the method of manufacturing the capacitor element.
  • FIG. 11 is a perspective view used for explaining the plating process of the capacitor element manufacturing method.
  • FIG. 12 is a plan view showing the state of the second sheet for element formation after execution of the plating step.
  • FIG. 13: is a top view used for description of the resist peeling process about the manufacturing method of the said capacitor
  • FIG. 14 is a plan view used for explaining the cutting step of the method for manufacturing the capacitor element.
  • FIG. 14 is a plan view used for explaining the cutting step of the method for manufacturing the capacitor element.
  • FIG. 15 is a perspective view used for description of the sticking process about the manufacturing method of the said board
  • FIG. 16 is a perspective view used for explaining the pre-stage of the peeling step in the method for manufacturing the capacitor built-in substrate.
  • FIG. 17 is a perspective view used for explaining the middle stage of the peeling process.
  • FIG. 18 is a perspective view used for explaining the latter stage of the peeling step.
  • FIG. 19 is a perspective view used for explaining the stacking process of the method for manufacturing the capacitor built-in substrate.
  • FIG. 20 is a plan view of the capacitor element built in the capacitor built-in substrate as viewed from the second electrode layer side in the first variation of the capacitor built-in substrate.
  • FIG. 21 is a plan view of the capacitor element built in the capacitor built-in substrate as viewed from the second electrode layer side in the second modification of the capacitor built-in substrate.
  • FIG. 22 is a sectional view showing a third modification of the capacitor built-in substrate.
  • FIG. 23 is a cross-sectional view showing a fourth modification of the capacitor built-in substrate.
  • FIG. 24 is an enlarged cross-sectional view of a region in the vicinity of the interface between the first electrode layer and the dielectric layer of the capacitor element built in the capacitor built-in substrate according to the second embodiment of the present invention.
  • FIG. 25 is an enlarged cross-sectional view of a region in the vicinity of the interface between the first electrode layer and the dielectric layer of the capacitor element built in the capacitor built-in substrate according to the third embodiment of the present invention.
  • FIG. 26 (a) is a perspective view used for explaining the dielectric layer forming step of another method for manufacturing the capacitor-embedded substrate
  • FIG. 26 (b) is a view shown in FIG. 26 (a). It is sectional drawing which follows the -B line.
  • FIG. 27 is a perspective view used for explaining the annealing step for another manufacturing method of the capacitor built-in substrate.
  • FIG. 28 is a perspective view used for explaining the resist forming process of another method for manufacturing the capacitor-embedded substrate.
  • FIG. 29 is a perspective view used for explaining the plating process of another manufacturing method of the capacitor built-in substrate.
  • FIG. 30 is a plan view showing the state of the second sheet for element formation after execution of the plating step.
  • FIG. 31 is a plan view used for explaining the resist stripping step for another method for manufacturing the capacitor-embedded substrate.
  • 32 is a cross-sectional view taken along the line CC shown in FIG.
  • FIG. 33 is a cross-sectional view used for explaining the attaching step for another method for manufacturing the substrate with a built-in capacitor.
  • FIG. 34 is a cross-sectional view used for explaining the etching process of another method for manufacturing the capacitor-embedded substrate.
  • FIG. 35 is a cross-sectional view used for explaining the stacking process of another method for manufacturing the capacitor-embedded substrate.
  • FIG. 36 is a cross-sectional view showing a conventional capacitor built-in substrate.
  • FIG. 37 is a cross-sectional view showing a conventional capacitor mounting board.
  • FIG. 1 is a sectional view showing a capacitor built-in substrate according to a first embodiment of the present invention.
  • the substrate with a built-in capacitor according to this embodiment includes an insulating substrate (2), and a capacitor element (1) is embedded in the insulating substrate (2), whereby the capacitor is placed on the insulating substrate (2).
  • the element (1) is built in.
  • the insulating substrate (2) is formed of a material having flame retardancy, for example, a material of FR-4 (Flame Retardant Type 4).
  • the material of FR-4 is a flame retardant material made of, for example, a composite material of glass fiber and epoxy resin.
  • the capacitor element (1) includes a first electrode layer (11), a dielectric layer (13) formed on the first electrode layer (11), and a first electrode formed on the dielectric layer (13).
  • Two electrode layers (12) are provided, and the surfaces of both electrode layers (11) and (12) are embedded in the insulating substrate (2) in a posture that is substantially parallel to the surface of the insulating substrate (2).
  • Dielectric layer (13) consists of barium titanate (BaTiO3), lithium niobate (LiNbO3), lithium borate (Li2B4O7), lead zirconate titanate (PbZrTiO3), strontium titanate (SrTiO3), lanthanum zirconate titanate It is made of various dielectric materials mainly composed of lead (PbLaZrTiO3), lithium tantalate (LiTaO3), zinc oxide (ZnO), tantalum oxide (Ta2O5) and the like.
  • the dielectric layer (13) may contain an additive to improve dielectric properties, insulating properties, strength, and the like.
  • the first electrode layer (11) of the capacitor element (1) is formed of a metal foil.
  • the metal foil is formed of a metal material that can form a foil and can be an electrode layer, such as copper (Cu), nickel (Ni), aluminum (Al), platinum (Pt), or the like.
  • the metal foil can be handled by itself, for example, can hold itself.
  • the thickness dimension of the metal foil is preferably 1 ⁇ m or more.
  • copper (Cu) is used as the metal material of the metal foil forming the first electrode layer (11).
  • the second electrode layer (12) of the capacitor element (1) is formed of a metal thin film.
  • the metal thin film is a metal film formed thinly on the surface of the base material such as the dielectric layer (13), and a thin film such as copper (Cu) can be formed and can be an electrode layer. It is formed from a metal material. Therefore, the metal thin film is difficult to handle by itself, and is handled integrally with the base material.
  • the thickness dimension of the metal thin film is preferably 20 ⁇ m or less.
  • copper (Cu) is used as the metal material of the metal thin film that forms the second electrode layer (12).
  • FIG. 2 is a plan view of the capacitor element (1) as seen from the second electrode layer (12) side.
  • the first electrode layer (11) of the capacitor element (1) has a surface (111) on the second electrode layer (12) side (upper surface in FIG. 1; hereinafter referred to as “upper surface”). Is covered with the second electrode layer (12).
  • the first electrode layer (11) has a substantially square shape
  • the second electrode layer (12) has a substantially square shape having a smaller area than the first electrode layer (11).
  • the second electrode layer (12) covers the central region of the upper surface (111) of the first electrode layer (11).
  • the dielectric layer (13) is on the region (112) covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). And is not formed on the region (113) that is not covered by the second electrode layer (12).
  • FIG. 3 is an enlarged cross-sectional view of a region near the interface between the first electrode layer (11) and the dielectric layer (13) of the capacitor element (1).
  • a metal layer (14) between the first electrode layer (11) and the dielectric layer (13), there is a metal layer (14) and the surface of the metal layer (14) on the dielectric layer (13) side. And an oxide film (15) formed by oxidizing.
  • the metal layer (14) contains nickel (Ni) as a main component.
  • the metal layer (14) is made of one or more metals selected from the group consisting of aluminum (Al), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), and copper (Cu). It may be included as a main component.
  • a first conductive via (31) and a second conductive via (32) are formed in the insulating substrate (2).
  • the first conductive via (31) is electrically connected to a region (113) not covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11).
  • the second conductive via (32) is electrically connected to the surface (121) of the second electrode layer (12) opposite to the first electrode layer (11) (the upper surface in FIG. 1).
  • the conductive vias 31 and 32 are formed on the surface region 21 on the second electrode layer 12 side of the capacitor element 1 on the surface of the insulating substrate 2 (the upper surface in FIG. 1).
  • both conductive vias (31) and (32) are exposed in the surface region (21).
  • a conductive material such as copper (Cu) is used to form both conductive vias (31) and (32).
  • the first conductive is provided at 12 positions on the region (113) not covered by the second electrode layer (12) among the upper surface (111) of the first electrode layer (11).
  • Vias (31) are formed, and second conductive vias (32) are formed at four locations on the upper surface (121) of the second electrode layer (12).
  • (31) and the second conductive vias (32) to (32) are arranged in a 4 ⁇ 4 matrix on the paper surface of FIG.
  • a ground terminal (41) and a power supply terminal (42) are formed on the upper surface (21) of the insulating substrate (2).
  • the tip of each first conductive via (31) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected to the ground terminal (41), and the power terminal (42)
  • the tip of each second conductive via (32) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected. Therefore, an electrical path is formed between the ground terminal (41) and the power supply terminal (42) via the capacitor element (1).
  • the tip of each second conductive via (32) may be connected to the ground terminal (41), and the tip of each first conductive via (31) may be connected to the power supply terminal (42).
  • each first conductive via (31) extends toward the upper surface (21) of the insulating substrate (2) without being in electrical contact with the second electrode layer (12), and is formed on the upper surface (21).
  • the front end portion of the first conductive via (31) can be exposed. Therefore, the conductive via to be electrically connected to the conventional capacitor-embedded substrate, specifically the first electrode layer (11), is the first electrode of the capacitor element (1) in the surface of the insulating substrate (2).
  • the capacitor is built in this embodiment.
  • the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced. This improves the impedance characteristics of the capacitor built-in substrate in the high frequency region.
  • FIG. 4 is a graph (91) showing the impedance characteristics obtained by simulation for the capacitor built-in substrate (FIG. 1) of this embodiment.
  • the impedance characteristic of the conventional capacitor mounting board as shown in FIG. 37 is also shown by a graph (92).
  • a chip-like capacitor element (316) is mounted on the lower surface (311) of the insulating substrate (304).
  • an electrical path is formed between the power supply terminal (306) and the ground terminal (307) formed on the upper surface (305) of the insulating substrate (304) via the capacitor element (316). Yes.
  • the metal layer forming step, the dielectric layer forming step, the annealing step, the resist forming step, the plating step, the resist stripping step, and the cutting step are performed in this order.
  • FIG. 5 is a perspective view used for explaining the metal layer forming step.
  • a metal foil (50) is prepared.
  • a foil containing copper (Cu) as a main component is used as the metal foil (50).
  • the surface (501) of the metal foil (50) is subjected to nickel ( A metal thin film (51) containing Ni) as a main component is formed.
  • the surface (501) of the metal foil (50) is used by plating.
  • the metal thin film (51) can be easily formed.
  • the adhesion between the metal foil (50) and the metal thin film (51) is improved.
  • the surface (501) of the metal foil (50) is not limited to the metal thin film (51) containing nickel (Ni) as a main component, but also aluminum (Al), titanium (Ti), tantalum (Ta), niobium ( A metal thin film (51) containing as a main component one or more metals selected from the group consisting of Nb), nickel (Ni), and copper (Cu) may be formed.
  • FIG. 6 is a perspective view used for explaining the dielectric layer forming step.
  • a dielectric layer (13) is formed on a plurality of predetermined regions (512) using a powder spray coating method.
  • the first sheet for element formation (61) in which the plurality of dielectric layers (13) are formed on the surface (511) of the metal thin film (51) is formed.
  • a film forming apparatus (7) is used for forming the dielectric layer (13).
  • a dielectric layer (13) having a square shape is powdered at 16 locations arranged in a 4 ⁇ 4 matrix shape on the surface (511) of the metal thin film (51). It is formed using a spray coating method.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • the powder spray coating method includes various film forming methods such as an aerosol deposition method and a powder jet deposition method.
  • FIG. 7 is a view showing a film forming apparatus (7) used in the aerosol deposition method.
  • the film-forming apparatus (7) maintains the inside in a vacuum state with an aerosol generator (71) that stirs and mixes powder with high-pressure gas to form an aerosol, and a vacuum pump (73).
  • the film forming chamber (72) that can be connected is connected by a thin transfer tube (74).
  • the inside of the film formation chamber (72) is maintained in a vacuum state, whereby the space (high pressure space) in the aerosol generator (71) into which the high pressure gas flows and the film formation chamber (72) There will be a pressure difference between this space (low pressure space). Accordingly, the powder aerosolized by the aerosol generator (71) flows in the transfer tube (74) toward the film forming chamber (72).
  • a stage (75) for installing a target on which a thin film is to be formed is provided, and the stage (75) is an installation surface (751) on which the target is installed.
  • the stage (75) In the XY plane parallel to the XY plane, translation in the Z-axis direction perpendicular to the XY plane, and rotation around the Z-axis.
  • One end of the transfer tube (74) is disposed in the film forming chamber (72), and at one end, a slit-like nozzle (76) is positioned so that its tip faces the installation surface (751) of the stage (75). It is attached with.
  • the nozzle (76) has a shape capable of accelerating the powder discharged from one end of the transfer tube (74) to about 100 m / sec.
  • the powder is discharged from the tip of the nozzle (76) at a high speed, and the discharged powder is sprayed onto the surface of the target on the stage (75).
  • FIG. 8 is a view showing a film forming apparatus (7) used in the powder jet deposition method.
  • the film forming apparatus (7) includes a stepped nozzle (81) having two regions (811) and (812) having different inner diameters, and the nozzle (81) has an inner diameter.
  • a through hole (82) for supplying powder is formed at a position close to the second region (812) having a small inner diameter in the large first region (811).
  • the discharged powder is sprayed onto the surface of the target on the stage (75) as in the film forming apparatus (FIG. 7) used for the aerosol deposition method.
  • a powdery dielectric material is sprayed onto the surface (511) of the metal thin film (51) using the powder spray coating method. Thereby, the powdery dielectric material collides with and crushes the surface (511), and the powdery dielectric material collides with and crushes on the surface (511). On the surface (511) of (51), a fine dielectric material is densely deposited to form a dielectric layer (13).
  • a dielectric layer (13) having a desired thickness dimension is formed in each predetermined region (512) without masking the surface (511) of the metal thin film (51).
  • the thickness dimension of the dielectric layer (13) can be easily changed by adjusting the number of scans, scan speed, discharge speed, and the like of the film forming apparatus (7). Therefore, even when the dielectric layer (13) is formed on the plurality of predetermined regions (512) of the metal thin film (51), the thickness dimension of the dielectric layer (13) must be changed for each predetermined region (512). Can be changed easily.
  • the type of dielectric material sprayed for each predetermined region (512) can be changed, and the change can be easily performed.
  • the dielectric layer forming step masking may be performed on a region different from the region on each predetermined region (512) in the surface (511) of the metal thin film (51). Even in this case, it is possible to form the dielectric layer (13) having a desired thickness dimension on each predetermined region (512) by using the powder spray coating method. Further, on the plurality of predetermined regions (512) of the metal thin film (51), not only the plurality of dielectric layers (13) having different thickness dimensions but also a plurality of film formation areas and / or thickness dimensions different from each other. A dielectric layer (13) may be formed.
  • FIG. 9 is a perspective view used for explaining the annealing process.
  • each dielectric layer (13) is irradiated with a laser so that the dielectric layer (13) is annealed.
  • the characteristics of the dielectric layer (13) can be further improved.
  • the region covered with the dielectric layer (13) in the surface (511) of the metal thin film (51) is oxidized, thereby forming an oxide film (15) (see FIG. 3). Therefore, the annealing step is an oxidation treatment step in which the surface (511) of the metal thin film (51) is oxidized to form the oxide film (15) by heat-treating the surface (511) of the metal thin film (51). Will work.
  • various heat treatment methods such as microwave heating, heating in the air or nitrogen atmosphere (using a furnace or the like) can be used for the annealing treatment.
  • FIG. 10 is a perspective view used for explaining the resist formation process.
  • the first sheet for element formation (61) is subjected to a masking process.
  • a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next.
  • the dielectric layer (13 The resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.
  • FIG. 11 is a perspective view used for explaining the plating process.
  • the second sheet for element formation (62) is immersed in a plating solution (9) to perform an electroless plating process on the second sheet for element formation (62).
  • condenser element (1) is formed on each dielectric material layer (13).
  • copper (Cu) is used as the metal material for the electroless plating process.
  • the metal thin film (53) can be formed by a sputtering method, a vapor deposition method, a screen printing method, an ink jet method, or the like.
  • FIG. 13 is a plan view used for explaining the resist stripping process.
  • the resist (52) (see FIG. 12) formed on the surface (511) of the metal thin film (51) is stripped and the surface (511) of the metal thin film (51) is stripped. )
  • the third sheet for element formation (63) is formed.
  • a chemical method can be used for removing the resist (52).
  • FIG. 14 is a plan view used for explaining the cutting process.
  • the third sheet for element formation (63) is cut.
  • a plurality of metal foil pieces (502) are cut out from the metal foil (50) by cutting the metal foil (50) along the broken line shown in FIG.
  • the metal foil (50) is cut so that a part of the surface of each metal foil piece (502) is covered with the corresponding metal thin film (53).
  • the central region of the surface of each metal foil piece (502) is covered with the metal thin film (53), and the shape of each metal foil piece (502) is substantially square. Disconnected.
  • the capacitor element (1) shown in FIG. 1 and FIG. 3 is completed by executing the above cutting step, and the completed capacitor element (1) has a small thickness and becomes a sheet.
  • the cut metal foil piece (502) serves as the first electrode layer (11) of the capacitor element (1)
  • the metal thin film (51) formed on the metal foil piece (502) serves as a capacitor.
  • the metal layer (14) of the element (1) and the metal thin film (53) formed on the metal foil film (51) become the second electrode layer (12) of the capacitor element (1).
  • the dielectric layer forming step the dielectric layer (13) is formed on the metal thin film (51) using a powder spray coating method. Accordingly, when forming the dielectric layer (13), the powdery dielectric material violently collides with the metal thin film (51), while the metal foil (50) is made of the dielectric material by the metal thin film (51). You will be protected from collisions. Therefore, the surface (501) of the metal foil (50) is not easily damaged, and unevenness is hardly formed on the surface (501) of the metal foil (50).
  • the metal thin film (51) contains, as a main component, a metal (nickel (Ni) in this embodiment) whose hardness is higher than the metal (copper (Cu) in this embodiment) included in the metal foil (50) as a main component.
  • the metal thin film (51) is less likely to be damaged by the collision of the powdery dielectric material. Accordingly, it is difficult to form irregularities on the surface (511) of the metal thin film (51).
  • the first electrode layer (11) and the second electrode layer (12) It becomes difficult to reduce the electrical insulation resistance between the two.
  • the oxide film (15) is interposed between the first electrode layer (11) and the dielectric layer (13). Therefore, when the dielectric layer (13) is formed using the powder spray coating method, even when irregularities are formed on the surface (511) of the metal thin film (51) to be the metal layer (14), The oxide film (15) prevents electrical breakdown between the first electrode layer (11) and the second electrode layer (12).
  • the oxide film (15) of the metal layer (14) containing aluminum (Al), tantalum (Ta), niobium (Nb), or nickel (Ni) as a main component has high insulating properties. Among these metals, nickel (Ni) has particularly good insulating properties of its oxide film.
  • the element mounting process and the stacking process are executed in this order. Further, in the element mounting process, the bonding process and the peeling process are executed in this order, so that two of the insulating substrates (20), (20) (see FIG. 19) constituting the insulating substrate (2). One or a plurality of capacitor elements (1) are mounted on one insulating substrate (20). In the following, a method for producing a capacitor built-in substrate in which a plurality of capacitor elements (1) are mounted on an insulating substrate (2) will be described.
  • FIG. 15 is a perspective view used for explaining the sticking process.
  • the carrier sheet (80) capable of adhering and peeling the capacitor element (1) by applying an external action such as heat and pressure is used.
  • the element attachment sheet (8) is produced.
  • each capacitor element (1) is adhered to the carrier sheet (80) in a state where the first electrode layer (11) is in surface contact with a predetermined region (81) on the surface of the carrier sheet (80).
  • the predetermined area (81) is set corresponding to a predetermined position on the insulating base material (20) on which the capacitor element (1) is to be mounted.
  • FIG. 16 is a perspective view used for explaining the former stage of the peeling process.
  • the pair of prepregs (201) (201) and the core material (202) constituting the insulating base material (20) are combined with the pair of prepregs (201) (201).
  • the core material (202) is sandwiched between the layers.
  • the element attachment sheet (8) is superposed at a predetermined position on the prepreg (201) with the capacitor element (1) attached to the element attachment sheet (8) in a posture toward the prepreg (201). .
  • the laminated body (82) which consists of a pair of prepreg (201) (201), core material (202), and element attachment sheet (8) is formed.
  • FIG. 17 is a perspective view used for explaining the middle stage of the peeling process.
  • the pair of prepregs (201) (201) and the core material (202) are thermocompression bonded to each other.
  • the capacitor element (1) attached to the element attachment sheet (8) is thermocompression bonded to the surface of the prepreg (201) on which the element attachment sheet (8) overlaps, while forming the material (20).
  • the capacitor element (1) is easily peeled off from the carrier sheet (80).
  • FIG. 18 is a perspective view used for explaining the latter stage of the peeling process.
  • each capacitor element (1) is peeled from the carrier sheet (80) by peeling off the carrier sheet (80) from the insulating substrate (20).
  • a plurality of capacitor elements (1) are mounted at predetermined positions on the insulating base material (20).
  • the carrier sheet (80) A non-peelable sheet such as a PET (polyethylene terephthalate) sheet having adhesiveness can be used.
  • FIG. 19 is a perspective view used for explaining the stacking process.
  • another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20).
  • an insulating substrate (2) is formed by the two laminated insulating base materials (20).
  • a first conductive via (31) and a second conductive via (32) corresponding to each capacitor element (1) are formed on the insulating substrate (2), and the insulating substrate (2) is formed.
  • a ground terminal (41) and a power supply terminal (42) corresponding to each capacitor element (1) are formed on the upper surface (21). As a result, the capacitor built-in substrate is completed.
  • the capacitor element (1) mounted on the insulating base material (20) in the method for manufacturing a substrate with a built-in capacitor has a small thickness and a sheet shape.
  • Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the element mounting process for mounting the capacitor element (1) on the insulating base material (20) is complicated. Become.
  • the capacitor element (1) is mounted at a predetermined position on the insulating substrate (20) using the element attachment sheet (8) to which the capacitor element (1) is attached. For this reason, it is not necessary to handle the capacitor elements (1) individually, and the element mounting process for mounting the capacitor elements (1) on the insulating substrate (20) is simplified.
  • the first conductive layer (11) of the capacitor element (1) made of metal foil is hardly damaged even when it is peeled off after being stuck on the carrier sheet (80). Therefore, as in the above manufacturing method, after the first electrode layer (11) is stuck to the carrier sheet (80) in the sticking step, the capacitor element (1) is peeled from the carrier sheet (80) in the peeling step. Even in this case, the first electrode layer (11) is hardly damaged.
  • substrate with a built-in capacitor exists in the range of 5 micrometers or more and 100 micrometers or less. This is because when the thickness is smaller than 5 ⁇ m, it is difficult to handle the capacitor element (1), and problems such as an increase in resistance occur. Further, when the thickness dimension is larger than 100 ⁇ m, the thickness of the capacitor element (1) affects the surface of the insulating base material (20), so that irregularities are formed on the surface of the insulating base material (20). This is because it becomes difficult to laminate another insulating base material (20) thereon.
  • FIG. 20 is a plan view of the capacitor element (1) built in the capacitor built-in substrate as viewed from the second electrode layer (12) side in the first variation of the capacitor built-in substrate.
  • the first conductive via (31) is located on the upper surface (111) of the first electrode layer (11) over the region (113) not covered by the second electrode layer (12).
  • the second conductive vias (32) are formed at 25 locations on the upper surface (121) of the second electrode layer (12), and the first conductive vias (31) to (31) are formed.
  • the second conductive vias (32) to (32) may be arranged in a 7 ⁇ 7 matrix on the paper surface of FIG.
  • FIG. 21 is a plan view of the capacitor element (1) built in the capacitor built-in substrate as viewed from the second electrode layer (12) side in the second variation of the capacitor built-in substrate.
  • the dielectric layer (13) is interposed at four locations on the upper surface (111) of the first electrode layer (11) of the capacitor element (1).
  • the second electrode layer (12) may be provided, and the second electrode layers (12) provided at the four locations may be arranged apart from each other.
  • the conductive vias arranged in the first row, the fourth row, and the seventh row, the first column A total of 33 conductive vias arranged in the row and the seventh row are first conductive vias (31), and the other 16 conductive vias are second conductive vias (32).
  • the 16 second conductive vias (32) are connected to the second electrode layers (12) provided at the four locations, four by four.
  • the number of the first conductive vias (31) can be increased.
  • the first conductive via (31) has a gap between the second conductive via (32). There are many things with the smallest distance. Therefore, the inductance generated in the capacitor built-in substrate can be further reduced.
  • FIG. 22 is a cross-sectional view showing a third modification of the capacitor built-in substrate.
  • the insulating substrate (2) is opposite to the second electrode layer (12) of the first electrode layer (11) of the capacitor element (1).
  • a third conductive via (33) electrically connected to the surface (114) of the substrate (lower surface in FIG. 1 and FIG. 22) is further formed, and the third conductive via (33) is formed on the insulating substrate (2).
  • the tip of the third conductive via (33) may be exposed on the lower surface (22).
  • FIG. 23 is a cross-sectional view showing a fourth modification of the capacitor built-in substrate.
  • the dielectric layer (13) is formed on a region (112) covered with the second electrode layer (12) in the upper surface (111) of the first electrode layer (11).
  • it may be formed on a region (113) not covered with the second electrode layer (12).
  • the first conductive via (31) extends through the dielectric layer (13) toward the upper surface (21) of the insulating substrate (2).
  • FIG. 24 shows a capacitor element (1) built in a capacitor-embedded substrate according to a second embodiment of the present invention, its first electrode layer (11), dielectric layer (13), and It is sectional drawing to which the area
  • the first electrode layer (11) includes aluminum (Al), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), copper ( One or more metals selected from the group consisting of Cu) as a main component, and without the metal layer (14) interposed between the first electrode layer (11) and the dielectric layer (13), An oxide film (16) formed by oxidizing the surface of the first electrode layer (11) on the dielectric layer (13) side may be interposed.
  • a film forming method such as a sol-gel method, a sputtering method, a vacuum deposition method, or a powder spray coating method is used.
  • a sol-gel method a sol-gel method
  • a sputtering method a vacuum deposition method
  • a powder spray coating method is used.
  • the oxide film (16) is interposed between the first electrode layer (11) and the dielectric layer (13). Therefore, even when pinholes or cracks are generated in the dielectric layer (13), the electrical coating between the first electrode layer (11) and the second electrode layer (12) is caused by the oxide film (16).
  • Dielectric breakdown will be prevented. Further, even if the surface of the first electrode layer (11) is uneven by forming the dielectric layer (13) using the powder spray coating method, the first oxide film (16) is used to form the first layer. Electrical breakdown between the electrode layer (11) and the second electrode layer (12) is prevented.
  • FIG. 25 shows a capacitor element (1) built in a capacitor built-in substrate according to a third embodiment of the present invention, and its first electrode layer (11), dielectric layer (13), and It is sectional drawing to which the area
  • the capacitor element (1) may have a configuration without the oxide film (15) on the metal layer (14).
  • the metal layer (14) includes a metal having a higher hardness than the metal included in the first electrode layer (11) as a main component, so that the metal layer (14) is a powdery dielectric material. Less susceptible to damage from collisions. Accordingly, it is difficult for irregularities to be formed on the surface of the metal layer (14), and as a result, electrical insulation between the first electrode layer (11) and the second electrode layer (12) in the capacitor element (1). Resistance becomes difficult to decrease.
  • a metal thin film (51) containing nickel (Ni) as a main component is formed on the surface (501) of the metal foil (50) in the same manner as the metal layer forming step described with reference to FIG. To do.
  • the surface (501) of the metal foil (50) is not limited to the metal thin film (51) containing nickel (Ni) as a main component, but also aluminum (Al), titanium (Ti), tantalum (Ta), niobium ( A metal thin film (51) containing as a main component one or more metals selected from the group consisting of Nb), nickel (Ni), and copper (Cu) may be formed.
  • FIG. 26 (a) is a perspective view used for explaining the dielectric layer forming step
  • FIG. 26 (b) is a cross-sectional view taken along the line BB shown in FIG. 26 (a).
  • the metal foil (50) has predetermined regions (54) to be the first electrode layer (11) of the capacitor element (1) at a plurality of locations.
  • the dielectric layer (13) is formed on the surface (511) of the metal thin film (51) existing on each predetermined region (54) by using a powder spray coating method. .
  • the dielectric layer (13) is formed on each predetermined region (54) so as to cover a part of the predetermined region (54).
  • a first element forming sheet (61) in which a plurality of dielectric layers (13) are formed on the surface (511) of the metal thin film (51) on the metal foil (50) is formed.
  • a film forming apparatus (7) is used for forming the dielectric layer (13).
  • a dielectric layer (13) having a square shape is formed on each predetermined region (54) by using a powder spray coating method. At this time, the dielectric layer (13) is formed on each predetermined region (54) so as to cover the central portion of the predetermined region (54).
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • the powder spray coating method includes various film forming methods such as an aerosol deposition method and a powder jet deposition method.
  • a film forming apparatus (7) shown in FIGS. 7 and 8 is used, respectively.
  • the surface (511) of the metal thin film (51) is not masked on each predetermined region (54).
  • a dielectric layer (13) having a desired thickness dimension T can be formed on the surface (511) of the existing metal thin film (51).
  • the thickness dimension T of the dielectric layer (13) can be easily changed by adjusting the number of scans, scan speed, discharge speed, etc. of the film forming apparatus (7). Therefore, even when the dielectric layer (13) is formed at a plurality of locations on the surface (511) of the metal thin film (51), the thickness dimension T is set for each dielectric layer (13) as shown in FIG. It can be changed and the change can be easily performed.
  • the type of dielectric material sprayed for each dielectric layer (13) can be changed, and the change can be easily performed.
  • the dielectric layer forming step masking may be performed on a region different from the region on each predetermined region (54) of the metal foil (50) in the surface (511) of the metal thin film (51). Even in this case, by using the powder spray coating method, the dielectric layer (13) having a desired thickness is formed on the surface (511) of the metal thin film (51) existing on each predetermined region (54). It is possible to form. Further, the surface (511) of the metal thin film (51) existing on the plurality of predetermined regions (54) of the metal foil (50) is not limited to the plurality of dielectric layers (13) having different thickness dimensions. A plurality of dielectric layers (13) having different film areas and / or thickness dimensions may be formed.
  • FIG. 27 is a perspective view used for explaining the annealing process.
  • each dielectric layer (13) is irradiated with a laser to thereby anneal the dielectric layer (13).
  • the characteristics of the dielectric layer (13) can be further improved.
  • the region covered with the dielectric layer (13) in the surface (511) of the metal thin film (51) is oxidized, thereby forming an oxide film (15) (see FIG. 3). Therefore, the annealing step is an oxidation treatment step in which the surface (511) of the metal thin film (51) is oxidized to form the oxide film (15) by heat-treating the surface (511) of the metal thin film (51). Will work.
  • various heat treatment methods such as microwave heating, heating in the air or nitrogen atmosphere (using a furnace or the like) can be used for the annealing treatment.
  • FIG. 28 is a perspective view used for explaining the resist formation process.
  • a masking process is performed on the first element forming sheet (61).
  • a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next.
  • the dielectric layer (13 The resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.
  • FIG. 29 is a perspective view used for explaining the plating process.
  • the element forming second sheet (62) is subjected to electroless plating by immersing the element forming second sheet (62) in a plating solution (9).
  • a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) is formed on each dielectric layer (13).
  • copper (Cu) is used as the metal material for the electroless plating process.
  • the metal thin film (53) can be formed by a sputtering method, a vapor deposition method, a screen printing method, an ink jet method, or the like.
  • FIG. 31 is a plan view used for explaining the resist stripping process.
  • FIG. 32 is a sectional view taken along the line CC shown in FIG.
  • the resist (52) (see FIG. 30) formed on the surface (511) of the metal thin film (51) is stripped to remove the metal thin film (51).
  • the resist (52) is removed from the surface (511).
  • each predetermined region (54) of the metal foil (50), a metal thin film (51) formed on the predetermined region (54), and a dielectric layer (on the metal thin film (51) An element sheet (6) having a plurality of element portions (5) composed of 13) and a metal thin film (53) formed on the dielectric layer (13) is formed.
  • a chemical method can be used for removing the resist (52).
  • FIG. 33 is a cross-sectional view used for explaining the pasting process. As shown in FIG. 33, in the pasting step, the surface of one insulating base material (20) of the two insulating base materials (20) and (20) (see FIG. 35) constituting the insulating substrate (2) is applied. The element sheet (6) is pasted.
  • FIG. 34 is a cross-sectional view used for explaining the etching process. As shown in FIG. 34, in the etching process, pattern etching is performed on the metal foil (50) (see FIG. 33) of the element sheet (6) to thereby form each predetermined region set in the metal foil (50) (see FIG. 34). 54) is left on the insulating substrate (20).
  • each predetermined region (54) left on the insulating base (20) is a part of the surface on the metal thin film (53) side, specifically, the central region on the surface on the metal thin film (53) side. It will be covered by the metal thin film (53).
  • the metal thin film (53) In other words, in the etching process, a part of the surface on the metal thin film (53) side of the predetermined region (54) to be left out of the metal foil (50) is covered with the metal thin film (53).
  • pattern etching is performed on the metal foil (50).
  • the plurality of element portions (5) of the element sheet (6) are left at predetermined positions on the insulating base (20), and as a result, each element left on the insulating base (20).
  • the capacitor element (1) is formed from the portion (5). Specifically, a predetermined region (54) of the metal foil (50) left on the insulating substrate (20) in each element part (5) becomes the first electrode layer (11) of the capacitor element (1).
  • the metal thin film (51) formed on the predetermined region (54) becomes the metal layer (14) of the capacitor element (1), and is formed on the metal thin film (51) via the dielectric layer (13).
  • the metal thin film (53) thus formed becomes the second electrode layer (12).
  • each capacitor element (1) is mounted at a predetermined position on the insulating substrate (20).
  • the right capacitor element (1) and the left capacitor element (1) have different thickness dimensions T of the dielectric layer (13).
  • the capacitor elements (1) have different capacitances.
  • the insulating substrate (2) As shown in FIG. 34, in the etching process of the present embodiment, by performing pattern etching on the metal foil (50), in addition to the first electrode layer (11) of the capacitor element (1), the insulating substrate (2) An electrode pattern (55) such as a power supply pattern and a ground pattern to be formed therein is also formed.
  • FIG. 35 is a cross-sectional view used for explaining the stacking process.
  • another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20).
  • the insulating substrate (2) is formed by the two laminated insulating base materials (20).
  • a first conductive via (31) and a second conductive via (32) corresponding to each capacitor element (1) are formed on the insulating substrate (2), and the insulating substrate (2) is formed.
  • a ground terminal (41) and a power supply terminal (42) corresponding to each capacitor element (1) are formed on the upper surface (21). As a result, the capacitor built-in substrate is completed.
  • the dielectric layer (13) is formed using a powder spray coating method.
  • the powder spray coating method as described above, even when the dielectric layer (13) is formed at a plurality of locations on the surface (511) of the metal thin film (51), as shown in FIG.
  • the deposition area and / or thickness dimension T can be changed for each dielectric layer (13), and the change can be easily performed.
  • the type of dielectric material sprayed for each dielectric layer (13) can be changed, and the change can be easily performed.
  • the capacitor element (1) having a desired capacitance can be mounted at a predetermined position on the insulating substrate (20). .
  • the type of dielectric material constituting the dielectric layer (13), the film formation area of the dielectric layer (13), and the dielectric layer It is only necessary to change at least one of the thickness dimensions T in 13), and it is not necessary to redesign the arrangement of the capacitor element (1).
  • the dielectric layer (13) can be formed without masking the surface (511) of the metal thin film (51), and therefore the yield of the capacitor-embedded substrate can be improved.
  • the surface (501) of the metal foil (50) to be the first electrode layer (11) is covered with the metal thin film (51) to be the metal layer (14).
  • the dielectric layer forming step the dielectric layer (13) is formed on the metal thin film (51) using a powder spray coating method. Accordingly, when forming the dielectric layer (13), the powdery dielectric material violently collides with the metal thin film (51), while the metal foil (50) is made of the dielectric material by the metal thin film (51). You will be protected from collisions. Therefore, the surface (501) of the metal foil (50) is not easily damaged, and unevenness is hardly formed on the surface (501) of the metal foil (50).
  • the metal thin film (51) contains, as a main component, a metal (nickel (Ni) in this embodiment) whose hardness is higher than the metal (copper (Cu) in this embodiment) included in the metal foil (50) as a main component.
  • the metal thin film (51) is less likely to be damaged by the collision of the powdery dielectric material. Accordingly, it is difficult to form irregularities on the surface (511) of the metal thin film (51).
  • the first electrode layer (11) and the second electrode are formed. The electrical insulation resistance between the layer (12) is difficult to decrease.
  • the oxide film (15) is interposed between the first electrode layer (11) and the dielectric layer (13). It will be. Therefore, when the dielectric layer (13) is formed using the powder spray coating method, even when irregularities are formed on the surface (511) of the metal thin film (51) to be the metal layer (14), The oxide film (15) prevents electrical breakdown between the first electrode layer (11) and the second electrode layer (12).
  • the oxide film (15) of the metal layer (14) containing aluminum (Al), tantalum (Ta), niobium (Nb), or nickel (Ni) as a main component has high insulating properties.
  • nickel (Ni) has particularly good insulating properties of its oxide film.
  • the capacitor element (1) mounted on the insulating substrate (20) in the above manufacturing method has a small thickness dimension and is in the form of a sheet.
  • Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the process of mounting the capacitor elements (1) on the insulating base material (20) becomes complicated.
  • the capacitor element (1) is formed by performing the etching process, and the capacitor element (1) is handled as the element sheet (6) until the etching process is performed. Therefore, it is not necessary to handle the capacitor elements (1) individually, and the process of mounting the capacitor elements (1) on the insulating base material (20) is simplified.
  • the metal that becomes the metal layer (14) of the capacitor element (1) is formed on the metal foil (50).
  • a thin film (51), an oxide film (15), a dielectric layer (13), and a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) an element sheet (6) Is making. Therefore, the metal thin film (51) to be the metal layer (14), the oxide film (15), the dielectric layer (13), and the metal thin film (53) to be the second electrode layer (12) are combined with the insulating base (20 ) No need to form on.
  • the dielectric material or the metal material for forming the dielectric layer (13) and the metal thin films (51) and (53) is mixed into another component such as the insulating base (20). Further, even when it is necessary to perform a heat treatment, specifically, the above-described annealing step, in order to form the capacitor element (1), there is no possibility that another component is adversely affected by the heat treatment.
  • each part of the present invention is not limited to the first to fourth embodiments, and various modifications can be made within the technical scope described in the claims.
  • the method for manufacturing a capacitor built-in substrate can also be applied to the manufacture of a capacitor built-in substrate in which the capacitor element (1) is embedded only at one location in the insulating substrate (2).
  • the dielectric layer (13) in the dielectric layer forming step, may be formed by using a film forming method such as a sol-gel method, a sputtering method, or a vacuum evaporation method.
  • a film forming method such as a sol-gel method, a sputtering method, or a vacuum evaporation method.
  • the oxide film (15) is interposed between the metal layer (14) and the dielectric layer (13). Therefore, even when pinholes or cracks are generated in the dielectric layer (13), the electrical coating between the first electrode layer (11) and the second electrode layer (12) is caused by the oxide film (15). Dielectric breakdown will be prevented.
  • the surface (511) of the metal thin film (51) is formed.
  • an oxide film (15) is previously formed on the surface of the metal foil to be the metal layer (14), and the metal foil is attached to a predetermined region on the metal foil (50) to be the first electrode layer (11). May be attached.
  • the annealing step is not an essential step, but only when the characteristics of the dielectric layer (13) are further improved or when the insulating characteristics of the capacitor element (1) to be manufactured are further improved. An annealing step may be performed.
  • the surface (511) of the metal thin film (51) or the metal foil (50) to be the metal layer (14) is formed.
  • an oxide film can be formed on these surfaces.
  • the metal thin film (51) to be the metal layer (14) is formed by plating the metal foil (50) to be the first electrode layer (11).
  • the present invention is not limited to this.
  • another metal foil to be the metal layer (14) may be attached on the metal foil (50) to be the first electrode layer (11).
  • the metal foil is formed into the first metal foil. It can be affixed to a metal foil (50) to be an electrode layer (11).
  • the second electrode layer (12) of the capacitor element (1) may be formed of a metal foil.
  • the shape of the first electrode layer (11) and the second electrode layer (12) of the capacitor element (1) is not limited to a substantially square shape, but the first electrode layer (11) and the second electrode layer (12). ) Various shapes can be used.
  • the first conductive via (31) may be formed only at one location in the insulating substrate (2).
  • the second conductive via (32) may be formed only at one place in the insulating substrate (2).
  • Capacitor element (11) First electrode layer (12) Second electrode layer (13) Dielectric layer (14) Metal layer (15) Oxide film (16) Oxide film (2) Insulating substrate (20) Insulating substrate (31) First conductive via (32) Second conductive via (33) Third conductive via (41) Ground terminal (42) Power supply terminal (5) Element section (50) Metal foil (51) Metal thin film (metal layer) (53) Metal thin film (second metal layer) (54) Predetermined area (6) Element sheet (7) Deposition system (8) Element attachment sheet (80) Carrier sheet (81) Predetermined area

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Capacitors (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'élément condensateur (1) de l'invention est muni : d'une première couche d'électrode (11), d'une couche diélectrique (13) formée sur ladite première couche d'électrode (11), et d'une seconde couche d'électrode formée sur ladite couche diélectrique (13). Entre la première couche d'électrode (11) et la couche diélectrique (13), sont interposées : une couche métallique (14) contenant en tant que composant principal un ou plusieurs métaux choisis dans un groupe constitué d'aluminium, de titane, de tantale, de niobium, de nickel, et de cuivre; et une membrane de revêtement d'oxyde (15) formée par oxydation de la surface côté couche diélectrique (13) de ladite couche métallique (14).
PCT/JP2011/053640 2010-03-26 2011-02-21 Élément de condensateur, substrat avec condensateur intégré, feuille d'élément, et procédés de fabrication de ceux-ci WO2011118308A1 (fr)

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JP2011228390A (ja) * 2010-04-16 2011-11-10 Fujitsu Ltd キャパシタ及びその製造方法
JP2017224757A (ja) * 2016-06-16 2017-12-21 住友電工デバイス・イノベーション株式会社 キャパシタの製造方法
WO2018034753A3 (fr) * 2016-08-18 2018-06-14 Qualcomm Incorporated Condensateur mim à densité multiple pour performance améliorée de multiplexeur passif sur verre (pog)

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JP2017224757A (ja) * 2016-06-16 2017-12-21 住友電工デバイス・イノベーション株式会社 キャパシタの製造方法
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