WO2011086797A1 - Procédé de fabrication de substrat avec condensateur incorporé - Google Patents

Procédé de fabrication de substrat avec condensateur incorporé Download PDF

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Publication number
WO2011086797A1
WO2011086797A1 PCT/JP2010/071976 JP2010071976W WO2011086797A1 WO 2011086797 A1 WO2011086797 A1 WO 2011086797A1 JP 2010071976 W JP2010071976 W JP 2010071976W WO 2011086797 A1 WO2011086797 A1 WO 2011086797A1
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WIPO (PCT)
Prior art keywords
capacitor
electrode layer
sheet
substrate
capacitor element
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PCT/JP2010/071976
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English (en)
Japanese (ja)
Inventor
田中　直樹
江崎　賢一
一也 二木
野口　仁志
真吾 前田
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三洋電機株式会社
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Publication of WO2011086797A1 publication Critical patent/WO2011086797A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • H01G13/003—Apparatus or processes for encapsulating capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances

Definitions

  • the present invention relates to a method for manufacturing a capacitor built-in substrate in which a capacitor element is built in an insulating substrate.
  • capacitors are provided at a plurality of locations in a surface region (305) (upper surface in FIG. 20; hereinafter referred to as “upper surface”) on which a semiconductor element such as a CPU is mounted.
  • a ground terminal (306) and a power supply terminal (307) to which both electrode layers (301) and (302) of the element (300) are to be electrically connected are formed.
  • the capacitor element (300) is embedded in the insulating substrate (304) so that both electrode layers (301) and (302) are substantially parallel to the upper surface (305) of the insulating substrate (304).
  • the first electrode layer (301) and each ground terminal (306) are electrically connected to each other through conductive vias (308) and (309) formed in the insulating substrate (304), while the capacitor element
  • the second electrode layer (302) of (300) and each power supply terminal (307) are electrically connected to each other through a conductive via (310) formed in the insulating substrate (304).
  • the capacitor element (300) is mounted on one of the two insulating substrates constituting the insulating substrate (304), and then the other insulating substrate. Is laminated on one insulating substrate.
  • the capacitor element (300) mounted on the insulating base material has a small thickness and is in the form of a sheet.
  • Such a capacitor element (300) requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements (300) to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements (300) on the insulating base material becomes complicated.
  • an object of the present invention is to simplify the process of mounting a capacitor element on an insulating base material in the method of manufacturing a capacitor built-in substrate.
  • a method for manufacturing a capacitor-embedded substrate according to the present invention includes one or a plurality of capacitor elements having a dielectric layer interposed between a first electrode layer and a second electrode layer, and an insulating substrate.
  • a method of manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in an insulating substrate by embedding the capacitor element includes a sticking step, a peeling step, and a stacking step.
  • the capacitor element is applied to one or a plurality of predetermined regions in the surface of the sheet by using a sheet capable of attaching and peeling the capacitor element by applying an external action.
  • An element attachment sheet is prepared by attaching and attaching.
  • the element attachment sheet is placed at a predetermined position on one of the two insulating bases constituting the insulating substrate, and the capacitor element attached to the element attaching sheet is placed on the one side.
  • the capacitor elements are peeled off from the sheet and mounted on the one insulating substrate by superimposing them in a posture toward the insulating substrate and applying the external action to the element attachment sheet in that state.
  • the insulating substrate is formed by laminating the other insulating base material on the one insulating base material.
  • the capacitor element mounted on the insulating substrate has a small thickness dimension and is in the form of a sheet.
  • Such a capacitor element requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements on the insulating base material becomes complicated.
  • the capacitor element is mounted at a predetermined position on the insulating substrate using the element attachment sheet to which the capacitor element is attached. For this reason, it is not necessary to handle the capacitor elements individually, and the process of mounting the capacitor elements on the insulating substrate is simplified.
  • the capacitor element has the first electrode layer formed of a metal foil while the second electrode layer is formed of a metal thin film or a metal foil.
  • the capacitor element is attached to the sheet in a state where the first electrode layer is in surface contact with a predetermined region on the surface of the sheet.
  • the first electrode layer made of metal foil is not easily damaged even if it is peeled off after being attached to a sheet. Therefore, even if the capacitor element is peeled off from the sheet in the peeling step after the first electrode layer is stuck on the sheet in the sticking step as in the above specific configuration, the first electrode layer is hardly damaged. .
  • the first electrode layer of the capacitor element has a part of the surface on the second electrode layer side covered with the second electrode layer.
  • the process of mounting the capacitor element on the insulating base material can be simplified.
  • FIG. 1 is a sectional view showing a capacitor built-in substrate according to an embodiment of the present invention.
  • FIG. 2 is a plan view of the capacitor element built in the capacitor built-in substrate as viewed from the second electrode layer side.
  • FIG. 3 is a diagram showing impedance characteristics of the capacitor built-in substrate.
  • FIG. 4 is a perspective view for explaining a dielectric layer forming step of the method of manufacturing the capacitor element.
  • FIG. 5 is a perspective view for explaining an annealing process of the manufacturing method.
  • FIG. 6 is a perspective view for explaining a resist forming step of the manufacturing method.
  • FIG. 7 is a perspective view for explaining a plating step of the manufacturing method.
  • FIG. 8 is a plan view for explaining the state of the second sheet for element formation after execution of the plating step.
  • FIG. 9 is a plan view for explaining a resist stripping step of the manufacturing method.
  • FIG. 10 is a plan view for explaining a cutting step of the manufacturing method.
  • FIG. 11 is a perspective view for explaining a sticking step among the capacitor element mounting methods executed in the element mounting step of the method for manufacturing a capacitor built-in substrate.
  • FIG. 12 is a perspective view for explaining the first stage of the peeling process of the mounting method.
  • FIG. 13 is a perspective view for explaining the middle stage of the peeling process of the mounting method.
  • FIG. 14 is a perspective view for explaining the latter stage of the peeling process of the mounting method.
  • FIG. 15 is a perspective view for explaining a lamination process of the method for manufacturing a capacitor built-in substrate.
  • FIG. 16 is a plan view of the capacitor-embedded substrate according to the first modification of the present invention when the capacitor element built in the capacitor-embedded substrate is viewed from the second electrode layer side.
  • FIG. 17: is the top view which looked at the capacitor
  • FIG. 18 is a cross-sectional view showing a capacitor built-in substrate according to a third modification of the present invention.
  • FIG. 19 is a cross-sectional view showing a capacitor built-in substrate according to a fourth modification of the present invention.
  • FIG. 20 is a cross-sectional view showing a conventional capacitor built-in substrate.
  • FIG. 21 is a cross-sectional view showing a conventional capacitor mounting board.
  • FIG. 1 is a cross-sectional view showing a capacitor built-in substrate according to an embodiment of the present invention.
  • the capacitor-embedded substrate of this embodiment includes a capacitor element (1) having a dielectric layer (13) interposed between a first electrode layer (11) and a second electrode layer (12).
  • the capacitor element (1) is built in the insulating substrate (2) by embedding the capacitor element (1) in the insulating substrate (2).
  • the capacitor element (1) is embedded in the insulating substrate (2) in such a posture that the surfaces of the electrode layers (11), (12) are substantially parallel to the surface of the insulating substrate (2).
  • the insulating substrate (2) is formed from a material having flame retardancy, for example, a material of FR-4 (Flame Retardant Type 4).
  • FR-4 Flame Retardant Type 4
  • the material of FR-4 is a flame retardant material made of, for example, a composite material of glass fiber and epoxy resin.
  • the first electrode layer (11) of the capacitor element (1) is formed of a metal foil.
  • the metal foil is formed of a metal material that can form a foil and can be an electrode layer, such as copper (Cu), nickel (Ni), aluminum (Al), platinum (Pt), or the like.
  • the metal foil can be handled by itself, for example, can hold itself.
  • the thickness dimension of the metal foil is preferably 1 ⁇ m or more.
  • copper (Cu) is used as the metal material of the metal foil forming the first electrode layer (11).
  • the second electrode layer (12) of the capacitor element (1) is formed of a metal thin film.
  • the metal thin film is a metal film formed thinly on the surface of the base material such as the dielectric layer (13), and a thin film such as copper (Cu) can be formed and can be an electrode layer. It is formed from a metal material. Therefore, the metal thin film is difficult to handle by itself, and is handled integrally with the base material.
  • the thickness dimension of the metal thin film is preferably 20 ⁇ m or less.
  • copper (Cu) is used as the metal material of the metal thin film that forms the second electrode layer (12).
  • FIG. 2 is a plan view of the capacitor element (1) as seen from the second electrode layer (12) side.
  • the first electrode layer (11) of the capacitor element (1) has a surface (111) on the second electrode layer (12) side (upper surface in FIG. 1; hereinafter referred to as “upper surface”). Is covered with the second electrode layer (12).
  • the first electrode layer (11) has a substantially square shape
  • the second electrode layer (12) has a substantially square shape having a smaller area than the first electrode layer (11).
  • the second electrode layer (12) covers the central region of the upper surface (111) of the first electrode layer (11).
  • the dielectric layer (13) is a region (112) covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). ) And is not formed on the region (113) not covered by the second electrode layer (12).
  • the insulating substrate (2) is electrically connected to a region (113) of the upper surface (111) of the first electrode layer (11) that is not covered by the second electrode layer (12).
  • the connected first conductive via (31) and the surface (121) of the second electrode layer (12) on the opposite side of the first electrode layer (11) (upper surface in FIG. 1; hereinafter referred to as “upper surface”) ) are electrically connected to the second conductive via (32).
  • the conductive vias 31 and 32 are formed on the surface region 21 on the second electrode layer 12 side of the capacitor element 1 on the surface of the insulating substrate 2 (the upper surface in FIG. 1).
  • both conductive vias (31) and (32) are exposed in the surface region (21).
  • a conductive material such as copper (Cu) is used to form both conductive vias (31) and (32).
  • the first electrode layer is formed at 12 locations on the upper surface (111) of the first electrode layer (11) on the region (113) not covered by the second electrode layer (12).
  • Conductive vias (31) are formed, and second conductive vias (32) are formed at four locations on the upper surface (121) of the second electrode layer (12).
  • These first conductive vias (31) (31) and second conductive vias (32) to (32) are arranged in a 4 ⁇ 4 matrix on the paper surface of FIG.
  • a ground terminal (41) and a power supply terminal (42) are formed on the upper surface (21) of the insulating substrate (2).
  • the tip of each first conductive via (31) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected to the ground terminal (41), and the power terminal (42)
  • the tip of each second conductive via (32) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected. Therefore, an electrical path is formed between the ground terminal (41) and the power supply terminal (42) via the capacitor element (1).
  • each second conductive via (32) may be connected to the ground terminal (41), and the tip of each first conductive via (31) may be connected to the power supply terminal (42).
  • each first conductive via (31) extends toward the upper surface (21) of the insulating substrate (2) without being in electrical contact with the second electrode layer (12), and is formed on the upper surface (21).
  • the front end portion of the first conductive via (31) can be exposed. Therefore, the conductive via to be electrically connected to the conventional capacitor-embedded substrate, specifically the first electrode layer (11), is the first electrode of the capacitor element (1) in the surface of the insulating substrate (2).
  • this embodiment Compared with the capacitor built-in substrate (see FIG. 20) routed to the surface region (22) on the layer (11) side (the lower surface in FIG. 1; hereinafter referred to as the “lower surface”), this embodiment has a built-in capacitor.
  • the substrate FIG. 1
  • the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced. This improves the impedance characteristics of the capacitor built-in substrate in the high frequency region.
  • FIG. 3 is a graph (91) showing the impedance characteristics of the substrate with a built-in capacitor of the present embodiment obtained by simulation.
  • the impedance characteristic of the conventional capacitor mounting board as shown in FIG. 21 is also shown by a graph (92).
  • a chip-like capacitor element (316) is mounted on the lower surface (311) of the insulating substrate (304).
  • an electrical path is formed between the power supply terminal (306) and the ground terminal (307) formed on the upper surface (305) of the insulating substrate (304) via the capacitor element (316). Yes.
  • FIG. 4 is a perspective view for explaining a dielectric layer forming step of the method of manufacturing the capacitor element (1).
  • a film forming apparatus (71) is used on the surface (501) of the metal foil (50) to be the first electrode layer (11) of the capacitor element (1).
  • the dielectric layer (13) of the capacitor element (1) is formed.
  • a dielectric layer (13) having a square shape is formed in a 4 ⁇ 4 matrix on the surface (501) of one metal foil (50) made of copper (Cu). .
  • the first sheet for element formation (61) in which a plurality of dielectric layers (13) are formed on the surface (501) of the metal foil (50) is formed.
  • FIG. 5 is a perspective view for explaining the annealing step of the method for manufacturing the capacitor element (1).
  • An annealing process is a process performed after execution of a dielectric material layer formation process. As shown in FIG. 5, in the annealing step, each dielectric layer (13) is irradiated with a laser to thereby anneal the dielectric layer (13). Thereby, the characteristics of the dielectric layer (13) can be further improved.
  • the annealing step is not an essential step for manufacturing the capacitor element (1) according to the present invention, and the annealing step may be performed only when the characteristics of the dielectric layer are further improved.
  • annealing may be performed by a method such as microwave heating, heating in the atmosphere or nitrogen atmosphere (using a furnace or the like), or the like.
  • FIG. 6 is a perspective view for explaining a resist forming step of the method of manufacturing the capacitor element (1).
  • the resist formation step is a step that is executed after the annealing step.
  • a masking process is performed on the first element forming sheet (61).
  • a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next.
  • the dielectric layer 13
  • the resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.
  • FIG. 7 is a perspective view for explaining a plating step of the method of manufacturing the capacitor element (1).
  • a plating process is a process performed after execution of a resist formation process.
  • the element forming second sheet (62) is subjected to electroless plating by immersing the element forming second sheet (62) in a plating solution (72).
  • a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) is formed on each dielectric layer (13).
  • copper (Cu) is used as the metal material for the electroless plating process.
  • a method such as sputtering, vapor deposition, screen printing, and ink jet can be used in addition to plating.
  • FIG. 9 is a plan view for explaining the resist stripping step of the method of manufacturing the capacitor element (1).
  • the resist stripping process is a process executed after the plating process.
  • the resist (52) (see FIG. 8) formed on the surface (501) of the metal foil (50) is stripped and the surface (501) of the metal foil (50) is removed. )
  • the third sheet for element formation (63) is formed.
  • a chemical method can be used for removing the resist (52).
  • FIG. 10 is a plan view for explaining a cutting step of the method of manufacturing the capacitor element (1).
  • a cutting process is a process performed after execution of a resist peeling process.
  • the third sheet for element formation (63) is cut.
  • the first electrode layer (11) is formed from the metal foil (50) by cutting the metal foil (50) along the broken line shown in FIG.
  • the metal foil (50) is cut so that a part of the surface of the formed first electrode layer (11) is covered with the second electrode layer (12). Specifically, in the metal foil (50), the central region of the surface of the first electrode layer (11) is covered with the second electrode layer (12), and the shape of the first electrode layer (11) is substantially square. It is cut like this.
  • the capacitor element (1) is completed by carrying out the manufacturing method described above, and the capacitor element (1) manufactured as described above has a small thickness and a sheet shape.
  • the capacitor element (1) is placed on one insulating base material (20) of the two insulating base materials (20) and (20) (see FIG. 15) constituting the insulating substrate (2).
  • the element mounting process to be mounted is executed.
  • FIG. 11 is a perspective view for explaining a sticking process of the mounting method of the capacitor element (1).
  • the carrier sheet (80) capable of adhering and peeling the capacitor element (1) by applying an external action such as heat and pressure is used.
  • the element attachment sheet (8) is produced by attaching and attaching the capacitor element (1) to one or a plurality of predetermined regions (81) of the surface of the sheet (80).
  • the capacitor element (1) is adhered to the carrier sheet (80) in a state where the first electrode layer (11) is in surface contact with a predetermined region (81) on the surface of the carrier sheet (80).
  • the predetermined area (81) is set corresponding to a predetermined position on the insulating base material (20) on which the capacitor element (1) is to be mounted.
  • FIGS. 12 to 14 are perspective views for explaining the peeling process of the mounting method of the capacitor element (1).
  • a peeling process is a process performed after execution of a sticking process.
  • the pair of prepregs (201) (201) and the core material (202) constituting the insulating base material (20) are combined with the pair of prepregs (201) ( 201) and sandwiching the core material (202).
  • the element attachment sheet (8) is superposed at a predetermined position on the prepreg (201) with the capacitor element (1) attached to the element attachment sheet (8) in a posture toward the prepreg (201). .
  • the laminated body (82) which consists of a pair of prepreg (201) (201), core material (202), and element attachment sheet (8) is formed.
  • the pair of prepregs (201) (201) and the core material (202) are thermocompression bonded.
  • the capacitor substrate (1) attached to the element attachment sheet (8) is thermocompression-bonded to the surface of the prepreg (201) on which the element attachment sheet (8) overlaps. To do. At this time, since heat is applied to the element attachment sheet (8), the capacitor element (1) is easily peeled off from the carrier sheet (80).
  • the capacitor element (1) is peeled from the carrier sheet (80) by peeling the carrier sheet (80) from the insulating base (20) in the latter stage of the peeling step. As a result, the capacitor element (1) is mounted at a predetermined position on the insulating substrate (20).
  • the carrier sheet (80) A non-peelable sheet such as a PET (polyethylene terephthalate) sheet having adhesiveness can be used.
  • FIG. 15 is a perspective view for explaining a stacking process of a method for producing a capacitor built-in substrate.
  • a lamination process is a process performed after execution of an element mounting process.
  • another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20).
  • the insulating substrate (2) is formed by the two insulating base materials (20) laminated.
  • a first conductive via (31) and a second conductive via (32) are formed on the insulating substrate (2), and a ground terminal is formed on the upper surface (21) of the insulating substrate (2). (41) and a power supply terminal (42) are formed. As a result, the capacitor built-in substrate is completed.
  • the capacitor element (1) mounted on the insulating base (20) has a small thickness and is in the form of a sheet.
  • Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the element mounting process for mounting the capacitor element (1) on the insulating base material (20) is complicated. Become.
  • the capacitor element (1) is mounted at a predetermined position on the insulating base (20) using the element attachment sheet (8) to which the capacitor element (1) is attached. For this reason, it is not necessary to handle the capacitor elements (1) individually, and the element mounting process for mounting the capacitor elements (1) on the insulating substrate (20) is simplified.
  • the first conductive layer (11) of the capacitor element (1) made of metal foil is hardly damaged even when it is peeled off after being stuck on the carrier sheet (80). Therefore, like the mounting method of the capacitor element (1), after the first electrode layer (11) is attached to the carrier sheet (80) in the attaching step, the capacitor element (1) is attached to the carrier sheet in the releasing step. Even when peeled from (80), the first electrode layer (11) is hardly damaged.
  • substrate with a built-in capacitor exists in the range of 5 micrometers or more and 100 micrometers or less. This is because when the thickness is smaller than 5 ⁇ m, it is difficult to handle the capacitor element (1), and problems such as an increase in resistance occur. Further, when the thickness dimension is larger than 100 ⁇ m, the thickness of the capacitor element (1) affects the surface of the insulating base material (20), so that irregularities are formed on the surface of the insulating base material (20). This is because it becomes difficult to laminate another insulating base material (20) thereon.
  • FIG. 16 is a plan view of the capacitor built-in substrate according to the first modified example of the present invention when the capacitor element (1) built in the capacitor built-in substrate is viewed from the second electrode layer (12) side.
  • the first conductive via (31) is located on the upper surface (111) of the first electrode layer (11) over the region (113) not covered by the second electrode layer (12).
  • the second conductive vias (32) are formed at 25 locations on the upper surface (121) of the second electrode layer (12), and the first conductive vias (31) to (31) are formed.
  • the second conductive vias (32) to (32) may be arranged in a 7 ⁇ 7 matrix on the paper surface of FIG.
  • FIG. 17 is a plan view of the capacitor-embedded substrate according to the second modification of the present invention when the capacitor element (1) built in the capacitor-embedded substrate is viewed from the second electrode layer (12) side.
  • An electrode layer (12) may be provided, and the second electrode layers (12) provided at the four locations may be arranged apart from each other.
  • the conductive vias arranged in the first row, the fourth row, and the seventh row, the first column A total of 33 conductive vias arranged in the row and the seventh row are first conductive vias (31), and the other 16 conductive vias are second conductive vias (32).
  • the 16 second conductive vias (32) are connected to the second electrode layers (12) provided at the four locations, four by four.
  • the number of the first conductive vias (31) can be increased.
  • the first conductive via (31) has a gap between the second conductive via (32). There are many things with the smallest distance. Therefore, the inductance generated in the capacitor built-in substrate can be further reduced.
  • FIG. 18 is a cross-sectional view showing a capacitor built-in substrate according to a third modification of the present invention.
  • the surface of the insulating substrate (2) opposite to the second electrode layer (12) of the first electrode layer (11) of the capacitor element (1) (114) A third conductive via (33) electrically connected to the lower surface (the lower surface in FIG. 1 and FIG. 18) is formed, and the third conductive via (33) is formed on the lower surface of the insulating substrate (2) ( 22) and the tip of the third conductive via (33) may be exposed on the lower surface (22).
  • FIG. 19 is a cross-sectional view showing a capacitor built-in substrate according to a fourth modification of the present invention.
  • the dielectric layer (13) is formed on the upper surface (111) of the first electrode layer (11) on the region (112) covered with the second electrode layer (12). In addition, it may be formed on a region (113) not covered with the second electrode layer (12).
  • the first conductive via (31) extends through the dielectric layer (13) toward the upper surface (21) of the insulating substrate (2).
  • the second electrode layer (12) of the capacitor element (1) may be formed of a metal foil.
  • the shape of the first electrode layer (11) and the second electrode layer (12) of the capacitor element (1) is not limited to a substantially square shape, but the first electrode layer (11) and the second electrode layer (12). ) Various shapes can be used.
  • the first electrode layer (11) of the capacitor element (1) may be formed integrally with a power supply pattern or a ground pattern formed in the insulating substrate (2).
  • the first conductive via (31) may be formed only at one location in the insulating substrate (2).
  • the second conductive via (32) may be formed only at one place in the insulating substrate (2).
  • Capacitor element (11) First electrode layer (12) Second electrode layer (13) Dielectric layer (2) Insulating substrate (20) Insulating substrate (31) First conductive via (32) Second conductive via (33) Third conductive via (41) Ground terminal (42) Power supply terminal (8) Element attachment sheet (80) Carrier sheet (81) Predetermined area

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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention porte sur un procédé de fabrication d'un substrat avec un condensateur incorporé, dans lequel procédé un processus pour monter des éléments de condensateur sur un matériau de base isolant est simplifié. Le procédé de fabrication d'un substrat avec un condensateur incorporé met en œuvre un processus de collage, un processus d'arrachage et un processus de stratification. Dans le processus de collage, une feuille à laquelle sont attachés des éléments (8) est créée, à l'aide d'une feuille (80) qui peut comporter des éléments de condensateur (1) collés ou arrachés par application d'une action externe sur celle-ci, et par collage et fixation de l'élément de condensateur (1) sur une ou sur une pluralité de zones prescrites à l'intérieur de la surface de la feuille (80). Dans le processus d'arrachage, les éléments de condensateur (1) sont arrachés de la feuille (8) et montés sur le matériau de base isolant (20), par superposition de la feuille sur laquelle sont attachés des éléments (8) sur une position prescrite du matériau de base isolant (20), la feuille sur laquelle sont attachés des éléments (8) prenant une position dans laquelle les éléments de condensateur (1) qui sont attachés sur celle-ci sont dirigés vers le matériau de base isolant (20), et application d'une action externe sur la feuille sur laquelle sont attachés des éléments (8) dans cet état pour arracher les éléments de condensateur (1). Dans le processus de stratification, un substrat isolant est formé par stratification d'un autre matériau de base isolant (20) sur le matériau de base isolant (20).
PCT/JP2010/071976 2010-01-15 2010-12-08 Procédé de fabrication de substrat avec condensateur incorporé WO2011086797A1 (fr)

Applications Claiming Priority (2)

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JP2010-007412 2010-01-15
JP2010007412A JP2013062266A (ja) 2010-01-15 2010-01-15 コンデンサ内蔵基板の製造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116344519A (zh) * 2023-03-01 2023-06-27 河北杰微科技有限公司 衬底集成电容及其制备方法和olt结构

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH08264948A (ja) * 1995-03-16 1996-10-11 Robert Bosch Gmbh 多層印刷配線回路の製造方法
JPH1126943A (ja) * 1997-06-30 1999-01-29 Kyocera Corp 多層配線基板およびその製造方法
JP2006237132A (ja) * 2005-02-23 2006-09-07 Ngk Spark Plug Co Ltd 配線基板及び配線基板の製造方法
JP2009043769A (ja) * 2007-08-06 2009-02-26 Ngk Spark Plug Co Ltd コンデンサ内蔵配線基板及びその製造方法、支持体付きコンデンサ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08264948A (ja) * 1995-03-16 1996-10-11 Robert Bosch Gmbh 多層印刷配線回路の製造方法
JPH1126943A (ja) * 1997-06-30 1999-01-29 Kyocera Corp 多層配線基板およびその製造方法
JP2006237132A (ja) * 2005-02-23 2006-09-07 Ngk Spark Plug Co Ltd 配線基板及び配線基板の製造方法
JP2009043769A (ja) * 2007-08-06 2009-02-26 Ngk Spark Plug Co Ltd コンデンサ内蔵配線基板及びその製造方法、支持体付きコンデンサ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116344519A (zh) * 2023-03-01 2023-06-27 河北杰微科技有限公司 衬底集成电容及其制备方法和olt结构

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