WO2018163859A1 - Substrat multicouche, appareil électronique et procédé de production de substrat multicouche - Google Patents

Substrat multicouche, appareil électronique et procédé de production de substrat multicouche Download PDF

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Publication number
WO2018163859A1
WO2018163859A1 PCT/JP2018/006679 JP2018006679W WO2018163859A1 WO 2018163859 A1 WO2018163859 A1 WO 2018163859A1 JP 2018006679 W JP2018006679 W JP 2018006679W WO 2018163859 A1 WO2018163859 A1 WO 2018163859A1
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WIPO (PCT)
Prior art keywords
insulating base
mounting
base material
multilayer substrate
material layer
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PCT/JP2018/006679
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English (en)
Japanese (ja)
Inventor
伊藤　慎悟
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株式会社村田製作所
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Priority to CN201890000453.6U priority Critical patent/CN210899888U/zh
Publication of WO2018163859A1 publication Critical patent/WO2018163859A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a multilayer substrate, and in particular, a multilayer substrate formed by laminating a plurality of insulating base layers, and a conductor pattern formed on the insulating base layer, and an electronic including the multilayer substrate
  • the present invention also relates to a device and a method for manufacturing the multilayer substrate.
  • Patent Document 1 in a structure in which a plurality of insulating base material layers having a conductor pattern attached to the surface is laminated, the surface roughness on one main surface side of the conductor pattern attached to the insulating base material layer is on the other hand, a multilayer substrate having a surface roughness larger than that of the main surface is disclosed. With this configuration, the bonding strength of the conductor pattern to the insulating base layer can be increased.
  • the mounting surface of the mounting electrode for mounting the multilayer substrate on the mounting substrate or the like is the other main surface of the conductor pattern having a relatively smaller surface roughness than the one main surface. . Therefore, the contact area of the mounting electrode with respect to the conductive bonding material is small, high bonding strength cannot be obtained, and the multilayer substrate may be peeled off from the mounting substrate or the like after mounting.
  • An object of the present invention is to provide a mounting board when mounted on a mounting board or the like in a configuration including a laminate formed by laminating a plurality of insulating base layers and a mounting electrode formed on the insulating base layer. It is an object of the present invention to provide a multilayer substrate that can ensure a sufficient bonding strength with respect to the above.
  • the multilayer substrate of the present invention is A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer; A mounting electrode that has a first surface and a second surface opposite to the first surface, and is formed on any of the plurality of insulating base layers; With The mounting electrode has the first insulating base layer so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer. And the second insulating base material layer, The surface roughness of the first surface is greater than the surface roughness of the second surface, The first insulating base material layer has a base material layer non-forming portion that exposes a part of the first surface.
  • the second surface of the mounting electrode is conductive.
  • the contact area of the mounting electrode with respect to the conductive bonding material is increased as compared with the case where the bonding electrode is bonded to the mounting substrate or the like. Therefore, with this configuration, the conductive bonding material and the mounting electrode can be bonded with high bonding strength, and peeling of the multilayer substrate from the mounting substrate or the like after mounting can be suppressed. Also, with this configuration, the conductor loss of the mounting electrode can be reduced as compared with the case where the surface roughness of both the first surface and the second surface of the mounting electrode is large.
  • a said 1st insulating base material layer and a said 2nd insulating base material layer consist of the same resin material.
  • the mounting electrode does not reach the outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers.
  • the mounting electrode reaches the surface of the multilayer body (when it is exposed on the surface of the multilayer body)
  • the mounting electrode is easily peeled from the multilayer substrate by applying an external force to the exposed portion of the mounting electrode.
  • the mounting electrode since the mounting electrode is not exposed from the outer edge (surface) of the mounting surface of the laminate, it is possible to suppress the peeling of the mounting electrode from the multilayer substrate due to the application of external force. Also, with this configuration, it is possible to prevent peeling of the mounting electrode from the laminate due to stress applied to the end portion of the mounting electrode when separating the individual pieces from the collective substrate.
  • the first insulating base layer covers more than half of the outer periphery of the first surface.
  • the mounting electrode is disposed in the vicinity of an outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers, and the base layer non-forming portion is the plurality of base layers. It is preferable to reach the outer edge of the mounting surface when viewed from the stacking direction of the insulating base layer.
  • the electronic device of the present invention The multilayer substrate according to any one of (1) to (5) above; A mounting board; With The first surface of the mounting electrode is bonded to the mounting substrate through a conductive bonding material.
  • the conductive bonding material and the mounting electrode can be bonded with high bonding strength, and an electronic device in which peeling of the multilayer substrate from the mounting substrate after mounting can be realized.
  • the electronic device of the present invention The multilayer substrate according to the above (4) or (5); A mounting board; With The first surface of the mounting electrode is bonded to the mounting substrate by forming a solder fillet.
  • the method for producing the multilayer substrate of the present invention comprises: A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer; A mounting electrode facing the first surface and the first surface, having a second surface having a smaller surface roughness than the first surface, and formed on any of the plurality of insulating base layers; A method for producing a multilayer substrate comprising: Forming the mounting electrode such that the first surface is in contact with the surface of the first insulating base layer; After the electrode forming step, the plurality of insulating base layers are formed so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer.
  • the laminated body is formed by heating and pressurizing the plurality of laminated insulating base material layers, and the mounting electrode is embedded in the laminated body.
  • the layered body forming step the layered body is removed from the mounting surface side, and a base material layer non-forming portion that exposes a part of the first surface is formed on the first insulating base material layer. Process, It is characterized by providing.
  • the mounting substrate is mounted on the mounting substrate or the like. It is possible to realize a multi-layer substrate that can ensure sufficient bonding strength to the above.
  • FIG. 1 is a perspective view of a multilayer substrate 101 according to the first embodiment.
  • 2A is an AA cross-sectional view in FIG. 1, and
  • FIG. 2B is an exploded cross-sectional view of the multilayer substrate 101.
  • FIG. 3 is a bottom view of the multilayer substrate 101.
  • FIG. 4 is a cross-sectional view illustrating a main part of the electronic apparatus 301 according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps of the multilayer substrate 101.
  • FIG. 6 is a perspective view of the multilayer substrate 102 according to the second embodiment.
  • 7A is a cross-sectional view taken along the line BB in FIG. 6, and
  • FIG. 7B is a bottom view of the multilayer substrate 102.
  • FIG. 8 is a cross-sectional view illustrating a main part of the electronic device 302 according to the second embodiment.
  • FIG. 1 is a perspective view of a multilayer substrate 101 according to the first embodiment.
  • 2A is an AA cross-sectional view in FIG. 1
  • FIG. 2B is an exploded cross-sectional view of the multilayer substrate 101.
  • FIG. 3 is a bottom view of the multilayer substrate 101. 2A and 2B, the thickness of each insulating base material layer and the surface roughness of the mounting electrode are exaggerated. The same applies to the cross-sectional views shown below. Further, in FIG. 3, in order to make the structure easy to understand, a portion exposed from the stacked body in the first surface of the mounting electrode is shown by a dot pattern.
  • the multilayer substrate 101 includes a laminated body 10A formed by laminating a plurality of insulating base layers 11, 12, 13, 14, and 15, mounting electrodes P1 and P2, a plurality of conductors 21, 22, 23, 24, and 25, and A plurality of interlayer connection conductors V1, V2, etc. are provided.
  • the laminated body 10A is a substantially rectangular parallelepiped made of a thermoplastic resin whose longitudinal direction coincides with the X-axis direction, and has a first main surface VS1 and a second main surface VS2 facing each other.
  • the laminated body 10A is formed by laminating a plurality of insulating base material layers 11, 12, 13, 14, and 15 in this order.
  • the plurality of insulating base material layers 11, 12, 13, 14, and 15 are thermoplastic resin flat plates each having a rectangular planar outer shape.
  • the insulating base layers 11, 12, 13, 14, 15 are resin sheets whose main material is, for example, liquid crystal polymer (LCP) or polyether ether ketone (PEEK).
  • the first main surface VS1 of the stacked body 10A corresponds to the “mounting surface” in the present invention.
  • the insulating base material layer 11 corresponds to the “first insulating base material layer” in the present invention
  • the insulating base material layers 12, 13, 14, and 15 are the “second insulating base material layer” in the present invention. Is equivalent to.
  • the mounting electrodes P1 and P2 are rectangular conductors formed on any of the plurality of insulating base layers 11, 12, 13, 14, and 15, and have a first surface S1 and a second surface facing each other.
  • the mounting electrodes P1 and P2 are conductor patterns such as Cu foil, for example.
  • the surface roughness (Ra1) of the first surfaces S1A and S1B of the mounting electrodes P1 and P2 is larger than the surface roughness (Ra2) of the second surfaces S2A and S2B (Ra1> Ra2).
  • the surfaces of the first surfaces S1A and S1B of the mounting electrode P1 are roughened by, for example, a sand blaster method, a plasma method, a plating method, an etching method, or the like.
  • the surface roughness of the first surfaces S1A and S1B is 0.5 ⁇ m, for example, and the surface roughness of the second surfaces S2A and S2B is 0.2 ⁇ m, for example.
  • the standard (arithmetic average roughness) defined in [JIS B 0601-2001] is adopted.
  • the mounting electrodes P1 and P2 have the first surfaces S1A and S1B facing the first insulating base layer (insulating base layer 11), and the second surfaces S2A and S2B have the second insulating base layer (insulating). It is sandwiched between the first insulating base layer and the second insulating base layer so as to face the base layer 12).
  • the first insulating base material layer has rectangular base material layer non-forming portions NFP1 and NFP2 that expose a part of the first surfaces S1A and S1B.
  • the first insulating base material layer covers the entire outer periphery of the first surfaces S1A and S1B, and the center of the first surfaces S1A and S1B. The part is exposed from the laminated body 10A as shown in FIG.
  • the mounting electrodes P1 and P2 are viewed from the stacking direction (Z-axis direction) of the plurality of insulating base material layers 11, 12, 13, 14, and 15, and the first main surface ( It is arranged near the outer edge of the mounting surface.
  • the mounting electrode P1 is disposed in the vicinity of the first side of the mounting surface (the left side of the first main surface of the stacked body 10A in FIG. 3) as viewed from the Z-axis direction.
  • the mounting electrode P2 is disposed in the vicinity of the second side of the mounting surface (the right side of the first main surface of the stacked body 10A in FIG. 3) as viewed from the Z-axis direction.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
  • the plurality of conductors 21, 22, 23, 24, and 25 and the plurality of interlayer connection conductors V1 and V2 are conductors formed in the multilayer body 10A.
  • the conductor 21 is a conductor pattern formed on the surface of the insulating base material layer 12.
  • the conductors 22 and 23 are conductor patterns formed on the surface of the insulating base material layer 13.
  • the conductors 24 and 25 are conductor patterns formed on the surface of the insulating base material layer 14.
  • the conductor 21 and the conductor 22 are connected to each other via an interlayer connection conductor V1 formed on the insulating base material layer 13.
  • the conductor 23 and the conductor 24 are connected to each other through an interlayer connection conductor V2 formed on the insulating base layer 14.
  • the conductors 21, 22, 23, 24, and 25 are conductor patterns such as Cu foil, for example.
  • FIG. 4 is a cross-sectional view illustrating a main part of the electronic apparatus 301 according to the first embodiment.
  • the electronic device 301 includes a multilayer substrate 101, a mounting substrate 201, and the like. As shown in FIG. 4, the multilayer substrate 101 is mounted on the mounting substrate 201.
  • the mounting board 201 is, for example, a printed wiring board.
  • Conductors 41 and 42 are formed on the main surface of the mounting substrate 201.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the conductors 41 and 42 of the mounting substrate 201 via the conductive bonding material 1, respectively.
  • the conductive bonding material 1 is, for example, solder.
  • the multilayer substrate 101 according to this embodiment has the following effects.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the mounting substrate or the like via the conductive bonding material 1, and the surface roughness (Ra1) of the first surfaces S1A and S1B Is larger than the surface roughness (Ra2) of the second surfaces S2A and S2B (Ra1> Ra2). Therefore, compared with the case where the second surfaces S2A and S2B of the mounting electrode P2 are bonded to the mounting substrate or the like via the conductive bonding material 1, the contact area of the mounting electrodes P1 and P2 with respect to the conductive bonding material 1 is increased.
  • the conductive bonding material 1 and the mounting electrodes P1 and P2 can be bonded with high bonding strength, and peeling of the multilayer substrate 101 from the mounting substrate or the like after mounting can be suppressed.
  • the conductor loss of the mounting electrodes P1 and P2 can be reduced as compared with the case where the surface roughness of the first surfaces S1A and S1B and the second surfaces S2A and S2B of the mounting electrodes P1 and P2 is large.
  • FIGS. 2A and 3 In the multilayer substrate 101, as shown in FIGS. 2A and 3, a part of the mounting electrodes P1 and P2 (outer edge portions of the mounting electrodes P1 and P2 in FIG. It is sandwiched between the material layer (insulating base material layer 11) and the second insulating base material layer (insulating base material layer 12). Therefore, compared with the case where mounting electrodes P1 and P2 are formed on the surface of stacked body 10A, mounting electrodes P1 and P2 can be made difficult to peel from stacked body 10A.
  • the first insulating base layer (insulating base layer 11) and the second insulating base layer (insulating base layer 12) are made of the same resin material. With this configuration, there is no physical property difference between the first insulating base material layer and the second insulating base material layer sandwiching part of the mounting electrodes P1 and P2, and the first insulating base material layer and the second insulating base material layer The bonding strength between the two increases. Therefore, peeling of the mounting electrodes P1 and P2 from the multilayer substrate is suppressed.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface VS1 (mounting surface) when viewed from the Z-axis direction.
  • an external force is applied to the exposed portions of the mounting electrodes P1 and P2, thereby causing the mounting electrodes P1 and P2 to be exposed.
  • P2 becomes easy to peel from the multilayer substrate.
  • this configuration since the mounting electrodes P1 and P2 are not exposed from the outer edge (surface) of the mounting surface of the multilayer body 10A, peeling of the mounting electrodes P1 and P2 from the multilayer substrate due to an external force can be suppressed.
  • this configuration eliminates the need to separate the mounting electrodes P1 and P2 when separating individual pieces (multilayer substrates) from the collective substrate (described in detail later). Therefore, it is possible to prevent peeling of the mounting electrodes P1 and P2 from the stacked body 10A due to stress applied to the end portions of the mounting electrodes P1 and P2 during manufacturing.
  • the first insulating base layer (insulating base layer 11) covers the entire outer periphery of the first surfaces S1A and S1B. With this configuration, it is possible to make it difficult to peel the mounting electrode from the multilayer substrate (laminated body) as compared with the case where the first insulating base material layer covers a part of the outer periphery of the first surfaces S1A and S1B of the mounting electrodes P1 and P2.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 of the multilayer substrate 101 are bonded to the mounting substrate 201 via the conductive bonding material 1.
  • the conductive bonding material 1 and the mounting electrodes P1 and P2 can be bonded with high bonding strength, and an electronic device in which peeling of the multilayer substrate from the mounting substrate 201 or the like can be realized after mounting.
  • FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps of the multilayer substrate 101.
  • FIG. 5 for the convenience of explanation, the manufacturing process using one chip (individual piece) will be described. However, the actual manufacturing process of the diaphragm is performed in a collective substrate state.
  • insulating base material layers 11, 12, 13, 14, and 15 are prepared.
  • the insulating base layers 11, 12, 13, 14, and 15 are thermoplastic resin sheets such as liquid crystal polymer (LCP) or polyether ether ketone (PEEK).
  • mounting electrodes P1 and P2 having first surfaces S1A and S1B and second surfaces S2A and S2B facing each other are formed on the insulating base layer 11 (first insulating base layer).
  • a metal foil for example, Cu foil
  • the metal foil is patterned by photolithography to form mounting electrodes P1 and P2.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are roughened.
  • the first surfaces S1A and S1B are roughened by, for example, a sand blaster method, a plasma method, a plating method, an etching method, or the like.
  • This step of forming the mounting electrodes P1, P2 so that the first surfaces S1A, S1B are in contact with the surface of the first insulating base layer (insulating base layer 11) is an example of the “electrode forming step” in the present invention. is there.
  • conductors 21, 22, 23, 24, 25, etc. are respectively formed on the plurality of insulating base material layers 12, 13, 14 (second insulating base material layers).
  • a metal foil for example, Cu foil
  • the metal foil is laminated on one side main surface of the insulating base material layers 12, 13, and 14 in the aggregated substrate state, and the metal foil is patterned by photolithography, whereby the conductor 21 , 22, 23, 24, 25, and the like.
  • one surface of the conductors 21, 22, 23, 24, 25 in contact with the insulating base material layers 12, 13, 14 is the mounting electrode P1 described above.
  • P2 are roughened in the same manner as the first surfaces S1A and S1B.
  • interlayer connection conductors V1 and V2 are formed on the plurality of insulating base material layers 13 and 14, respectively.
  • Interlayer connection conductors V1 and V2 are made of a conductive paste containing one or more of Cu, Ag, Sn, Ni, Mo, etc. or an alloy thereof after providing through holes in insulating base layers 13 and 14 with a laser or the like. It is provided by being disposed and cured (solidified) by subsequent heating and pressing. Therefore, the interlayer connection conductors V1 and V2 are made of a material having a melting point (melting temperature) lower than the temperature at the time of subsequent heating and pressurization.
  • the insulating base layers 11, 12, 13, 14, and 15 are laminated in this order.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are opposed to the first insulating base layer (insulating base layer 11), and the second surfaces S2A and S2B are the second insulating base layer (insulating).
  • a plurality of insulating base layers 11, 12, 13, 14, and 15 are laminated so that the second surfaces S2A and S2B face the base layer 12).
  • a plurality of insulating base materials are provided such that the first surfaces S1A and S1B face the first insulating base material layer and the second surfaces S2A and S2B face the second insulating base material layer.
  • This step of laminating the layers 11, 12, 13, 14, and 15 is an example of the “lamination step” in the present invention.
  • the stacked body 10AP is configured. At this time, the mounting electrodes P1 and P2 are embedded in the stacked body 10AP.
  • the laminated insulating base material layers 11, 12, 13, 14, and 15 are heated and pressurized to form the laminated body 10AP, and the mounting electrodes P1 and P2 are disposed inside the laminated body 10AP.
  • This step of embedding in the substrate is an example of the “laminated body forming step” in the present invention.
  • the laminated body 10AP is removed, and the first insulating base material layer (insulating base material layer 11) is exposed to a part of the first surfaces S1A and S1B.
  • the material layer non-formation parts NFP1 and NFP2 are formed.
  • the first main surface VS1 of the stacked body 10AP is formed by a laser beam LR that is irradiated toward the stacking direction (Z-axis direction).
  • the laser beam LR is blocked by the mounting electrodes P1 and P2 embedded in the stacked body 10AP. Therefore, by using this manufacturing method, it is possible to easily form the base material layer non-forming portions NFP1, NFP2 that expose a part of the first surfaces S1A, S1B.
  • the layered body 10AP is removed from the mounting surface side, and the base material from which the first surfaces S1A and S1B are partially exposed to the first insulating base material layer (insulating base material layer 11).
  • This step of forming the layer non-forming portions NFP1 and NFP2 is an example of the “removal step” in the present invention.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface VS1 (mounting surface) when viewed from the Z-axis direction. Therefore, when separating the individual pieces (multilayer substrate) from the collective substrate, it is not necessary to separate the mounting electrodes P1 and P2 into individual pieces. Therefore, it is possible to prevent the mounting electrodes P1 and P2 from being peeled off from the stacked body 10A during manufacturing.
  • the plurality of insulating base material layers 11, 12, 13, 14, and 15 forming the laminate are made of a thermoplastic resin. According to the manufacturing method described above, since the laminated body 10A can be easily formed by collectively pressing the plurality of laminated insulating base material layers 11, 12, 13, 14, and 15, the man-hours for the manufacturing process of the insulating base material are reduced. The cost can be kept low.
  • Second Embodiment the example of the multilayer substrate from which the structure of a base material layer non-formation part differs is shown.
  • FIG. 6 is a perspective view of the multilayer substrate 102 according to the second embodiment.
  • 7A is a cross-sectional view taken along the line BB in FIG. 6, and
  • FIG. 7B is a bottom view of the multilayer substrate 102.
  • a portion of the first surface of the mounting electrode that is exposed from the stacked body is indicated by a dot pattern.
  • the multilayer substrate 102 includes a laminated body 10B formed by laminating a plurality of insulating base layers 11, 12, 13, 14, and 15, mounting electrodes P1 and P2, a plurality of conductors 21, 22, 23, 24, and 25, and A plurality of interlayer connection conductors V1, V2, etc. are provided.
  • the multilayer substrate 102 is different from the multilayer substrate 101 according to the first embodiment in the shapes of the base material layer non-forming portions NFP1 and NFP2. Other configurations are substantially the same as those of the multilayer substrate 101.
  • the base material layer non-forming portions NFP1, NFP2 reach the outer edge of the first main surface (mounting surface) as viewed from the Z-axis direction (the base material layer non-forming portion in FIG. 7B). (See the left side of the forming part NFP1 and the right side of the base material layer non-forming part NFP2).
  • the first insulating base material layer (see the insulating base material layer 11 in FIG. 7A) is the outer periphery of the first surface (S1A, S1B). Covers more than half. Specifically, the first insulating base layer covers about 3/4 of the outer periphery of the first surface (S1A) (the upper side, the right side, and the lower side of the mounting electrode P1 in FIG. 7B). In addition, the first insulating base layer covers about 3/4 of the outer periphery of the first surface (S1B) (the upper side, the left side, and the lower side of the mounting electrode P2 in FIG. 7B).
  • FIG. 8 is a cross-sectional view illustrating a main part of the electronic device 302 according to the second embodiment.
  • the electronic device 302 includes a multilayer substrate 102, a mounting substrate 201, and the like. As shown in FIG. 8, the multilayer substrate 102 is mounted on the mounting substrate 201.
  • the mounting substrate 201 is the same as that described in the first embodiment.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the conductors 41 and 42 of the mounting substrate 201 through the conductive bonding material 1, respectively. As shown in FIG. 8, the first surfaces S1A and S1B are bonded to the mounting substrate 201 by forming solder fillets.
  • the multilayer substrate 102 according to the present embodiment has the following effects in addition to the effects described in the first embodiment.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
  • the base material layer non-forming portions NFP1, NFP2 reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
  • the example of the multilayer substrate in which the first insulating base material layer covers about 3/4 of the outer periphery of the first surface (S1A, S1B) is shown, but the present invention is limited to this configuration. is not. If the first insulating base layer (insulating base layer 11) covers more than half of the outer periphery of the first surface (S1A, S1B), it is difficult to peel the mounting electrodes P1, P2 from the multilayer substrate (laminated body). The effect
  • the laminated body 10A, 10B showed the example which is a substantially rectangular parallelepiped shape, it is not limited to this structure.
  • the planar shape of the laminate can be changed as appropriate within the range where the functions and effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse, an L shape, a crank shape, a T shape, a Y shape, or the like.
  • the some insulating base material layers 11, 12, 13, 14, and 15 which form a laminated body consist of a thermoplastic resin is not limited to this structure.
  • the plurality of insulating base layers 11, 12, 13, 14, and 15 may be thermosetting resins.
  • the insulating base material layers 11, 12, 13, 14, and 15 are thermoplastic resins, the insulating base material can be easily formed as described above, thereby reducing the number of steps in the manufacturing process of the multilayer substrate. Cost can be kept low.
  • the multilayer substrate provided with the laminated body formed by laminating the five insulating base material layers 11, 12, 13, 14, and 15 has been described.
  • the present invention is not limited to this configuration. It is not something.
  • the number of insulating base material layers forming the laminate can be changed as appropriate within the range where the functions and effects of the present invention are exhibited.
  • one first insulating base material layer (insulating base material layer 11) and four second insulating base material layers (insulating base material layers 12, 13, 14, 15) are laminated.
  • the number of the first insulating base layers and the number of the second insulating base layers are not limited thereto.
  • the number of the first insulating base material layers and the number of the second insulating base material layers can be appropriately changed within a range where the functions and effects of the present invention are exhibited.
  • the number of first insulating base layers may be two or more, for example.
  • the number of the second insulating base layers may be one or two or more.
  • the present invention is not limited to this configuration.
  • the shape of the mounting electrode can be changed as appropriate within the scope of the operation and effect of the present invention.
  • the mounting electrode may be polygonal, circular, elliptical, L-shaped, crank-shaped, T-shaped, Y-shaped, or the like.
  • the number of mounting electrodes can be appropriately changed according to a circuit formed on the multilayer substrate.
  • the 1st insulating base material layer showed the example which has rectangular base material layer non-formation part NFP1, NFP2, it is not limited to this structure.
  • the shape of the base material layer non-forming part can be appropriately changed within the range where the functions and effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse or the like.
  • the number of base material layer non-formation parts is not limited to two, and may be one or three or more.
  • stacking several insulating base material layers 11, 12, 13, 14, and 15 protection of a solder resist film, a coverlay film, etc. was shown.
  • the layer may be formed on the first main surface VS1 or the second main surface VS2 of the stacked body.
  • the circuit formed on the multilayer substrate can be freely configured as long as the operations and effects of the present invention are achieved.
  • a transmission line such as a stripline structure, a microstripline structure, or a coplanar line may be formed on the multilayer substrate, and for example, a coil or a capacitor formed of a conductor pattern may be formed.
  • chip components such as chip inductors and chip capacitors may be mounted on the multilayer substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un substrat multicouche pourvu d'un stratifié (10A), formé par la stratification d'une pluralité de couches de substrat isolant (11, 12, 13, 14, 15) et d'électrodes de montage (P1, P2) comportant des premières surfaces mutuellement opposées (S1A, S1B) et des deuxièmes surfaces (S2A, S2B). Les électrodes de montage (P1, P2) sont placées entre une première couche de substrat isolant (couche de substrat isolant (11)) et une deuxième couche de substrat isolant (couche de substrat isolant (12)), de sorte que la première surface (S1A) fait face à la première couche de substrat isolant, et que les deuxièmes surfaces (S2A, S2B) font face à la deuxième couche de substrat isolant. La rugosité de surface (Ra1) des premières surfaces (S1A, S1B) est supérieure à la rugosité de surface (Ra2) des deuxièmes surfaces (S2A, S2B) (Ra1 > Ra2). La première couche de substrat isolant (couche de substrat isolant (11)) comporte des parties ne formant pas de couche de substrat (NFP1, NFP2), dans lesquelles des parties des premières surfaces (S1A, S1B) sont découvertes.
PCT/JP2018/006679 2017-03-06 2018-02-23 Substrat multicouche, appareil électronique et procédé de production de substrat multicouche WO2018163859A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020071473A1 (fr) * 2018-10-04 2020-04-09 株式会社村田製作所 Corps stratifié et son procédé de production
JPWO2021261416A1 (fr) * 2020-06-24 2021-12-30

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4816157A (fr) * 1971-07-08 1973-03-01
JP2004207636A (ja) * 2002-12-26 2004-07-22 Fujikura Ltd 多層配線板およびその製造方法
JP2005072085A (ja) * 2003-08-28 2005-03-17 Ngk Spark Plug Co Ltd 配線基板の製造方法、及び配線基板
JP2011258590A (ja) * 2010-06-04 2011-12-22 Shinko Electric Ind Co Ltd 配線基板及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4816157A (fr) * 1971-07-08 1973-03-01
JP2004207636A (ja) * 2002-12-26 2004-07-22 Fujikura Ltd 多層配線板およびその製造方法
JP2005072085A (ja) * 2003-08-28 2005-03-17 Ngk Spark Plug Co Ltd 配線基板の製造方法、及び配線基板
JP2011258590A (ja) * 2010-06-04 2011-12-22 Shinko Electric Ind Co Ltd 配線基板及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020071473A1 (fr) * 2018-10-04 2020-04-09 株式会社村田製作所 Corps stratifié et son procédé de production
JPWO2020071473A1 (ja) * 2018-10-04 2021-09-02 株式会社村田製作所 積層体及びその製造方法
US11445606B2 (en) 2018-10-04 2022-09-13 Murata Manufacturing Co., Ltd. Laminated body and method for manufacturing the same
JP7283481B2 (ja) 2018-10-04 2023-05-30 株式会社村田製作所 積層体及びその製造方法
JPWO2021261416A1 (fr) * 2020-06-24 2021-12-30
WO2021261416A1 (fr) * 2020-06-24 2021-12-30 株式会社村田製作所 Substrat de résine à couches multiples et son procédé de production
JP7315102B2 (ja) 2020-06-24 2023-07-26 株式会社村田製作所 樹脂多層基板

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