WO2018163859A1 - Multi-layer substrate, electronic apparatus, and method for producing multi-layer substrate - Google Patents

Multi-layer substrate, electronic apparatus, and method for producing multi-layer substrate Download PDF

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Publication number
WO2018163859A1
WO2018163859A1 PCT/JP2018/006679 JP2018006679W WO2018163859A1 WO 2018163859 A1 WO2018163859 A1 WO 2018163859A1 JP 2018006679 W JP2018006679 W JP 2018006679W WO 2018163859 A1 WO2018163859 A1 WO 2018163859A1
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WO
WIPO (PCT)
Prior art keywords
insulating base
mounting
base material
multilayer substrate
material layer
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PCT/JP2018/006679
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French (fr)
Japanese (ja)
Inventor
伊藤　慎悟
Original Assignee
株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201890000453.6U priority Critical patent/CN210899888U/en
Publication of WO2018163859A1 publication Critical patent/WO2018163859A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a multilayer substrate, and in particular, a multilayer substrate formed by laminating a plurality of insulating base layers, and a conductor pattern formed on the insulating base layer, and an electronic including the multilayer substrate
  • the present invention also relates to a device and a method for manufacturing the multilayer substrate.
  • Patent Document 1 in a structure in which a plurality of insulating base material layers having a conductor pattern attached to the surface is laminated, the surface roughness on one main surface side of the conductor pattern attached to the insulating base material layer is on the other hand, a multilayer substrate having a surface roughness larger than that of the main surface is disclosed. With this configuration, the bonding strength of the conductor pattern to the insulating base layer can be increased.
  • the mounting surface of the mounting electrode for mounting the multilayer substrate on the mounting substrate or the like is the other main surface of the conductor pattern having a relatively smaller surface roughness than the one main surface. . Therefore, the contact area of the mounting electrode with respect to the conductive bonding material is small, high bonding strength cannot be obtained, and the multilayer substrate may be peeled off from the mounting substrate or the like after mounting.
  • An object of the present invention is to provide a mounting board when mounted on a mounting board or the like in a configuration including a laminate formed by laminating a plurality of insulating base layers and a mounting electrode formed on the insulating base layer. It is an object of the present invention to provide a multilayer substrate that can ensure a sufficient bonding strength with respect to the above.
  • the multilayer substrate of the present invention is A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer; A mounting electrode that has a first surface and a second surface opposite to the first surface, and is formed on any of the plurality of insulating base layers; With The mounting electrode has the first insulating base layer so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer. And the second insulating base material layer, The surface roughness of the first surface is greater than the surface roughness of the second surface, The first insulating base material layer has a base material layer non-forming portion that exposes a part of the first surface.
  • the second surface of the mounting electrode is conductive.
  • the contact area of the mounting electrode with respect to the conductive bonding material is increased as compared with the case where the bonding electrode is bonded to the mounting substrate or the like. Therefore, with this configuration, the conductive bonding material and the mounting electrode can be bonded with high bonding strength, and peeling of the multilayer substrate from the mounting substrate or the like after mounting can be suppressed. Also, with this configuration, the conductor loss of the mounting electrode can be reduced as compared with the case where the surface roughness of both the first surface and the second surface of the mounting electrode is large.
  • a said 1st insulating base material layer and a said 2nd insulating base material layer consist of the same resin material.
  • the mounting electrode does not reach the outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers.
  • the mounting electrode reaches the surface of the multilayer body (when it is exposed on the surface of the multilayer body)
  • the mounting electrode is easily peeled from the multilayer substrate by applying an external force to the exposed portion of the mounting electrode.
  • the mounting electrode since the mounting electrode is not exposed from the outer edge (surface) of the mounting surface of the laminate, it is possible to suppress the peeling of the mounting electrode from the multilayer substrate due to the application of external force. Also, with this configuration, it is possible to prevent peeling of the mounting electrode from the laminate due to stress applied to the end portion of the mounting electrode when separating the individual pieces from the collective substrate.
  • the first insulating base layer covers more than half of the outer periphery of the first surface.
  • the mounting electrode is disposed in the vicinity of an outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers, and the base layer non-forming portion is the plurality of base layers. It is preferable to reach the outer edge of the mounting surface when viewed from the stacking direction of the insulating base layer.
  • the electronic device of the present invention The multilayer substrate according to any one of (1) to (5) above; A mounting board; With The first surface of the mounting electrode is bonded to the mounting substrate through a conductive bonding material.
  • the conductive bonding material and the mounting electrode can be bonded with high bonding strength, and an electronic device in which peeling of the multilayer substrate from the mounting substrate after mounting can be realized.
  • the electronic device of the present invention The multilayer substrate according to the above (4) or (5); A mounting board; With The first surface of the mounting electrode is bonded to the mounting substrate by forming a solder fillet.
  • the method for producing the multilayer substrate of the present invention comprises: A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer; A mounting electrode facing the first surface and the first surface, having a second surface having a smaller surface roughness than the first surface, and formed on any of the plurality of insulating base layers; A method for producing a multilayer substrate comprising: Forming the mounting electrode such that the first surface is in contact with the surface of the first insulating base layer; After the electrode forming step, the plurality of insulating base layers are formed so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer.
  • the laminated body is formed by heating and pressurizing the plurality of laminated insulating base material layers, and the mounting electrode is embedded in the laminated body.
  • the layered body forming step the layered body is removed from the mounting surface side, and a base material layer non-forming portion that exposes a part of the first surface is formed on the first insulating base material layer. Process, It is characterized by providing.
  • the mounting substrate is mounted on the mounting substrate or the like. It is possible to realize a multi-layer substrate that can ensure sufficient bonding strength to the above.
  • FIG. 1 is a perspective view of a multilayer substrate 101 according to the first embodiment.
  • 2A is an AA cross-sectional view in FIG. 1, and
  • FIG. 2B is an exploded cross-sectional view of the multilayer substrate 101.
  • FIG. 3 is a bottom view of the multilayer substrate 101.
  • FIG. 4 is a cross-sectional view illustrating a main part of the electronic apparatus 301 according to the first embodiment.
  • FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps of the multilayer substrate 101.
  • FIG. 6 is a perspective view of the multilayer substrate 102 according to the second embodiment.
  • 7A is a cross-sectional view taken along the line BB in FIG. 6, and
  • FIG. 7B is a bottom view of the multilayer substrate 102.
  • FIG. 8 is a cross-sectional view illustrating a main part of the electronic device 302 according to the second embodiment.
  • FIG. 1 is a perspective view of a multilayer substrate 101 according to the first embodiment.
  • 2A is an AA cross-sectional view in FIG. 1
  • FIG. 2B is an exploded cross-sectional view of the multilayer substrate 101.
  • FIG. 3 is a bottom view of the multilayer substrate 101. 2A and 2B, the thickness of each insulating base material layer and the surface roughness of the mounting electrode are exaggerated. The same applies to the cross-sectional views shown below. Further, in FIG. 3, in order to make the structure easy to understand, a portion exposed from the stacked body in the first surface of the mounting electrode is shown by a dot pattern.
  • the multilayer substrate 101 includes a laminated body 10A formed by laminating a plurality of insulating base layers 11, 12, 13, 14, and 15, mounting electrodes P1 and P2, a plurality of conductors 21, 22, 23, 24, and 25, and A plurality of interlayer connection conductors V1, V2, etc. are provided.
  • the laminated body 10A is a substantially rectangular parallelepiped made of a thermoplastic resin whose longitudinal direction coincides with the X-axis direction, and has a first main surface VS1 and a second main surface VS2 facing each other.
  • the laminated body 10A is formed by laminating a plurality of insulating base material layers 11, 12, 13, 14, and 15 in this order.
  • the plurality of insulating base material layers 11, 12, 13, 14, and 15 are thermoplastic resin flat plates each having a rectangular planar outer shape.
  • the insulating base layers 11, 12, 13, 14, 15 are resin sheets whose main material is, for example, liquid crystal polymer (LCP) or polyether ether ketone (PEEK).
  • the first main surface VS1 of the stacked body 10A corresponds to the “mounting surface” in the present invention.
  • the insulating base material layer 11 corresponds to the “first insulating base material layer” in the present invention
  • the insulating base material layers 12, 13, 14, and 15 are the “second insulating base material layer” in the present invention. Is equivalent to.
  • the mounting electrodes P1 and P2 are rectangular conductors formed on any of the plurality of insulating base layers 11, 12, 13, 14, and 15, and have a first surface S1 and a second surface facing each other.
  • the mounting electrodes P1 and P2 are conductor patterns such as Cu foil, for example.
  • the surface roughness (Ra1) of the first surfaces S1A and S1B of the mounting electrodes P1 and P2 is larger than the surface roughness (Ra2) of the second surfaces S2A and S2B (Ra1> Ra2).
  • the surfaces of the first surfaces S1A and S1B of the mounting electrode P1 are roughened by, for example, a sand blaster method, a plasma method, a plating method, an etching method, or the like.
  • the surface roughness of the first surfaces S1A and S1B is 0.5 ⁇ m, for example, and the surface roughness of the second surfaces S2A and S2B is 0.2 ⁇ m, for example.
  • the standard (arithmetic average roughness) defined in [JIS B 0601-2001] is adopted.
  • the mounting electrodes P1 and P2 have the first surfaces S1A and S1B facing the first insulating base layer (insulating base layer 11), and the second surfaces S2A and S2B have the second insulating base layer (insulating). It is sandwiched between the first insulating base layer and the second insulating base layer so as to face the base layer 12).
  • the first insulating base material layer has rectangular base material layer non-forming portions NFP1 and NFP2 that expose a part of the first surfaces S1A and S1B.
  • the first insulating base material layer covers the entire outer periphery of the first surfaces S1A and S1B, and the center of the first surfaces S1A and S1B. The part is exposed from the laminated body 10A as shown in FIG.
  • the mounting electrodes P1 and P2 are viewed from the stacking direction (Z-axis direction) of the plurality of insulating base material layers 11, 12, 13, 14, and 15, and the first main surface ( It is arranged near the outer edge of the mounting surface.
  • the mounting electrode P1 is disposed in the vicinity of the first side of the mounting surface (the left side of the first main surface of the stacked body 10A in FIG. 3) as viewed from the Z-axis direction.
  • the mounting electrode P2 is disposed in the vicinity of the second side of the mounting surface (the right side of the first main surface of the stacked body 10A in FIG. 3) as viewed from the Z-axis direction.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
  • the plurality of conductors 21, 22, 23, 24, and 25 and the plurality of interlayer connection conductors V1 and V2 are conductors formed in the multilayer body 10A.
  • the conductor 21 is a conductor pattern formed on the surface of the insulating base material layer 12.
  • the conductors 22 and 23 are conductor patterns formed on the surface of the insulating base material layer 13.
  • the conductors 24 and 25 are conductor patterns formed on the surface of the insulating base material layer 14.
  • the conductor 21 and the conductor 22 are connected to each other via an interlayer connection conductor V1 formed on the insulating base material layer 13.
  • the conductor 23 and the conductor 24 are connected to each other through an interlayer connection conductor V2 formed on the insulating base layer 14.
  • the conductors 21, 22, 23, 24, and 25 are conductor patterns such as Cu foil, for example.
  • FIG. 4 is a cross-sectional view illustrating a main part of the electronic apparatus 301 according to the first embodiment.
  • the electronic device 301 includes a multilayer substrate 101, a mounting substrate 201, and the like. As shown in FIG. 4, the multilayer substrate 101 is mounted on the mounting substrate 201.
  • the mounting board 201 is, for example, a printed wiring board.
  • Conductors 41 and 42 are formed on the main surface of the mounting substrate 201.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the conductors 41 and 42 of the mounting substrate 201 via the conductive bonding material 1, respectively.
  • the conductive bonding material 1 is, for example, solder.
  • the multilayer substrate 101 according to this embodiment has the following effects.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the mounting substrate or the like via the conductive bonding material 1, and the surface roughness (Ra1) of the first surfaces S1A and S1B Is larger than the surface roughness (Ra2) of the second surfaces S2A and S2B (Ra1> Ra2). Therefore, compared with the case where the second surfaces S2A and S2B of the mounting electrode P2 are bonded to the mounting substrate or the like via the conductive bonding material 1, the contact area of the mounting electrodes P1 and P2 with respect to the conductive bonding material 1 is increased.
  • the conductive bonding material 1 and the mounting electrodes P1 and P2 can be bonded with high bonding strength, and peeling of the multilayer substrate 101 from the mounting substrate or the like after mounting can be suppressed.
  • the conductor loss of the mounting electrodes P1 and P2 can be reduced as compared with the case where the surface roughness of the first surfaces S1A and S1B and the second surfaces S2A and S2B of the mounting electrodes P1 and P2 is large.
  • FIGS. 2A and 3 In the multilayer substrate 101, as shown in FIGS. 2A and 3, a part of the mounting electrodes P1 and P2 (outer edge portions of the mounting electrodes P1 and P2 in FIG. It is sandwiched between the material layer (insulating base material layer 11) and the second insulating base material layer (insulating base material layer 12). Therefore, compared with the case where mounting electrodes P1 and P2 are formed on the surface of stacked body 10A, mounting electrodes P1 and P2 can be made difficult to peel from stacked body 10A.
  • the first insulating base layer (insulating base layer 11) and the second insulating base layer (insulating base layer 12) are made of the same resin material. With this configuration, there is no physical property difference between the first insulating base material layer and the second insulating base material layer sandwiching part of the mounting electrodes P1 and P2, and the first insulating base material layer and the second insulating base material layer The bonding strength between the two increases. Therefore, peeling of the mounting electrodes P1 and P2 from the multilayer substrate is suppressed.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface VS1 (mounting surface) when viewed from the Z-axis direction.
  • an external force is applied to the exposed portions of the mounting electrodes P1 and P2, thereby causing the mounting electrodes P1 and P2 to be exposed.
  • P2 becomes easy to peel from the multilayer substrate.
  • this configuration since the mounting electrodes P1 and P2 are not exposed from the outer edge (surface) of the mounting surface of the multilayer body 10A, peeling of the mounting electrodes P1 and P2 from the multilayer substrate due to an external force can be suppressed.
  • this configuration eliminates the need to separate the mounting electrodes P1 and P2 when separating individual pieces (multilayer substrates) from the collective substrate (described in detail later). Therefore, it is possible to prevent peeling of the mounting electrodes P1 and P2 from the stacked body 10A due to stress applied to the end portions of the mounting electrodes P1 and P2 during manufacturing.
  • the first insulating base layer (insulating base layer 11) covers the entire outer periphery of the first surfaces S1A and S1B. With this configuration, it is possible to make it difficult to peel the mounting electrode from the multilayer substrate (laminated body) as compared with the case where the first insulating base material layer covers a part of the outer periphery of the first surfaces S1A and S1B of the mounting electrodes P1 and P2.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 of the multilayer substrate 101 are bonded to the mounting substrate 201 via the conductive bonding material 1.
  • the conductive bonding material 1 and the mounting electrodes P1 and P2 can be bonded with high bonding strength, and an electronic device in which peeling of the multilayer substrate from the mounting substrate 201 or the like can be realized after mounting.
  • FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps of the multilayer substrate 101.
  • FIG. 5 for the convenience of explanation, the manufacturing process using one chip (individual piece) will be described. However, the actual manufacturing process of the diaphragm is performed in a collective substrate state.
  • insulating base material layers 11, 12, 13, 14, and 15 are prepared.
  • the insulating base layers 11, 12, 13, 14, and 15 are thermoplastic resin sheets such as liquid crystal polymer (LCP) or polyether ether ketone (PEEK).
  • mounting electrodes P1 and P2 having first surfaces S1A and S1B and second surfaces S2A and S2B facing each other are formed on the insulating base layer 11 (first insulating base layer).
  • a metal foil for example, Cu foil
  • the metal foil is patterned by photolithography to form mounting electrodes P1 and P2.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are roughened.
  • the first surfaces S1A and S1B are roughened by, for example, a sand blaster method, a plasma method, a plating method, an etching method, or the like.
  • This step of forming the mounting electrodes P1, P2 so that the first surfaces S1A, S1B are in contact with the surface of the first insulating base layer (insulating base layer 11) is an example of the “electrode forming step” in the present invention. is there.
  • conductors 21, 22, 23, 24, 25, etc. are respectively formed on the plurality of insulating base material layers 12, 13, 14 (second insulating base material layers).
  • a metal foil for example, Cu foil
  • the metal foil is laminated on one side main surface of the insulating base material layers 12, 13, and 14 in the aggregated substrate state, and the metal foil is patterned by photolithography, whereby the conductor 21 , 22, 23, 24, 25, and the like.
  • one surface of the conductors 21, 22, 23, 24, 25 in contact with the insulating base material layers 12, 13, 14 is the mounting electrode P1 described above.
  • P2 are roughened in the same manner as the first surfaces S1A and S1B.
  • interlayer connection conductors V1 and V2 are formed on the plurality of insulating base material layers 13 and 14, respectively.
  • Interlayer connection conductors V1 and V2 are made of a conductive paste containing one or more of Cu, Ag, Sn, Ni, Mo, etc. or an alloy thereof after providing through holes in insulating base layers 13 and 14 with a laser or the like. It is provided by being disposed and cured (solidified) by subsequent heating and pressing. Therefore, the interlayer connection conductors V1 and V2 are made of a material having a melting point (melting temperature) lower than the temperature at the time of subsequent heating and pressurization.
  • the insulating base layers 11, 12, 13, 14, and 15 are laminated in this order.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are opposed to the first insulating base layer (insulating base layer 11), and the second surfaces S2A and S2B are the second insulating base layer (insulating).
  • a plurality of insulating base layers 11, 12, 13, 14, and 15 are laminated so that the second surfaces S2A and S2B face the base layer 12).
  • a plurality of insulating base materials are provided such that the first surfaces S1A and S1B face the first insulating base material layer and the second surfaces S2A and S2B face the second insulating base material layer.
  • This step of laminating the layers 11, 12, 13, 14, and 15 is an example of the “lamination step” in the present invention.
  • the stacked body 10AP is configured. At this time, the mounting electrodes P1 and P2 are embedded in the stacked body 10AP.
  • the laminated insulating base material layers 11, 12, 13, 14, and 15 are heated and pressurized to form the laminated body 10AP, and the mounting electrodes P1 and P2 are disposed inside the laminated body 10AP.
  • This step of embedding in the substrate is an example of the “laminated body forming step” in the present invention.
  • the laminated body 10AP is removed, and the first insulating base material layer (insulating base material layer 11) is exposed to a part of the first surfaces S1A and S1B.
  • the material layer non-formation parts NFP1 and NFP2 are formed.
  • the first main surface VS1 of the stacked body 10AP is formed by a laser beam LR that is irradiated toward the stacking direction (Z-axis direction).
  • the laser beam LR is blocked by the mounting electrodes P1 and P2 embedded in the stacked body 10AP. Therefore, by using this manufacturing method, it is possible to easily form the base material layer non-forming portions NFP1, NFP2 that expose a part of the first surfaces S1A, S1B.
  • the layered body 10AP is removed from the mounting surface side, and the base material from which the first surfaces S1A and S1B are partially exposed to the first insulating base material layer (insulating base material layer 11).
  • This step of forming the layer non-forming portions NFP1 and NFP2 is an example of the “removal step” in the present invention.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface VS1 (mounting surface) when viewed from the Z-axis direction. Therefore, when separating the individual pieces (multilayer substrate) from the collective substrate, it is not necessary to separate the mounting electrodes P1 and P2 into individual pieces. Therefore, it is possible to prevent the mounting electrodes P1 and P2 from being peeled off from the stacked body 10A during manufacturing.
  • the plurality of insulating base material layers 11, 12, 13, 14, and 15 forming the laminate are made of a thermoplastic resin. According to the manufacturing method described above, since the laminated body 10A can be easily formed by collectively pressing the plurality of laminated insulating base material layers 11, 12, 13, 14, and 15, the man-hours for the manufacturing process of the insulating base material are reduced. The cost can be kept low.
  • Second Embodiment the example of the multilayer substrate from which the structure of a base material layer non-formation part differs is shown.
  • FIG. 6 is a perspective view of the multilayer substrate 102 according to the second embodiment.
  • 7A is a cross-sectional view taken along the line BB in FIG. 6, and
  • FIG. 7B is a bottom view of the multilayer substrate 102.
  • a portion of the first surface of the mounting electrode that is exposed from the stacked body is indicated by a dot pattern.
  • the multilayer substrate 102 includes a laminated body 10B formed by laminating a plurality of insulating base layers 11, 12, 13, 14, and 15, mounting electrodes P1 and P2, a plurality of conductors 21, 22, 23, 24, and 25, and A plurality of interlayer connection conductors V1, V2, etc. are provided.
  • the multilayer substrate 102 is different from the multilayer substrate 101 according to the first embodiment in the shapes of the base material layer non-forming portions NFP1 and NFP2. Other configurations are substantially the same as those of the multilayer substrate 101.
  • the base material layer non-forming portions NFP1, NFP2 reach the outer edge of the first main surface (mounting surface) as viewed from the Z-axis direction (the base material layer non-forming portion in FIG. 7B). (See the left side of the forming part NFP1 and the right side of the base material layer non-forming part NFP2).
  • the first insulating base material layer (see the insulating base material layer 11 in FIG. 7A) is the outer periphery of the first surface (S1A, S1B). Covers more than half. Specifically, the first insulating base layer covers about 3/4 of the outer periphery of the first surface (S1A) (the upper side, the right side, and the lower side of the mounting electrode P1 in FIG. 7B). In addition, the first insulating base layer covers about 3/4 of the outer periphery of the first surface (S1B) (the upper side, the left side, and the lower side of the mounting electrode P2 in FIG. 7B).
  • FIG. 8 is a cross-sectional view illustrating a main part of the electronic device 302 according to the second embodiment.
  • the electronic device 302 includes a multilayer substrate 102, a mounting substrate 201, and the like. As shown in FIG. 8, the multilayer substrate 102 is mounted on the mounting substrate 201.
  • the mounting substrate 201 is the same as that described in the first embodiment.
  • the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the conductors 41 and 42 of the mounting substrate 201 through the conductive bonding material 1, respectively. As shown in FIG. 8, the first surfaces S1A and S1B are bonded to the mounting substrate 201 by forming solder fillets.
  • the multilayer substrate 102 according to the present embodiment has the following effects in addition to the effects described in the first embodiment.
  • the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
  • the base material layer non-forming portions NFP1, NFP2 reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
  • the example of the multilayer substrate in which the first insulating base material layer covers about 3/4 of the outer periphery of the first surface (S1A, S1B) is shown, but the present invention is limited to this configuration. is not. If the first insulating base layer (insulating base layer 11) covers more than half of the outer periphery of the first surface (S1A, S1B), it is difficult to peel the mounting electrodes P1, P2 from the multilayer substrate (laminated body). The effect
  • the laminated body 10A, 10B showed the example which is a substantially rectangular parallelepiped shape, it is not limited to this structure.
  • the planar shape of the laminate can be changed as appropriate within the range where the functions and effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse, an L shape, a crank shape, a T shape, a Y shape, or the like.
  • the some insulating base material layers 11, 12, 13, 14, and 15 which form a laminated body consist of a thermoplastic resin is not limited to this structure.
  • the plurality of insulating base layers 11, 12, 13, 14, and 15 may be thermosetting resins.
  • the insulating base material layers 11, 12, 13, 14, and 15 are thermoplastic resins, the insulating base material can be easily formed as described above, thereby reducing the number of steps in the manufacturing process of the multilayer substrate. Cost can be kept low.
  • the multilayer substrate provided with the laminated body formed by laminating the five insulating base material layers 11, 12, 13, 14, and 15 has been described.
  • the present invention is not limited to this configuration. It is not something.
  • the number of insulating base material layers forming the laminate can be changed as appropriate within the range where the functions and effects of the present invention are exhibited.
  • one first insulating base material layer (insulating base material layer 11) and four second insulating base material layers (insulating base material layers 12, 13, 14, 15) are laminated.
  • the number of the first insulating base layers and the number of the second insulating base layers are not limited thereto.
  • the number of the first insulating base material layers and the number of the second insulating base material layers can be appropriately changed within a range where the functions and effects of the present invention are exhibited.
  • the number of first insulating base layers may be two or more, for example.
  • the number of the second insulating base layers may be one or two or more.
  • the present invention is not limited to this configuration.
  • the shape of the mounting electrode can be changed as appropriate within the scope of the operation and effect of the present invention.
  • the mounting electrode may be polygonal, circular, elliptical, L-shaped, crank-shaped, T-shaped, Y-shaped, or the like.
  • the number of mounting electrodes can be appropriately changed according to a circuit formed on the multilayer substrate.
  • the 1st insulating base material layer showed the example which has rectangular base material layer non-formation part NFP1, NFP2, it is not limited to this structure.
  • the shape of the base material layer non-forming part can be appropriately changed within the range where the functions and effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse or the like.
  • the number of base material layer non-formation parts is not limited to two, and may be one or three or more.
  • stacking several insulating base material layers 11, 12, 13, 14, and 15 protection of a solder resist film, a coverlay film, etc. was shown.
  • the layer may be formed on the first main surface VS1 or the second main surface VS2 of the stacked body.
  • the circuit formed on the multilayer substrate can be freely configured as long as the operations and effects of the present invention are achieved.
  • a transmission line such as a stripline structure, a microstripline structure, or a coplanar line may be formed on the multilayer substrate, and for example, a coil or a capacitor formed of a conductor pattern may be formed.
  • chip components such as chip inductors and chip capacitors may be mounted on the multilayer substrate.

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Abstract

A multi-layer substrate (101) is provided with a laminate (10A) formed by layering a plurality of insulating substrate layers (11, 12, 13, 14, 15), and mounting electrodes (P1, P2) having mutually opposed first surfaces (S1A, S1B) and second surfaces (S2A, S2B). The mounting electrodes (P1, P2) are interposed between a first insulating substrate layer (insulating substrate layer (11)) and a second insulating substrate layer (insulating substrate layer (12)) such that the first surface (S1A) faces the first insulating substrate layer and such that the second surfaces (S2A, S2B) face the second insulating substrate layer. The surface roughness (Ra1) of the first surfaces (S1A, S1B) is greater than the surface roughness (Ra2) of the second surfaces (S2A, S2B) (Ra1 > Ra2). The first insulating substrate layer (insulating substrate layer (11)) has substrate layer non-formation parts (NFP1, NFP2) where parts of the first surfaces (S1A, S1B) are exposed.

Description

多層基板、電子機器および多層基板の製造方法Multilayer substrate, electronic device, and method for manufacturing multilayer substrate
　本発明は、多層基板に関し、特に複数の絶縁基材層を積層して形成される積層体と、絶縁基材層に形成される導体パターンと、を備える多層基板と、その多層基板を備える電子機器、さらには上記多層基板の製造方法に関する。 The present invention relates to a multilayer substrate, and in particular, a multilayer substrate formed by laminating a plurality of insulating base layers, and a conductor pattern formed on the insulating base layer, and an electronic including the multilayer substrate The present invention also relates to a device and a method for manufacturing the multilayer substrate.
　従来、銅箔等の導体パターンを表面に貼り付けられた複数の絶縁基材層を積層して、積層体を形成する方法が知られている。 Conventionally, a method of forming a laminated body by laminating a plurality of insulating base layers having a conductive pattern such as a copper foil attached on the surface is known.
　例えば、特許文献１には、導体パターンが表面に貼り付けられた複数の絶縁基材層を積層する構造において、絶縁基材層に貼り付けられる導体パターンの一方主面側の表面粗さを、他方主面側の表面粗さよりも大きくした多層基板が開示されている。この構成により、絶縁基材層に対する導体パターンの接合強度を高めることができる。 For example, in Patent Document 1, in a structure in which a plurality of insulating base material layers having a conductor pattern attached to the surface is laminated, the surface roughness on one main surface side of the conductor pattern attached to the insulating base material layer is On the other hand, a multilayer substrate having a surface roughness larger than that of the main surface is disclosed. With this configuration, the bonding strength of the conductor pattern to the insulating base layer can be increased.
国際公開第２０１４／１１５４３３号International Publication No. 2014/115433
　しかし、特許文献１に示される構成では、多層基板を実装基板等に実装するための実装電極の実装面が、一方主面よりも相対的に表面粗さの小さな導体パターンの他方主面となる。そのため、導電性接合材に対する実装電極の接触面積が小さく、高い接合強度が得られず、実装後に実装基板等から多層基板が剥離する虞がある。 However, in the configuration shown in Patent Document 1, the mounting surface of the mounting electrode for mounting the multilayer substrate on the mounting substrate or the like is the other main surface of the conductor pattern having a relatively smaller surface roughness than the one main surface. . Therefore, the contact area of the mounting electrode with respect to the conductive bonding material is small, high bonding strength cannot be obtained, and the multilayer substrate may be peeled off from the mounting substrate or the like after mounting.
　本発明の目的は、複数の絶縁基材層を積層して形成される積層体と、絶縁基材層に形成される実装電極とを備える構成において、実装基板等に実装した際に、実装基板等に対する十分な接合強度を確保できる多層基板を提供することにある。 An object of the present invention is to provide a mounting board when mounted on a mounting board or the like in a configuration including a laminate formed by laminating a plurality of insulating base layers and a mounting electrode formed on the insulating base layer. It is an object of the present invention to provide a multilayer substrate that can ensure a sufficient bonding strength with respect to the above.
（１）本発明の多層基板は、
　実装面を有し、第１絶縁基材層および第２絶縁基材層を含む複数の絶縁基材層を積層して形成される積層体と、
　第１面および前記第１面に対向する第２面を有し、前記複数の絶縁基材層のいずれかに形成される実装電極と、
　を備え、
　前記実装電極は、前記第１面が前記第１絶縁基材層と対向するように、且つ、前記第２面が前記第２絶縁基材層と対向するように、前記第１絶縁基材層と前記第２絶縁基材層との間に挟まれ、
　前記第１面の表面粗さは、前記第２面の表面粗さよりも大きく、
　前記第１絶縁基材層は、前記第１面の一部を露出させる基材層非形成部を有することを特徴とする。 (1) The multilayer substrate of the present invention is
A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer;
A mounting electrode that has a first surface and a second surface opposite to the first surface, and is formed on any of the plurality of insulating base layers;
With
The mounting electrode has the first insulating base layer so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer. And the second insulating base material layer,
The surface roughness of the first surface is greater than the surface roughness of the second surface,
The first insulating base material layer has a base material layer non-forming portion that exposes a part of the first surface.
　この構成では、導電性接合材を介して実装基板等に接合される実装電極の第１面の表面粗さが、第２面の表面粗さよりも大きいため、実装電極の第２面が導電性接合材を介して実装基板等に接合される場合に比べて、導電性接合材に対する実装電極の接触面積が大きくなる。したがって、この構成により、導電性接合材と実装電極とを高い接合強度で接合でき、実装後において実装基板等からの多層基板の剥離を抑制できる。また、この構成により、実装電極の第１面および第２面の表面粗さをいずれも大きい場合に比べて、実装電極の導体損を低減できる。 In this configuration, since the surface roughness of the first surface of the mounting electrode bonded to the mounting substrate or the like via the conductive bonding material is larger than the surface roughness of the second surface, the second surface of the mounting electrode is conductive. The contact area of the mounting electrode with respect to the conductive bonding material is increased as compared with the case where the bonding electrode is bonded to the mounting substrate or the like. Therefore, with this configuration, the conductive bonding material and the mounting electrode can be bonded with high bonding strength, and peeling of the multilayer substrate from the mounting substrate or the like after mounting can be suppressed. Also, with this configuration, the conductor loss of the mounting electrode can be reduced as compared with the case where the surface roughness of both the first surface and the second surface of the mounting electrode is large.
　また、この構成では、実装電極の一部が、第１絶縁基材層と第２絶縁基材層とで挟まれる。そのため、実装電極が積層体の表面に形成されている場合に比べ、積層体から実装電極を剥離し難くできる。 In this configuration, a part of the mounting electrode is sandwiched between the first insulating base material layer and the second insulating base material layer. Therefore, it is possible to make it difficult to peel the mounting electrode from the stacked body as compared with the case where the mounting electrode is formed on the surface of the stacked body.
（２）上記（１）において、前記第１絶縁基材層および前記第２絶縁基材層は、同じ樹脂材料からなることが好ましい。この構成により、実装電極の一部を挟む第１絶縁基材層と第２絶縁基材層との間の物性差が無くなり、第１絶縁基材層と第２絶縁基材層との間の接合強度が高まる。そのため、多層基板からの実装電極の剥離が抑制される。 (2) In said (1), it is preferable that a said 1st insulating base material layer and a said 2nd insulating base material layer consist of the same resin material. With this configuration, there is no physical property difference between the first insulating base material layer and the second insulating base material layer sandwiching a part of the mounting electrode, and there is no difference between the first insulating base material layer and the second insulating base material layer. Bonding strength is increased. Therefore, peeling of the mounting electrode from the multilayer substrate is suppressed.
（３）上記（１）または（２）において、前記実装電極は、前記複数の絶縁基材層の積層方向から視て、前記実装面の外縁に達していないことが好ましい。実装電極が積層体の表面にまで達している場合（積層体の表面に露出している場合）、実装電極が露出した部分に外力が加わることで、実装電極が多層基板から剥離しやすくなる。一方、この構成では、実装電極が積層体の実装面の外縁（表面）から露出していないため、外力が加わることによる多層基板からの実装電極の剥離を抑制できる。また、この構成により、集合基板から個片を分離する際に、実装電極の端部に応力が掛ることに起因した、積層体からの実装電極の剥離を防止できる。 (3) In the above (1) or (2), it is preferable that the mounting electrode does not reach the outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers. When the mounting electrode reaches the surface of the multilayer body (when it is exposed on the surface of the multilayer body), the mounting electrode is easily peeled from the multilayer substrate by applying an external force to the exposed portion of the mounting electrode. On the other hand, in this configuration, since the mounting electrode is not exposed from the outer edge (surface) of the mounting surface of the laminate, it is possible to suppress the peeling of the mounting electrode from the multilayer substrate due to the application of external force. Also, with this configuration, it is possible to prevent peeling of the mounting electrode from the laminate due to stress applied to the end portion of the mounting electrode when separating the individual pieces from the collective substrate.
（４）上記（１）から（３）のいずれかにおいて、前記第１絶縁基材層は、前記第１面の外周の半分以上を覆うことが好ましい。この構成により、絶縁基材層が実装電極の第１面の外周の半分未満を覆う場合に比べて、多層基板から実装電極を剥離し難くできる。 (4) In any one of the above (1) to (3), it is preferable that the first insulating base layer covers more than half of the outer periphery of the first surface. With this configuration, it is possible to make it difficult to peel the mounting electrode from the multilayer substrate as compared with the case where the insulating base layer covers less than half of the outer periphery of the first surface of the mounting electrode.
（５）上記（４）において、前記実装電極は、前記複数の絶縁基材層の積層方向から視て、前記実装面の外縁近傍に配置され、前記基材層非形成部は、前記複数の絶縁基材層の積層方向から視て、前記実装面の前記外縁に達することが好ましい。この構成により、実装面の外縁にまで達する基材層非形成部を利用して、多層基板の実装面積を大きくすることなく、はんだフィレットを形成できる。そのため、実装基板等に対する接合信頼性を高め、高密度配置が可能な多層基板を実現できる。 (5) In the above (4), the mounting electrode is disposed in the vicinity of an outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers, and the base layer non-forming portion is the plurality of base layers. It is preferable to reach the outer edge of the mounting surface when viewed from the stacking direction of the insulating base layer. With this configuration, it is possible to form a solder fillet without increasing the mounting area of the multilayer substrate by utilizing the base material layer non-forming portion reaching the outer edge of the mounting surface. Therefore, it is possible to realize a multilayer substrate capable of improving the bonding reliability with respect to the mounting substrate and the like and capable of high density arrangement.
（６）本発明の電子機器は、
　上記（１）から（５）のいずれかに記載の多層基板と、
　実装基板と、
　を備え、
　前記実装電極の前記第１面は、導電性接合材を介して前記実装基板に接合されることを特徴とする。 (6) The electronic device of the present invention
The multilayer substrate according to any one of (1) to (5) above;
A mounting board;
With
The first surface of the mounting electrode is bonded to the mounting substrate through a conductive bonding material.
　この構成により、導電性接合材と実装電極とを高い接合強度で接合でき、実装後において実装基板等から多層基板の剥離を抑制した電子機器を実現できる。 With this configuration, the conductive bonding material and the mounting electrode can be bonded with high bonding strength, and an electronic device in which peeling of the multilayer substrate from the mounting substrate after mounting can be realized.
（７）本発明の電子機器は、
　上記（４）または（５）に記載の多層基板と、
　実装基板と、
　を備え、
　前記実装電極の前記第１面は、はんだフィレットを形成して前記実装基板に接合されていることを特徴とする。 (7) The electronic device of the present invention
The multilayer substrate according to the above (4) or (5);
A mounting board;
With
The first surface of the mounting electrode is bonded to the mounting substrate by forming a solder fillet.
　この構成により、多層基板の実装面積を大きくすることなく、実装基板等に対する多層基板の接合信頼性を高めた電子機器を実現できる。 With this configuration, it is possible to realize an electronic device with improved bonding reliability of the multilayer board to the mounting board or the like without increasing the mounting area of the multilayer board.
（８）本発明の多層基板の製造方法は、
　実装面を有し、第１絶縁基材層および第２絶縁基材層を含む複数の絶縁基材層を積層して形成される積層体と、
　第１面、および前記第１面に対向し、前記第１面よりも表面粗さが小さな第２面を有し、前記複数の絶縁基材層のいずれかに形成される実装電極と、
　を備える多層基板の製造方法であって、
　　前記第１絶縁基材層の表面に、前記第１面が接するように前記実装電極を形成する、電極形成工程と、
　　前記電極形成工程の後に、前記第１絶縁基材層に前記第１面が対向し、且つ、前記第２絶縁基材層に前記第２面が対向するように前記複数の絶縁基材層を積層する、積層工程と、
　前記積層工程の後に、積層した前記複数の絶縁基材層を加熱加圧して前記積層体を形成するとともに、前記実装電極を前記積層体の内部に埋設する、積層体形成工程と、
　前記積層体形成工程の後に、前記積層体を前記実装面側から除去し、前記第１絶縁基材層に、前記第１面の一部を露出させる基材層非形成部を形成する、除去工程と、
　を備えることを特徴とする。 (8) The method for producing the multilayer substrate of the present invention comprises:
A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer;
A mounting electrode facing the first surface and the first surface, having a second surface having a smaller surface roughness than the first surface, and formed on any of the plurality of insulating base layers;
A method for producing a multilayer substrate comprising:
Forming the mounting electrode such that the first surface is in contact with the surface of the first insulating base layer;
After the electrode forming step, the plurality of insulating base layers are formed so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer. Laminating, laminating process,
After the laminating step, the laminated body is formed by heating and pressurizing the plurality of laminated insulating base material layers, and the mounting electrode is embedded in the laminated body.
After the layered body forming step, the layered body is removed from the mounting surface side, and a base material layer non-forming portion that exposes a part of the first surface is formed on the first insulating base material layer. Process,
It is characterized by providing.
　この製造方法により、複数の絶縁基材層を積層して形成される積層体と、絶縁基材層のいずれかに形成される実装電極とを備える構成において、実装基板等に実装した際に、実装基板等に対する十分な接合強度を確保できる多層基板を容易に製造できる。 In this configuration, in a configuration including a laminate formed by laminating a plurality of insulating base layers and a mounting electrode formed on any of the insulating base layers, when mounted on a mounting substrate or the like, A multilayer substrate that can ensure sufficient bonding strength to a mounting substrate or the like can be easily manufactured.
　本発明によれば、複数の絶縁基材層を積層して形成される積層体と、絶縁基材層に形成される実装電極とを備える構成において、実装基板等に実装した際に、実装基板等に対する十分な接合強度を確保できる多層基板を実現できる。 According to the present invention, in a configuration including a laminate formed by laminating a plurality of insulating base layers and a mounting electrode formed on the insulating base layer, the mounting substrate is mounted on the mounting substrate or the like. It is possible to realize a multi-layer substrate that can ensure sufficient bonding strength to the above.
図１は第１の実施形態に係る多層基板１０１の斜視図である。FIG. 1 is a perspective view of a multilayer substrate 101 according to the first embodiment. 図２（Ａ）は図１におけるＡ－Ａ断面図であり、図２（Ｂ）は多層基板１０１の分解断面図である。2A is an AA cross-sectional view in FIG. 1, and FIG. 2B is an exploded cross-sectional view of the multilayer substrate 101. 図３は、多層基板１０１の底面図である。FIG. 3 is a bottom view of the multilayer substrate 101. 図４は、第１の実施形態に係る電子機器３０１の主要部を示す断面図である。FIG. 4 is a cross-sectional view illustrating a main part of the electronic apparatus 301 according to the first embodiment. 図５は多層基板１０１の製造工程を順に示す断面図である。FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps of the multilayer substrate 101. 図６は、第２の実施形態に係る多層基板１０２の斜視図である。FIG. 6 is a perspective view of the multilayer substrate 102 according to the second embodiment. 図７（Ａ）は図６におけるＢ－Ｂ断面図であり、図７（Ｂ）は、多層基板１０２の底面図である。7A is a cross-sectional view taken along the line BB in FIG. 6, and FIG. 7B is a bottom view of the multilayer substrate 102. 図８は、第２の実施形態に係る電子機器３０２の主要部を示す断面図である。FIG. 8 is a cross-sectional view illustrating a main part of the electronic device 302 according to the second embodiment.
　以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付している。要点の説明または理解の容易性を考慮して、便宜上実施形態を分けて示すが、異なる実施形態で示した構成の部分的な置換または組み合わせが可能である。第２の実施形態以降では第１の実施形態と共通の事柄についての記述を省略し、異なる点についてのみ説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In each figure, the same reference numerals are assigned to the same portions. In consideration of ease of explanation or understanding of the main points, the embodiments are shown separately for convenience, but the components shown in different embodiments can be partially replaced or combined. In the second and subsequent embodiments, description of matters common to the first embodiment is omitted, and only different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.
　《第１の実施形態》
　図１は第１の実施形態に係る多層基板１０１の斜視図である。図２（Ａ）は図１におけるＡ－Ａ断面図であり、図２（Ｂ）は多層基板１０１の分解断面図である。図３は、多層基板１０１の底面図である。図２（Ａ）および図２（Ｂ）において、各絶縁基材層の厚み、および実装電極の表面粗さは誇張して図示している。このことは、以降に示す各断面図でも同様である。また、図３では、構造を分かりやすくするため、実装電極の第１面のうち、積層体から露出する部分をドットパターンで示している。 << First Embodiment >>
FIG. 1 is a perspective view of a multilayer substrate 101 according to the first embodiment. 2A is an AA cross-sectional view in FIG. 1, and FIG. 2B is an exploded cross-sectional view of the multilayer substrate 101. FIG. 3 is a bottom view of the multilayer substrate 101. 2A and 2B, the thickness of each insulating base material layer and the surface roughness of the mounting electrode are exaggerated. The same applies to the cross-sectional views shown below. Further, in FIG. 3, in order to make the structure easy to understand, a portion exposed from the stacked body in the first surface of the mounting electrode is shown by a dot pattern.
　多層基板１０１は、複数の絶縁基材層１１，１２，１３，１４，１５を積層して形成される積層体１０Ａ、実装電極Ｐ１，Ｐ２、複数の導体２１，２２，２３，２４，２５および複数の層間接続導体Ｖ１，Ｖ２等を備える。 The multilayer substrate 101 includes a laminated body 10A formed by laminating a plurality of insulating base layers 11, 12, 13, 14, and 15, mounting electrodes P1 and P2, a plurality of conductors 21, 22, 23, 24, and 25, and A plurality of interlayer connection conductors V1, V2, etc. are provided.
　積層体１０Ａは、長手方向がＸ軸方向に一致した熱可塑性樹脂製の略直方体であり、互いに対向する第１主面ＶＳ１および第２主面ＶＳ２を有する。積層体１０Ａは、複数の絶縁基材層１１，１２，１３，１４，１５の順に積層して形成される。複数の絶縁基材層１１，１２，１３，１４，１５は、それぞれ平面外形が矩形である熱可塑性樹脂の平板である。絶縁基材層１１，１２，１３，１４，１５は、例えば液晶ポリマー（ＬＣＰ）またはポリエーテルエーテルケトン（ＰＥＥＫ）を主材料とする樹脂シートである。 The laminated body 10A is a substantially rectangular parallelepiped made of a thermoplastic resin whose longitudinal direction coincides with the X-axis direction, and has a first main surface VS1 and a second main surface VS2 facing each other. The laminated body 10A is formed by laminating a plurality of insulating base material layers 11, 12, 13, 14, and 15 in this order. The plurality of insulating base material layers 11, 12, 13, 14, and 15 are thermoplastic resin flat plates each having a rectangular planar outer shape. The insulating base layers 11, 12, 13, 14, 15 are resin sheets whose main material is, for example, liquid crystal polymer (LCP) or polyether ether ketone (PEEK).
　なお、積層体１０Ａの第１主面ＶＳ１は、本発明における「実装面」に相当する。また、本実施形態では、絶縁基材層１１が本発明における「第１絶縁基材層」に相当し、絶縁基材層１２，１３，１４，１５が本発明における「第２絶縁基材層」に相当する。 The first main surface VS1 of the stacked body 10A corresponds to the “mounting surface” in the present invention. Moreover, in this embodiment, the insulating base material layer 11 corresponds to the “first insulating base material layer” in the present invention, and the insulating base material layers 12, 13, 14, and 15 are the “second insulating base material layer” in the present invention. Is equivalent to.
　実装電極Ｐ１，Ｐ２は、複数の絶縁基材層１１，１２，１３，１４，１５のいずれかに形成される矩形の導体であり、互いに対向する第１面Ｓ１および第２面を有する。実装電極Ｐ１，Ｐ２は、例えばＣｕ箔等の導体パターンである。 The mounting electrodes P1 and P2 are rectangular conductors formed on any of the plurality of insulating base layers 11, 12, 13, 14, and 15, and have a first surface S1 and a second surface facing each other. The mounting electrodes P1 and P2 are conductor patterns such as Cu foil, for example.
　実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂの表面粗さ（Ｒａ１）は、第２面Ｓ２Ａ，Ｓ２Ｂの表面粗さ（Ｒａ２）よりも大きい（Ｒａ１＞Ｒａ２）。実装電極Ｐ１の第１面Ｓ１Ａ，Ｓ１Ｂは、例えばサンドブラスタ法、プラズマ法、めっき法、エッチング法等によって、表面が粗面化されている。第１面Ｓ１Ａ，Ｓ１Ｂの表面粗さは例えば０．５μｍであり、第２面Ｓ２Ａ，Ｓ２Ｂの表面粗さは例えば０．２μｍである。表面粗さの算定は、［ＪＩＳ　Ｂ　０６０１－２００１］で定められた規格（算術平均粗さ）を採用する。 The surface roughness (Ra1) of the first surfaces S1A and S1B of the mounting electrodes P1 and P2 is larger than the surface roughness (Ra2) of the second surfaces S2A and S2B (Ra1> Ra2). The surfaces of the first surfaces S1A and S1B of the mounting electrode P1 are roughened by, for example, a sand blaster method, a plasma method, a plating method, an etching method, or the like. The surface roughness of the first surfaces S1A and S1B is 0.5 μm, for example, and the surface roughness of the second surfaces S2A and S2B is 0.2 μm, for example. For the calculation of the surface roughness, the standard (arithmetic average roughness) defined in [JIS B 0601-2001] is adopted.
　実装電極Ｐ１，Ｐ２は、第１面Ｓ１Ａ，Ｓ１Ｂが第１絶縁基材層（絶縁基材層１１）と対向するように、且つ、第２面Ｓ２Ａ，Ｓ２Ｂが第２絶縁基材層（絶縁基材層１２）と対向するように、第１絶縁基材層と第２絶縁基材層との間に挟まれている。図３に示すように、第１絶縁基材層は、第１面Ｓ１Ａ，Ｓ１Ｂの一部を露出させる矩形の基材層非形成部ＮＦＰ１，ＮＦＰ２を有する。 The mounting electrodes P1 and P2 have the first surfaces S1A and S1B facing the first insulating base layer (insulating base layer 11), and the second surfaces S2A and S2B have the second insulating base layer (insulating). It is sandwiched between the first insulating base layer and the second insulating base layer so as to face the base layer 12). As shown in FIG. 3, the first insulating base material layer has rectangular base material layer non-forming portions NFP1 and NFP2 that expose a part of the first surfaces S1A and S1B.
　本実施形態では、第１絶縁基材層（図２（Ａ）における絶縁基材層１１を参照）が、第１面Ｓ１Ａ，Ｓ１Ｂの外周全部を覆っており、第１面Ｓ１Ａ，Ｓ１Ｂの中央部は、図３に示すように、積層体１０Ａから露出している。 In the present embodiment, the first insulating base material layer (see the insulating base material layer 11 in FIG. 2A) covers the entire outer periphery of the first surfaces S1A and S1B, and the center of the first surfaces S1A and S1B. The part is exposed from the laminated body 10A as shown in FIG.
　また、本実施形態では、実装電極Ｐ１，Ｐ２が、複数の絶縁基材層１１，１２，１３，１４，１５の積層方向（Ｚ軸方向）から視て、積層体１０Ａの第１主面（実装面）の外縁近傍に配置されている。具体的には、実装電極Ｐ１が、Ｚ軸方向から視て、実装面の第１辺（図３における積層体１０Ａの第１主面の左辺）近傍に配置されている。また、実装電極Ｐ２は、Ｚ軸方向から視て、実装面の第２辺（図３における積層体１０Ａの第１主面の右辺）近傍に配置されている。さらに、本実施形態では、実装電極Ｐ１，Ｐ２は、Ｚ軸方向から視て、第１主面（実装面）の外縁に達していない。 In the present embodiment, the mounting electrodes P1 and P2 are viewed from the stacking direction (Z-axis direction) of the plurality of insulating base material layers 11, 12, 13, 14, and 15, and the first main surface ( It is arranged near the outer edge of the mounting surface. Specifically, the mounting electrode P1 is disposed in the vicinity of the first side of the mounting surface (the left side of the first main surface of the stacked body 10A in FIG. 3) as viewed from the Z-axis direction. Further, the mounting electrode P2 is disposed in the vicinity of the second side of the mounting surface (the right side of the first main surface of the stacked body 10A in FIG. 3) as viewed from the Z-axis direction. Further, in the present embodiment, the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction.
　複数の導体２１，２２，２３，２４，２５および複数の層間接続導体Ｖ１，Ｖ２は、積層体１０Ａに形成される導体である。具体的には、導体２１は、絶縁基材層１２の表面に形成される導体パターンである。導体２２，２３は、絶縁基材層１３の表面に形成される導体パターンである。導体２４，２５は、絶縁基材層１４の表面に形成される導体パターンである。導体２１および導体２２は、絶縁基材層１３に形成される層間接続導体Ｖ１を介して、互いに接続される。導体２３および導体２４は、絶縁基材層１４に形成される層間接続導体Ｖ２を介して、互いに接続される。導体２１，２２，２３，２４，２５は、例えばＣｕ箔等の導体パターンである。 The plurality of conductors 21, 22, 23, 24, and 25 and the plurality of interlayer connection conductors V1 and V2 are conductors formed in the multilayer body 10A. Specifically, the conductor 21 is a conductor pattern formed on the surface of the insulating base material layer 12. The conductors 22 and 23 are conductor patterns formed on the surface of the insulating base material layer 13. The conductors 24 and 25 are conductor patterns formed on the surface of the insulating base material layer 14. The conductor 21 and the conductor 22 are connected to each other via an interlayer connection conductor V1 formed on the insulating base material layer 13. The conductor 23 and the conductor 24 are connected to each other through an interlayer connection conductor V2 formed on the insulating base layer 14. The conductors 21, 22, 23, 24, and 25 are conductor patterns such as Cu foil, for example.
　次に、導電性接合材を用いて、多層基板１０１を実装基板に実装した状態について、図を参照して説明する。図４は、第１の実施形態に係る電子機器３０１の主要部を示す断面図である。 Next, a state where the multilayer substrate 101 is mounted on a mounting substrate using a conductive bonding material will be described with reference to the drawings. FIG. 4 is a cross-sectional view illustrating a main part of the electronic apparatus 301 according to the first embodiment.
　電子機器３０１は、多層基板１０１および実装基板２０１等を備える。図４に示すように、多層基板１０１は、実装基板２０１に実装される。実装基板２０１は例えばプリント配線基板である。 The electronic device 301 includes a multilayer substrate 101, a mounting substrate 201, and the like. As shown in FIG. 4, the multilayer substrate 101 is mounted on the mounting substrate 201. The mounting board 201 is, for example, a printed wiring board.
　実装基板２０１の主面には導体４１，４２が形成されている。実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂは、導電性接合材１を介して、実装基板２０１の導体４１，４２にそれぞれ接合される。導電性接合材１は例えばはんだ等である。 Conductors 41 and 42 are formed on the main surface of the mounting substrate 201. The first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the conductors 41 and 42 of the mounting substrate 201 via the conductive bonding material 1, respectively. The conductive bonding material 1 is, for example, solder.
　本実施形態に係る多層基板１０１によれば、次のような効果を奏する。 The multilayer substrate 101 according to this embodiment has the following effects.
（ａ）多層基板１０１は、実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂが、導電性接合材１を介して実装基板等に接合され、第１面Ｓ１Ａ，Ｓ１Ｂの表面粗さ（Ｒａ１）は第２面Ｓ２Ａ，Ｓ２Ｂの表面粗さ（Ｒａ２）よりも大きい（Ｒａ１＞Ｒａ２）。そのため、実装電極Ｐ２の第２面Ｓ２Ａ，Ｓ２Ｂが導電性接合材１を介して実装基板等に接合される場合に比べ、導電性接合材１に対する実装電極Ｐ１，Ｐ２の接触面積は大きくなる。したがって、この構成により、導電性接合材１と実装電極Ｐ１，Ｐ２とを高い接合強度で接合でき、実装後において実装基板等からの多層基板１０１の剥離を抑制できる。また、この構成により、実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂおよび第２面Ｓ２Ａ，Ｓ２Ｂの表面粗さをいずれも大きい場合に比べて、実装電極Ｐ１，Ｐ２の導体損を低減できる。 (A) In the multilayer substrate 101, the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the mounting substrate or the like via the conductive bonding material 1, and the surface roughness (Ra1) of the first surfaces S1A and S1B Is larger than the surface roughness (Ra2) of the second surfaces S2A and S2B (Ra1> Ra2). Therefore, compared with the case where the second surfaces S2A and S2B of the mounting electrode P2 are bonded to the mounting substrate or the like via the conductive bonding material 1, the contact area of the mounting electrodes P1 and P2 with respect to the conductive bonding material 1 is increased. Therefore, with this configuration, the conductive bonding material 1 and the mounting electrodes P1 and P2 can be bonded with high bonding strength, and peeling of the multilayer substrate 101 from the mounting substrate or the like after mounting can be suppressed. In addition, with this configuration, the conductor loss of the mounting electrodes P1 and P2 can be reduced as compared with the case where the surface roughness of the first surfaces S1A and S1B and the second surfaces S2A and S2B of the mounting electrodes P1 and P2 is large.
（ｂ）また、多層基板１０１では、図２（Ａ）および図３に示すように、実装電極Ｐ１，Ｐ２の一部（図３における実装電極Ｐ１，Ｐ２の外縁部分）が、第１絶縁基材層（絶縁基材層１１）と第２絶縁基材層（絶縁基材層１２）とで挟まれる。そのため、実装電極Ｐ１，Ｐ２が積層体１０Ａの表面に形成されている場合に比べ、積層体１０Ａから実装電極Ｐ１，Ｐ２を剥離し難くできる。 (B) In the multilayer substrate 101, as shown in FIGS. 2A and 3, a part of the mounting electrodes P1 and P2 (outer edge portions of the mounting electrodes P1 and P2 in FIG. It is sandwiched between the material layer (insulating base material layer 11) and the second insulating base material layer (insulating base material layer 12). Therefore, compared with the case where mounting electrodes P1 and P2 are formed on the surface of stacked body 10A, mounting electrodes P1 and P2 can be made difficult to peel from stacked body 10A.
（ｃ）多層基板１０１では、第１絶縁基材層（絶縁基材層１１）および第２絶縁基材層（絶縁基材層１２）が、同じ樹脂材料からなる。この構成により、実装電極Ｐ１，Ｐ２の一部を挟む第１絶縁基材層と第２絶縁基材層との間の物性差が無くなり、第１絶縁基材層と第２絶縁基材層との間の接合強度が高まる。そのため、多層基板からの実装電極Ｐ１，Ｐ２の剥離が抑制される。 (C) In the multilayer substrate 101, the first insulating base layer (insulating base layer 11) and the second insulating base layer (insulating base layer 12) are made of the same resin material. With this configuration, there is no physical property difference between the first insulating base material layer and the second insulating base material layer sandwiching part of the mounting electrodes P1 and P2, and the first insulating base material layer and the second insulating base material layer The bonding strength between the two increases. Therefore, peeling of the mounting electrodes P1 and P2 from the multilayer substrate is suppressed.
（ｄ）また、多層基板１０１では、実装電極Ｐ１，Ｐ２が、Ｚ軸方向から視て、第１主面ＶＳ１（実装面）の外縁に達していない。実装電極Ｐ１，Ｐ２が積層体１０Ａの表面にまで達している場合（積層体の表面に露出している場合）、実装電極Ｐ１，Ｐ２が露出した部分に外力が加わることで、実装電極Ｐ１，Ｐ２が多層基板から剥離しやすくなる。一方、この構成では、実装電極Ｐ１，Ｐ２が積層体１０Ａの実装面の外縁（表面）から露出していないため、外力が加わることによる多層基板からの実装電極Ｐ１，Ｐ２の剥離を抑制できる。また、この構成により、集合基板から個片（多層基板）を分離する際（後に詳述する）に、実装電極Ｐ１，Ｐ２ごとを分離する必要がない。そのため、製造時において、実装電極Ｐ１，Ｐ２の端部に応力が掛ることに起因した、積層体１０Ａからの実装電極Ｐ１，Ｐ２の剥離を防止できる。 (D) In the multilayer substrate 101, the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface VS1 (mounting surface) when viewed from the Z-axis direction. When the mounting electrodes P1 and P2 reach the surface of the multilayer body 10A (when exposed to the surface of the multilayer body), an external force is applied to the exposed portions of the mounting electrodes P1 and P2, thereby causing the mounting electrodes P1 and P2 to be exposed. P2 becomes easy to peel from the multilayer substrate. On the other hand, in this configuration, since the mounting electrodes P1 and P2 are not exposed from the outer edge (surface) of the mounting surface of the multilayer body 10A, peeling of the mounting electrodes P1 and P2 from the multilayer substrate due to an external force can be suppressed. In addition, this configuration eliminates the need to separate the mounting electrodes P1 and P2 when separating individual pieces (multilayer substrates) from the collective substrate (described in detail later). Therefore, it is possible to prevent peeling of the mounting electrodes P1 and P2 from the stacked body 10A due to stress applied to the end portions of the mounting electrodes P1 and P2 during manufacturing.
（ｅ）また、多層基板１０１では、第１絶縁基材層（絶縁基材層１１）が、第１面Ｓ１Ａ，Ｓ１Ｂの外周全部を覆っている。この構成により、第１絶縁基材層が実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂの外周の一部を覆う場合に比べて、多層基板（積層体）から実装電極を剥離し難くできる。 (E) In the multilayer substrate 101, the first insulating base layer (insulating base layer 11) covers the entire outer periphery of the first surfaces S1A and S1B. With this configuration, it is possible to make it difficult to peel the mounting electrode from the multilayer substrate (laminated body) as compared with the case where the first insulating base material layer covers a part of the outer periphery of the first surfaces S1A and S1B of the mounting electrodes P1 and P2.
（ｆ）また、本実施形態に係る電子機器３０１では、上記多層基板１０１の実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂが、導電性接合材１を介して実装基板２０１に接合される。この構成により、導電性接合材１と実装電極Ｐ１，Ｐ２とを高い接合強度で接合でき、実装後において実装基板２０１等から多層基板の剥離を抑制した電子機器を実現できる。 (F) In the electronic apparatus 301 according to the present embodiment, the first surfaces S1A and S1B of the mounting electrodes P1 and P2 of the multilayer substrate 101 are bonded to the mounting substrate 201 via the conductive bonding material 1. With this configuration, the conductive bonding material 1 and the mounting electrodes P1 and P2 can be bonded with high bonding strength, and an electronic device in which peeling of the multilayer substrate from the mounting substrate 201 or the like can be realized after mounting.
　なお、本実施形態に係る多層基板１０１は、例えば次の工程で製造される。図５は多層基板１０１の製造工程を順に示す断面図である。なお、図５では、説明の都合上ワンチップ（個片）での製造工程で説明するが、実際の振動板の製造工程は集合基板状態で行われる。 Note that the multilayer substrate 101 according to the present embodiment is manufactured by, for example, the following process. FIG. 5 is a cross-sectional view sequentially showing the manufacturing steps of the multilayer substrate 101. In FIG. 5, for the convenience of explanation, the manufacturing process using one chip (individual piece) will be described. However, the actual manufacturing process of the diaphragm is performed in a collective substrate state.
　図５中の（１）に示すように、まず複数の絶縁基材層１１，１２，１３，１４，１５を準備する。絶縁基材層１１，１２，１３，１４，１５は、例えば液晶ポリマー（ＬＣＰ）またはポリエーテルエーテルケトン（ＰＥＥＫ）等の熱可塑性樹脂シートである。 As shown in (1) of FIG. 5, first, a plurality of insulating base material layers 11, 12, 13, 14, and 15 are prepared. The insulating base layers 11, 12, 13, 14, and 15 are thermoplastic resin sheets such as liquid crystal polymer (LCP) or polyether ether ketone (PEEK).
　その後、絶縁基材層１１（第１絶縁基材層）に、互いに対向する第１面Ｓ１Ａ，Ｓ１Ｂおよび第２面Ｓ２Ａ，Ｓ２Ｂを有した実装電極Ｐ１，Ｐ２を形成する。具体的には、集合基板状態の絶縁基材層１１の片側主面に、金属箔（例えばＣｕ箔）を、その金属箔の第１面Ｓ１Ａ，Ｓ１Ｂ側が絶縁基材層１１に接するように、ラミネートする。その後、その金属箔をフォトリソグラフィでパターンニングすることで、実装電極Ｐ１，Ｐ２を形成する。実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂは粗面化されている。第１面Ｓ１Ａ，Ｓ１Ｂの粗面化は、例えばサンドブラスタ法、プラズマ法、めっき法、エッチング法等によって行われる。 Thereafter, mounting electrodes P1 and P2 having first surfaces S1A and S1B and second surfaces S2A and S2B facing each other are formed on the insulating base layer 11 (first insulating base layer). Specifically, on one side main surface of the insulating base material layer 11 in the aggregate substrate state, a metal foil (for example, Cu foil) is disposed so that the first surface S1A, S1B side of the metal foil is in contact with the insulating base material layer 11. Laminate. Thereafter, the metal foil is patterned by photolithography to form mounting electrodes P1 and P2. The first surfaces S1A and S1B of the mounting electrodes P1 and P2 are roughened. The first surfaces S1A and S1B are roughened by, for example, a sand blaster method, a plasma method, a plating method, an etching method, or the like.
　第１絶縁基材層（絶縁基材層１１）の表面に、第１面Ｓ１Ａ，Ｓ１Ｂが接するように実装電極Ｐ１，Ｐ２を形成するこの工程が、本発明における「電極形成工程」の例である。 This step of forming the mounting electrodes P1, P2 so that the first surfaces S1A, S1B are in contact with the surface of the first insulating base layer (insulating base layer 11) is an example of the “electrode forming step” in the present invention. is there.
　また、複数の絶縁基材層１２，１３，１４（第２絶縁基材層）に、導体２１，２２，２３，２４，２５等をそれぞれ形成する。具体的には、集合基板状態の絶縁基材層１２，１３，１４の片側主面に、金属箔（例えばＣｕ箔）をラミネートし、その金属箔をフォトリソグラフィでパターンニングすることで、導体２１，２２，２３，２４，２５等を形成する。なお、絶縁基材層１２，１３，１４に接する導体２１，２２，２３，２４，２５の一方面（図５における導体２１，２２，２３，２４，２５の下面）は、上述した実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂと同様に、粗面化されている。 Also, conductors 21, 22, 23, 24, 25, etc. are respectively formed on the plurality of insulating base material layers 12, 13, 14 (second insulating base material layers). Specifically, a metal foil (for example, Cu foil) is laminated on one side main surface of the insulating base material layers 12, 13, and 14 in the aggregated substrate state, and the metal foil is patterned by photolithography, whereby the conductor 21 , 22, 23, 24, 25, and the like. Note that one surface of the conductors 21, 22, 23, 24, 25 in contact with the insulating base material layers 12, 13, 14 (the lower surfaces of the conductors 21, 22, 23, 24, 25 in FIG. 5) is the mounting electrode P1 described above. , P2 are roughened in the same manner as the first surfaces S1A and S1B.
　なお、複数の絶縁基材層１３，１４には、層間接続導体Ｖ１，Ｖ２が形成される。層間接続導体Ｖ１，Ｖ２は、絶縁基材層１３，１４にレーザー等で貫通孔を設けた後、Ｃｕ，Ａｇ，Ｓｎ，Ｎｉ，Ｍｏ等のうち１以上もしくはそれらの合金を含む導電性ペーストを配設し、後の加熱加圧で硬化（固化）させることによって設けられる。そのため、層間接続導体Ｖ１，Ｖ２は、後の加熱加圧時の温度よりも融点（溶融温度）が低い材料とする。 In addition, interlayer connection conductors V1 and V2 are formed on the plurality of insulating base material layers 13 and 14, respectively. Interlayer connection conductors V1 and V2 are made of a conductive paste containing one or more of Cu, Ag, Sn, Ni, Mo, etc. or an alloy thereof after providing through holes in insulating base layers 13 and 14 with a laser or the like. It is provided by being disposed and cured (solidified) by subsequent heating and pressing. Therefore, the interlayer connection conductors V1 and V2 are made of a material having a melting point (melting temperature) lower than the temperature at the time of subsequent heating and pressurization.
　次に、図５中の（２）に示すように、絶縁基材層１１，１２，１３，１４，１５の順に積層する。このとき、第１絶縁基材層（絶縁基材層１１）に実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂが対向し、且つ、第２面Ｓ２Ａ，Ｓ２Ｂが第２絶縁基材層（絶縁基材層１２）に第２面Ｓ２Ａ，Ｓ２Ｂが対向するように複数の絶縁基材層１１，１２，１３，１４，１５を積層する。 Next, as shown in (2) in FIG. 5, the insulating base layers 11, 12, 13, 14, and 15 are laminated in this order. At this time, the first surfaces S1A and S1B of the mounting electrodes P1 and P2 are opposed to the first insulating base layer (insulating base layer 11), and the second surfaces S2A and S2B are the second insulating base layer (insulating). A plurality of insulating base layers 11, 12, 13, 14, and 15 are laminated so that the second surfaces S2A and S2B face the base layer 12).
　上記「電極形成工程」の後に、第１絶縁基材層に第１面Ｓ１Ａ，Ｓ１Ｂが対向し、且つ第２絶縁基材層に第２面Ｓ２Ａ，Ｓ２Ｂが対向するように複数の絶縁基材層１１，１２，１３，１４，１５を積層するこの工程が、本発明における「積層工程」の例である。 After the “electrode formation step”, a plurality of insulating base materials are provided such that the first surfaces S1A and S1B face the first insulating base material layer and the second surfaces S2A and S2B face the second insulating base material layer. This step of laminating the layers 11, 12, 13, 14, and 15 is an example of the “lamination step” in the present invention.
　その後、図５中の（２）（３）に示すように、積層した複数の絶縁基材層１１，１２，１３，１４，１５を加熱加圧（一括プレス）することにより、集合基板状態の積層体１０ＡＰを構成する。このとき、実装電極Ｐ１，Ｐ２は、積層体１０ＡＰの内部に埋設される。 Thereafter, as shown in (2) and (3) in FIG. 5, by heating and pressing (collective pressing) the plurality of laminated insulating base material layers 11, 12, 13, 14, and 15, The stacked body 10AP is configured. At this time, the mounting electrodes P1 and P2 are embedded in the stacked body 10AP.
　上記「積層工程」の後に、積層した複数の絶縁基材層１１，１２，１３，１４，１５を加熱加圧して、積層体１０ＡＰを形成するとともに、実装電極Ｐ１，Ｐ２を積層体１０ＡＰの内部に埋設するこの工程が、本発明における「積層体形成工程」の例である。 After the “lamination step”, the laminated insulating base material layers 11, 12, 13, 14, and 15 are heated and pressurized to form the laminated body 10AP, and the mounting electrodes P1 and P2 are disposed inside the laminated body 10AP. This step of embedding in the substrate is an example of the “laminated body forming step” in the present invention.
　次に、図５中の（３）に示すように、積層体１０ＡＰを除去し、第１絶縁基材層（絶縁基材層１１）に、第１面Ｓ１Ａ，Ｓ１Ｂの一部を露出させる基材層非形成部ＮＦＰ１，ＮＦＰ２を形成する。具体的には、積層体１０ＡＰの第１主面ＶＳ１に対し、積層方向（Ｚ軸方向）に向かって照射されるレーザー光ＬＲによって形成される。レーザー光ＬＲは、積層体１０ＡＰの内部に埋設される実装電極Ｐ１，Ｐ２で遮られる。したがって、この製造方法を用いることで、第１面Ｓ１Ａ，Ｓ１Ｂの一部を露出させる基材層非形成部ＮＦＰ１，ＮＦＰ２を容易に形成できる。 Next, as shown in (3) in FIG. 5, the laminated body 10AP is removed, and the first insulating base material layer (insulating base material layer 11) is exposed to a part of the first surfaces S1A and S1B. The material layer non-formation parts NFP1 and NFP2 are formed. Specifically, the first main surface VS1 of the stacked body 10AP is formed by a laser beam LR that is irradiated toward the stacking direction (Z-axis direction). The laser beam LR is blocked by the mounting electrodes P1 and P2 embedded in the stacked body 10AP. Therefore, by using this manufacturing method, it is possible to easily form the base material layer non-forming portions NFP1, NFP2 that expose a part of the first surfaces S1A, S1B.
　上記「積層体形成工程」の後に、積層体１０ＡＰを実装面側から除去し、第１絶縁基材層（絶縁基材層１１）に、第１面Ｓ１Ａ，Ｓ１Ｂの一部を露出させる基材層非形成部ＮＦＰ１，ＮＦＰ２を形成するこの工程が、本発明における「除去工程」の例である。 After the “layered body forming step”, the layered body 10AP is removed from the mounting surface side, and the base material from which the first surfaces S1A and S1B are partially exposed to the first insulating base material layer (insulating base material layer 11). This step of forming the layer non-forming portions NFP1 and NFP2 is an example of the “removal step” in the present invention.
　最後に、集合基板から個々の個片に分離して、図５中の（４）に示すような多層基板１０１を得る。 Finally, the multilayer substrate 101 as shown in (4) of FIG.
　上記の製造方法により、複数の絶縁基材層１１，１２，１３，１４，１５を積層して形成される積層体１０Ａと、絶縁基材層のいずれかに形成される実装電極Ｐ１，Ｐ２とを備える構成において、実装基板等に実装した際に、実装基板等に対する十分な接合強度を確保できる多層基板を容易に製造できる。 10A of laminated bodies formed by laminating | stacking the some insulating base material layers 11, 12, 13, 14, and 15 by said manufacturing method, Mounting electrode P1, P2 formed in either of the insulating base materials layers, In the configuration including the multilayer substrate, it is possible to easily manufacture a multilayer substrate that can ensure sufficient bonding strength to the mounting substrate or the like when mounted on the mounting substrate or the like.
　また、多層基板１０１は、実装電極Ｐ１，Ｐ２が、Ｚ軸方向から視て、第１主面ＶＳ１（実装面）の外縁に達していない。そのため、集合基板から個片（多層基板）を分離する際に、実装電極Ｐ１，Ｐ２ごと個片に分離する必要がない。したがって、製造時における積層体１０Ａからの実装電極Ｐ１，Ｐ２の剥離を防止できる。 Further, in the multilayer substrate 101, the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface VS1 (mounting surface) when viewed from the Z-axis direction. Therefore, when separating the individual pieces (multilayer substrate) from the collective substrate, it is not necessary to separate the mounting electrodes P1 and P2 into individual pieces. Therefore, it is possible to prevent the mounting electrodes P1 and P2 from being peeled off from the stacked body 10A during manufacturing.
　さらに、本実施形態では、積層体を形成する複数の絶縁基材層１１，１２，１３，１４，１５が熱可塑性樹脂からなる。上記製造方法によれば、積層した複数の絶縁基材層１１，１２，１３，１４，１５を一括プレスすることにより、積層体１０Ａを容易に形成できるため、絶縁基材の製造工程の工数が削減され、コストを低く抑えることができる。 Furthermore, in this embodiment, the plurality of insulating base material layers 11, 12, 13, 14, and 15 forming the laminate are made of a thermoplastic resin. According to the manufacturing method described above, since the laminated body 10A can be easily formed by collectively pressing the plurality of laminated insulating base material layers 11, 12, 13, 14, and 15, the man-hours for the manufacturing process of the insulating base material are reduced. The cost can be kept low.
　《第２の実施形態》
　第２の実施形態では、基材層非形成部の構成が異なる多層基板の例を示す。 << Second Embodiment >>
In 2nd Embodiment, the example of the multilayer substrate from which the structure of a base material layer non-formation part differs is shown.
　図６は、第２の実施形態に係る多層基板１０２の斜視図である。図７（Ａ）は図６におけるＢ－Ｂ断面図であり、図７（Ｂ）は、多層基板１０２の底面図である。図７（Ｂ）では、構造を分かりやすくするため、実装電極の第１面のうち、積層体から露出する部分をドットパターンで示している。 FIG. 6 is a perspective view of the multilayer substrate 102 according to the second embodiment. 7A is a cross-sectional view taken along the line BB in FIG. 6, and FIG. 7B is a bottom view of the multilayer substrate 102. In FIG. 7B, in order to make the structure easy to understand, a portion of the first surface of the mounting electrode that is exposed from the stacked body is indicated by a dot pattern.
　多層基板１０２は、複数の絶縁基材層１１，１２，１３，１４，１５を積層して形成される積層体１０Ｂ、実装電極Ｐ１，Ｐ２、複数の導体２１，２２，２３，２４，２５および複数の層間接続導体Ｖ１，Ｖ２等を備える。 The multilayer substrate 102 includes a laminated body 10B formed by laminating a plurality of insulating base layers 11, 12, 13, 14, and 15, mounting electrodes P1 and P2, a plurality of conductors 21, 22, 23, 24, and 25, and A plurality of interlayer connection conductors V1, V2, etc. are provided.
　多層基板１０２は、基材層非形成部ＮＦＰ１，ＮＦＰ２の形状が、第１の実施形態に係る多層基板１０１と異なる。その他の構成については、多層基板１０１と実質的に同じである。 The multilayer substrate 102 is different from the multilayer substrate 101 according to the first embodiment in the shapes of the base material layer non-forming portions NFP1 and NFP2. Other configurations are substantially the same as those of the multilayer substrate 101.
　以下、第１の実施形態に係る多層基板１０１と異なる部分について説明する。 Hereinafter, parts different from the multilayer substrate 101 according to the first embodiment will be described.
　本実施形態では、基材層非形成部ＮＦＰ１，ＮＦＰ２が、Ｚ軸方向から視て、が、第１主面（実装面）の外縁に達している（図７（Ｂ）における基材層非形成部ＮＦＰ１の左辺、および基材層非形成部ＮＦＰ２の右辺を参照）。 In the present embodiment, the base material layer non-forming portions NFP1, NFP2 reach the outer edge of the first main surface (mounting surface) as viewed from the Z-axis direction (the base material layer non-forming portion in FIG. 7B). (See the left side of the forming part NFP1 and the right side of the base material layer non-forming part NFP2).
　また、本実施形態では、図７（Ｂ）に示すように、第１絶縁基材層（図７（Ａ）における絶縁基材層１１を参照）が、第１面（Ｓ１Ａ，Ｓ１Ｂ）の外周の半分以上を覆っている。具体的には、第１絶縁基材層は、第１面（Ｓ１Ａ）の外周の約３／４（図７（Ｂ）における実装電極Ｐ１の上辺、右辺および下辺）を覆っている。また、第１絶縁基材層は、第１面（Ｓ１Ｂ）の外周の約３／４（図７（Ｂ）における実装電極Ｐ２の上辺、左辺および下辺）を覆っている。 In this embodiment, as shown in FIG. 7B, the first insulating base material layer (see the insulating base material layer 11 in FIG. 7A) is the outer periphery of the first surface (S1A, S1B). Covers more than half. Specifically, the first insulating base layer covers about 3/4 of the outer periphery of the first surface (S1A) (the upper side, the right side, and the lower side of the mounting electrode P1 in FIG. 7B). In addition, the first insulating base layer covers about 3/4 of the outer periphery of the first surface (S1B) (the upper side, the left side, and the lower side of the mounting electrode P2 in FIG. 7B).
　次に、導電性接合材を用いて、多層基板１０２を実装基板に実装した状態について、図を参照して説明する。図８は、第２の実施形態に係る電子機器３０２の主要部を示す断面図である。 Next, a state where the multilayer substrate 102 is mounted on a mounting substrate using a conductive bonding material will be described with reference to the drawings. FIG. 8 is a cross-sectional view illustrating a main part of the electronic device 302 according to the second embodiment.
　電子機器３０２は、多層基板１０２および実装基板２０１等を備える。図８に示すように、多層基板１０２は、実装基板２０１に実装される。実装基板２０１は、第１の実施形態で説明したものと同じである。 The electronic device 302 includes a multilayer substrate 102, a mounting substrate 201, and the like. As shown in FIG. 8, the multilayer substrate 102 is mounted on the mounting substrate 201. The mounting substrate 201 is the same as that described in the first embodiment.
　実装電極Ｐ１，Ｐ２の第１面Ｓ１Ａ，Ｓ１Ｂは、導電性接合材１を介して、実装基板２０１の導体４１，４２にそれぞれ接合される。図８に示すように、第１面Ｓ１Ａ，Ｓ１Ｂは、はんだフィレットを形成して実装基板２０１に接合される。 The first surfaces S1A and S1B of the mounting electrodes P1 and P2 are bonded to the conductors 41 and 42 of the mounting substrate 201 through the conductive bonding material 1, respectively. As shown in FIG. 8, the first surfaces S1A and S1B are bonded to the mounting substrate 201 by forming solder fillets.
　本実施形態に係る多層基板１０２によれば、第１の実施形態で述べた効果以外に、次のような効果を奏する。 The multilayer substrate 102 according to the present embodiment has the following effects in addition to the effects described in the first embodiment.
（ａ）多層基板１０２では、実装電極Ｐ１，Ｐ２が、Ｚ軸方向から視て、第１主面（実装面）の外縁に達していない。一方、基材層非形成部ＮＦＰ１，ＮＦＰ２は、Ｚ軸方向から視て、第１主面（実装面）の外縁に達している。この構成により、図８に示すように、実装面の外縁にまで達する基材層非形成部ＮＦＰ１，ＮＦＰ２を利用して、多層基板の実装面積を大きくすることなく、はんだフィレットを形成できる。そのため、実装基板２０１等に対する接合信頼性を高め、高密度配置が可能な多層基板を実現できる。 (A) In the multilayer substrate 102, the mounting electrodes P1 and P2 do not reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction. On the other hand, the base material layer non-forming portions NFP1, NFP2 reach the outer edge of the first main surface (mounting surface) when viewed from the Z-axis direction. With this configuration, as shown in FIG. 8, a solder fillet can be formed without increasing the mounting area of the multilayer board by using the base layer non-forming portions NFP1, NFP2 reaching the outer edge of the mounting surface. Therefore, it is possible to realize a multilayer substrate that can improve the bonding reliability with respect to the mounting substrate 201 and the like and can be arranged at high density.
　すなわち、この構成により、多層基板の実装面積を大きくすることなく、実装基板２０１等に対する多層基板の接合信頼性を高めた電子機器を実現できる。 That is, with this configuration, it is possible to realize an electronic device that has improved the bonding reliability of the multilayer substrate to the mounting substrate 201 or the like without increasing the mounting area of the multilayer substrate.
　なお、本実施形態では、第１絶縁基材層が、第１面（Ｓ１Ａ，Ｓ１Ｂ）の外周の約３／４を覆っている多層基板の例を示したが、この構成に限定されるものではない。第１絶縁基材層（絶縁基材層１１）が、第１面（Ｓ１Ａ，Ｓ１Ｂ）の外周の半分以上を覆っていれば、多層基板（積層体）から実装電極Ｐ１，Ｐ２を剥離し難くできるという作用・効果を奏する（上記（ｅ）を参照）。但し、多層基板から実装電極Ｐ１，Ｐ２を剥離し難くできるという点では、第１絶縁基材層は、第１面（Ｓ１Ａ，Ｓ１Ｂ）の外周全部を覆うことが好ましい。 In the present embodiment, the example of the multilayer substrate in which the first insulating base material layer covers about 3/4 of the outer periphery of the first surface (S1A, S1B) is shown, but the present invention is limited to this configuration. is not. If the first insulating base layer (insulating base layer 11) covers more than half of the outer periphery of the first surface (S1A, S1B), it is difficult to peel the mounting electrodes P1, P2 from the multilayer substrate (laminated body). The effect | action and effect that it can do are show | played (refer said (e)). However, it is preferable that the first insulating base layer covers the entire outer periphery of the first surface (S1A, S1B) in that it is difficult to peel the mounting electrodes P1, P2 from the multilayer substrate.
　《その他の実施形態》
　以上に示した各実施形態では、積層体１０Ａ，１０Ｂが略直方体状である例を示したが、この構成に限定されるものではない。積層体の平面形状は、本発明の作用・効果を奏する範囲において適宜変更可能であり、例えば多角形、円形、楕円形、Ｌ字形、クランク形、Ｔ字形、Ｙ字形等であってもよい。 << Other Embodiments >>
In each embodiment shown above, although the laminated body 10A, 10B showed the example which is a substantially rectangular parallelepiped shape, it is not limited to this structure. The planar shape of the laminate can be changed as appropriate within the range where the functions and effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse, an L shape, a crank shape, a T shape, a Y shape, or the like.
　以上に示した各実施形態では、積層体を形成する複数の絶縁基材層１１，１２，１３，１４，１５が熱可塑性樹脂からなる例について示したが、この構成に限定されるものではない。複数の絶縁基材層１１，１２，１３，１４，１５は、熱硬化性樹脂であってもよい。複数の絶縁基材層１１，１２，１３，１４，１５が熱可塑性樹脂である場合には、上述したように、絶縁基材を容易に形成できるため、多層基板の製造工程の工数が削減され、コストを低く抑えることができる。 In each embodiment shown above, although the example which the some insulating base material layers 11, 12, 13, 14, and 15 which form a laminated body consist of a thermoplastic resin was shown, it is not limited to this structure. . The plurality of insulating base layers 11, 12, 13, 14, and 15 may be thermosetting resins. When the plurality of insulating base material layers 11, 12, 13, 14, and 15 are thermoplastic resins, the insulating base material can be easily formed as described above, thereby reducing the number of steps in the manufacturing process of the multilayer substrate. Cost can be kept low.
　また、以上に示した各実施形態では、５つの絶縁基材層１１，１２，１３，１４，１５を積層して形成される積層体を備えた多層基板について示したが、この構成に限定されるものではない。積層体を形成する絶縁基材層の層数は、本発明の作用・効果を奏する範囲において適宜変更可能である。 Further, in each of the embodiments described above, the multilayer substrate provided with the laminated body formed by laminating the five insulating base material layers 11, 12, 13, 14, and 15 has been described. However, the present invention is not limited to this configuration. It is not something. The number of insulating base material layers forming the laminate can be changed as appropriate within the range where the functions and effects of the present invention are exhibited.
　さらに、以上に示した各実施形態では、１つの第１絶縁基材層（絶縁基材層１１）および４つの第２絶縁基材層（絶縁基材層１２，１３，１４，１５）を積層して形成される積層体の例を示したが、第１絶縁基材層の数および第２絶縁基材層の数はこれに限定されるものではない。第１絶縁基材層の数および第２絶縁基材層の数は、本発明の作用・効果を奏する範囲において適宜変更可能である。第１絶縁基材層の数は、例えば２つ以上であってもよい。また、第２絶縁基材層の数は、１つであってもよく、２つ以上であってもよい。 Further, in each of the embodiments described above, one first insulating base material layer (insulating base material layer 11) and four second insulating base material layers (insulating base material layers 12, 13, 14, 15) are laminated. However, the number of the first insulating base layers and the number of the second insulating base layers are not limited thereto. The number of the first insulating base material layers and the number of the second insulating base material layers can be appropriately changed within a range where the functions and effects of the present invention are exhibited. The number of first insulating base layers may be two or more, for example. Further, the number of the second insulating base layers may be one or two or more.
　以上に示した各実施形態では、矩形の実装電極Ｐ１，Ｐ２を備える多層基板の例を示したが、この構成に限定されるものではない。実装電極の形状は、本発明の作用・効果を奏する範囲において適宜変更可能であり、例えば多角形、円形、楕円形、Ｌ字形、クランク形、Ｔ字形、Ｙ字形等であってもよい。また、実装電極の個数は多層基板に形成される回路に応じて適宜変更可能である。 In each of the embodiments described above, an example of a multilayer substrate including rectangular mounting electrodes P1 and P2 has been described, but the present invention is not limited to this configuration. The shape of the mounting electrode can be changed as appropriate within the scope of the operation and effect of the present invention. For example, the mounting electrode may be polygonal, circular, elliptical, L-shaped, crank-shaped, T-shaped, Y-shaped, or the like. Further, the number of mounting electrodes can be appropriately changed according to a circuit formed on the multilayer substrate.
　さらに、以上に示した各実施形態では、第１絶縁基材層が、矩形の基材層非形成部ＮＦＰ１，ＮＦＰ２を有する例を示したが、この構成に限定されるものではない。基材層非形成部の形状は、本発明の作用・効果を奏する範囲において適宜変更可能であり、例えば多角形、円形、楕円形等であってもよい。また、基材層非形成部の数は２つに限定されず、１つであってもよく、３つ以上であってもよい。 Furthermore, in each embodiment shown above, although the 1st insulating base material layer showed the example which has rectangular base material layer non-formation part NFP1, NFP2, it is not limited to this structure. The shape of the base material layer non-forming part can be appropriately changed within the range where the functions and effects of the present invention are exhibited, and may be, for example, a polygon, a circle, an ellipse or the like. Moreover, the number of base material layer non-formation parts is not limited to two, and may be one or three or more.
　以上に示した各実施形態では、複数の絶縁基材層１１，１２，１３，１４，１５を積層して形成される積層体の例を示したが、ソルダーレジスト膜やカバーレイフィルム等の保護層が、積層体の第１主面ＶＳ１または第２主面ＶＳ２に形成されていてもよい。 In each embodiment shown above, although the example of the laminated body formed by laminating | stacking several insulating base material layers 11, 12, 13, 14, and 15 was shown, protection of a solder resist film, a coverlay film, etc. was shown. The layer may be formed on the first main surface VS1 or the second main surface VS2 of the stacked body.
　なお、多層基板に形成される回路は、本発明の作用・効果を奏する範囲において、自由に構成可能である。多層基板には、例えばストリップライン構造、マイクロストリップライン構造、またはコプレーナ線路等の伝送線路が形成されていてもよく、例えば導体パターンで形成されるコイルまたはキャパシタが形成されていてもよい。さらに、多層基板には、チップインダクタやチップキャパシタ等のチップ部品が実装されていてもよい。 It should be noted that the circuit formed on the multilayer substrate can be freely configured as long as the operations and effects of the present invention are achieved. For example, a transmission line such as a stripline structure, a microstripline structure, or a coplanar line may be formed on the multilayer substrate, and for example, a coil or a capacitor formed of a conductor pattern may be formed. Furthermore, chip components such as chip inductors and chip capacitors may be mounted on the multilayer substrate.
　最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形および変更が適宜可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲内と均等の範囲内での実施形態からの変更が含まれる。 Finally, the description of the above embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.
ＬＲ…レーザー光
ＮＦＰ１，ＮＦＰ２…基材層非形成部
Ｐ１，Ｐ２…実装電極
Ｓ１Ａ，Ｓ１Ｂ…実装電極の第１面
Ｓ２Ａ，Ｓ２Ｂ…実装電極の第２面
Ｖ１，Ｖ２…層間接続導体
ＶＳ１…積層体の第１主面（実装面）
ＶＳ２…積層体の第２主面
１…導電性接合材
１０Ａ，１０ＡＰ，１０Ｂ…積層体
１１，１２，１３，１４，１５…絶縁基材層
２１，２２，２３，２４，２５，４１，４２…導体
１０１，１０２…多層基板
２０１…実装基板
３０１，３０２…電子機器 LR ... Laser beams NFP1, NFP2 ... Substrate layer non-forming portions P1, P2 ... Mounting electrodes S1A, S1B ... Mounting electrode first surfaces S2A, S2B ... Mounting electrode second surfaces V1, V2 ... Interlayer connection conductor VS1 ... Laminated First main surface of body (mounting surface)
VS2 ... 2nd main surface of laminated body 1 ... Conductive bonding materials 10A, 10AP, 10B ... Laminated bodies 11, 12, 13, 14, 15 ... Insulating base material layers 21, 22, 23, 24, 25, 41, 42 ... Conductors 101, 102 ... Multilayer board 201 ... Mounting boards 301, 302 ... Electronic equipment

Claims (8)

  1. 　実装面を有し、第１絶縁基材層および第２絶縁基材層を含む複数の絶縁基材層を積層して形成される積層体と、
    　第１面および前記第１面に対向する第２面を有し、前記複数の絶縁基材層のいずれかに形成される実装電極と、
    　を備え、
    　前記実装電極は、前記第１面が前記第１絶縁基材層と対向するように、且つ、前記第２面が前記第２絶縁基材層と対向するように、前記第１絶縁基材層と前記第２絶縁基材層との間に挟まれ、
    　前記第１面の表面粗さは、前記第２面の表面粗さよりも大きく、
    　前記第１絶縁基材層は、前記第１面の一部を露出させる基材層非形成部を有する、多層基板。     A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer;
    A mounting electrode that has a first surface and a second surface opposite to the first surface, and is formed on any of the plurality of insulating base layers;
    With
    The mounting electrode has the first insulating base layer so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer. And the second insulating base material layer,
    The surface roughness of the first surface is greater than the surface roughness of the second surface,
    The first insulating base material layer has a base material layer non-forming portion that exposes a part of the first surface.
  2. 　前記第１絶縁基材層および前記第２絶縁基材層は、同じ樹脂材料からなる、請求項１に記載の多層基板。 The multilayer substrate according to claim 1, wherein the first insulating base layer and the second insulating base layer are made of the same resin material.
  3. 　前記実装電極は、前記複数の絶縁基材層の積層方向から視て、前記実装面の外縁に達していない、請求項１または２に記載の多層基板。 The multilayer substrate according to claim 1 or 2, wherein the mounting electrode does not reach an outer edge of the mounting surface when viewed from a stacking direction of the plurality of insulating base layers.
  4. 　前記第１絶縁基材層は、前記第１面の外周の半分以上を覆う、請求項１から３のいずれかに記載の多層基板。 The multilayer substrate according to any one of claims 1 to 3, wherein the first insulating base layer covers more than half of the outer periphery of the first surface.
  5. 　前記実装電極は、前記複数の絶縁基材層の積層方向から視て、前記実装面の外縁近傍に配置され、
    　前記基材層非形成部は、前記複数の絶縁基材層の積層方向から視て、前記実装面の前記外縁に達する、請求項４に記載の多層基板。     The mounting electrode is disposed in the vicinity of the outer edge of the mounting surface as viewed from the stacking direction of the plurality of insulating base layers,
    The multilayer substrate according to claim 4, wherein the base layer non-forming portion reaches the outer edge of the mounting surface when viewed from the stacking direction of the plurality of insulating base layers.
  6. 　請求項１から５のいずれかに記載の多層基板と、
    　実装基板と、
    　を備え、
    　前記実装電極の前記第１面は、導電性接合材を介して前記実装基板に接合される、電子機器。     A multilayer substrate according to any one of claims 1 to 5;
    A mounting board;
    With
    The electronic device, wherein the first surface of the mounting electrode is bonded to the mounting substrate via a conductive bonding material.
  7. 　請求項４または５に記載の多層基板と、
    　実装基板と、
    　を備え、
    　前記実装電極の前記第１面は、はんだフィレットを形成して前記実装基板に接合されている、電子機器。     The multilayer substrate according to claim 4 or 5,
    A mounting board;
    With
    The electronic device, wherein the first surface of the mounting electrode forms a solder fillet and is bonded to the mounting substrate.
  8. 　実装面を有し、第１絶縁基材層および第２絶縁基材層を含む複数の絶縁基材層を積層して形成される積層体と、
    　第１面、および前記第１面に対向し、前記第１面よりも表面粗さが小さな第２面を有し、前記複数の絶縁基材層のいずれかに形成される実装電極と、
    　を備える多層基板の製造方法であって、
    　　前記第１絶縁基材層の表面に、前記第１面が接するように前記実装電極を形成する、電極形成工程と、
    　　前記電極形成工程の後に、前記第１絶縁基材層に前記第１面が対向し、且つ、前記第２絶縁基材層に前記第２面が対向するように前記複数の絶縁基材層を積層する、積層工程と、
    　前記積層工程の後に、積層した前記複数の絶縁基材層を加熱加圧して前記積層体を形成するとともに、前記実装電極を前記積層体の内部に埋設する、積層体形成工程と、
    　前記積層体形成工程の後に、前記積層体を前記実装面側から除去し、前記第１絶縁基材層に、前記第１面の一部を露出させる基材層非形成部を形成する、除去工程と、
    　を備える、多層基板の製造方法。     A laminated body having a mounting surface and formed by laminating a plurality of insulating base material layers including a first insulating base material layer and a second insulating base material layer;
    A mounting electrode facing the first surface and the first surface, having a second surface having a smaller surface roughness than the first surface, and formed on any of the plurality of insulating base layers;
    A method for producing a multilayer substrate comprising:
    Forming the mounting electrode such that the first surface is in contact with the surface of the first insulating base layer;
    After the electrode forming step, the plurality of insulating base layers are formed so that the first surface faces the first insulating base layer and the second surface faces the second insulating base layer. Laminating, laminating process,
    After the laminating step, the laminated body is formed by heating and pressurizing the plurality of laminated insulating base material layers, and the mounting electrode is embedded in the laminated body.
    After the layered body forming step, the layered body is removed from the mounting surface side, and a base material layer non-forming portion that exposes a part of the first surface is formed on the first insulating base material layer. Process,
    A method for manufacturing a multilayer substrate.
PCT/JP2018/006679 2017-03-06 2018-02-23 Multi-layer substrate, electronic apparatus, and method for producing multi-layer substrate WO2018163859A1 (en)

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