WO2015083216A1 - Substrat multicouche et son procédé de fabrication - Google Patents

Substrat multicouche et son procédé de fabrication Download PDF

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Publication number
WO2015083216A1
WO2015083216A1 PCT/JP2013/082364 JP2013082364W WO2015083216A1 WO 2015083216 A1 WO2015083216 A1 WO 2015083216A1 JP 2013082364 W JP2013082364 W JP 2013082364W WO 2015083216 A1 WO2015083216 A1 WO 2015083216A1
Authority
WO
WIPO (PCT)
Prior art keywords
multilayer
substrate
multilayer substrate
pattern
manufacturing
Prior art date
Application number
PCT/JP2013/082364
Other languages
English (en)
Japanese (ja)
Inventor
善洋 福島
浩二 加本
昭一 山田
Original Assignee
山一電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 山一電機株式会社 filed Critical 山一電機株式会社
Priority to JP2015551279A priority Critical patent/JPWO2015083216A1/ja
Priority to PCT/JP2013/082364 priority patent/WO2015083216A1/fr
Publication of WO2015083216A1 publication Critical patent/WO2015083216A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates

Definitions

  • the present invention relates to a multilayer substrate and a method of manufacturing the same, and more particularly to a thin multilayer substrate and a method of manufacturing the same.
  • a flexible printed circuit board (FPC: Flexible Printed Circuit) is a printed circuit board (substrate) having a structure that can be bent using a thin insulating material.
  • a substrate refers to a rigid wiring board (hard substrate).
  • the rigid wiring board is a hard board on which components are mounted to form a circuit, and has a structure that does not bend.
  • Flexible wiring boards or rigid flexible wiring boards are thin and soft characteristics that can be bent or broken, and thus enable three-dimensional wiring and movable part wiring in equipment. For this reason, flexible wiring boards or rigid flexible wiring boards are widely used in familiar electronic devices, and are indispensable for reducing the size and weight of electronic devices such as mobile phones and liquid crystal televisions. .
  • the multilayer substrate by the build-up method it is necessary to repeat the lamination several times. Therefore, in the thermoplastic resin, the damage due to the heat history increases, and thinning the layers reduces the reliability and thins the multilayer substrate. There is a problem that it is difficult to In addition, in a method such as a laser via or a through hole other than the build-up method, it is necessary to perform a plating process, and since the thickness of the plating layer is added, it is difficult to reduce the thickness.
  • an object of the present invention is to provide a multilayer substrate capable of suppressing the problem of deformation such as distortion or wrinkle of the multilayer substrate generated when thinning the multilayer substrate, and a method of manufacturing the same.
  • a multilayer substrate of the present invention is a multilayer substrate which has a multilayer structure which laminates a conductive layer and an insulating layer one by one alternately, and a substrate which forms the above multilayer structure when laminating.
  • the conductive layer is characterized in that a pattern for increasing the porosity in the entire surface of the pattern is formed to suppress the deformation of the conductive layer.
  • the pattern for increasing the porosity may be a mesh pattern.
  • the multilayer printed wiring board of this invention is characterized by having the said multilayer structure.
  • the multilayer flexible wiring board of this invention is characterized by having the said multilayer structure.
  • a multilayer rigid flexible wiring board of the present invention is characterized by having the above-mentioned multilayer structure.
  • a manufacturing method of a multilayer board of the present invention is a manufacturing method of a multilayer board which laminates a conductive layer and an insulating layer one by one alternately, and when laminating, forming the above-mentioned multilayer board Forming a pattern on the conductive layer so as to increase the porosity of the entire surface of the pattern so as to suppress deformation of the substrate.
  • the present invention by forming a pattern for increasing the porosity on the entire surface of the pattern in the conductive layer, it is possible to suppress the problem of deformation such as distortion or wrinkle of the multilayer substrate that occurs when thinning the multilayer substrate. Thus, it is possible to provide a thinner multilayer substrate and a method of manufacturing the same.
  • 1 to 4 are conceptual views of an example of a method of manufacturing a multilayer substrate according to the present invention.
  • bumps 103 are printed on the conductor 102 to form a wiring pattern connecting two wiring layers in the internal circuit.
  • the bumps are also a kind of vias, and in this case, they are called bumps in the manufacturing process and are called vias after manufacturing.
  • an Ag-based conductive resin is generally used as the bump 103
  • copper is generally used as the conductor 102, but the invention is not limited thereto.
  • thermoplastic resin 101 and the other conductor 102 are simultaneously laminated on the printed conductor of the bump 103 on the above-mentioned conductor 102 to create a prototype (not shown) of a double-sided board. Do.
  • thermoplastic resin 101 Although a liquid crystal polymer (LCP: Liquid Crystal Polymer (CTZ: manufactured by Kuraray Co., Ltd.)) is used as the thermoplastic resin 101, the invention is not limited thereto.
  • LCP Liquid Crystal Polymer (CTZ: manufactured by Kuraray Co., Ltd.)
  • CTZ Liquid Crystal Polymer
  • the thermoplastic resin 101 is not limited to the above-mentioned materials as long as it satisfies such characteristics.
  • one of the conductors 102 indicated by the one-dot-and-dash line of the above-mentioned double-sided substrate prototype is etched to form a circuit pattern 102 ', and a two-layer basic lamination unit 100 is produced. Note that the conductor 102 on the inner side when being laminated is etched before being laminated, and the conductor 102 on the outer side when being laminated is etched after being laminated. The same applies to the following steps.
  • the same process as the lamination unit 100 is performed to form another lamination unit (not shown), and then the bumps 103 are printed on the circuit pattern 102 ′ on the etched surface to laminate two layers. Create a unit 110.
  • thermosetting resin 104 is sandwiched between the lamination unit 100 and the lamination unit 110 as an adhesive layer to form a lamination unit of four layers.
  • a thermosetting insulating resin film for bonding ADFLEMA (registered trademark): made by Namix Co., Ltd.
  • ADFLEMA registered trademark
  • Other resins can also be used as long as they are resinous.
  • the conductor 102 on the inner side is etched when laminating the four-layered lamination unit created by laminating the lamination unit 100 and the lamination unit 110, to form a circuit pattern 102 ', and four layers are formed.
  • thermosetting resin 104 is laminated as an adhesive layer between the four-layer stacking unit 220 and the two-layer stacking unit 230 to form a six-layer stacking unit.
  • the conductor 102 on the inner surface is etched when laminating a six-layered lamination unit made by laminating four-layered lamination units 220 and two-layered lamination units 230, and a circuit pattern 102 '.
  • a six-layer stacked unit 340 To form a six-layer stacked unit 340.
  • the same process as the four-layer stacking unit 220 is performed to create another four-layer stacking unit having a different circuit pattern, and the circuit pattern 102 'on the inner surface when stacking is performed.
  • the bumps 103 are printed on the substrate to make a lamination unit 350.
  • thermosetting resin 104 is sandwiched and laminated as an adhesive layer between a six-layer lamination unit 340 and a four-layer lamination unit 350 to form a ten-layer lamination unit 460.
  • the first and tenth layers of the conductor 102 which became the outermost surface, are etched to form a circuit pattern 102 ', and finally, a surface is coated with a cover, plating, etc.
  • the manufacture of the laminated substrate is completed.
  • the order of lamination is not limited to this example, and two, four, and four layers of lamination units are prepared, and two and eight layers of lamination units may be simultaneously laminated. Each of the layers may be prepared and laminated, or two layers may be sequentially laminated, and the invention is not limited to these examples.
  • the plating step necessary for the method such as the laser via and the through hole becomes unnecessary, so that a thin multilayer substrate without a plating layer can be formed.
  • thermosetting resin has a glass transition temperature higher than the lamination pressing temperature
  • the use of the thermosetting resin makes it possible to reduce the damage due to the heat history due to the repetition of lamination (sequential lamination), and Even if it is made thinner, the reliability can be kept high, and therefore, thinning of the multilayer substrate by the build-up method can be achieved.
  • thermosetting resins generally have low flame retardancy, it is difficult to satisfy the standards of flame retardancy such as UL (Underwriters Laboratories) if the insulating layer is composed only of thermosetting resins, but the flame retardancy is low.
  • UL Underwriters Laboratories
  • thermoplastic resin 101 and the thermosetting resin 104 have stable and excellent electric characteristics (for example, low dielectric constant, low dielectric loss tangent, low moisture absorption) in a high frequency region, the next generation high speed transmission Can also respond.
  • FIG. 5 is a schematic view of a 10-layer rigid flexible wiring board 500 as an embodiment of the multilayer board of the present invention.
  • a ten-layer rigid flexible wiring board 500 includes a ten-layer conductor 502 of conductive layers LY1 to LY10 and a thermoplastic resin 501 laminated between conductors 502 such as adjacent conductive layers LY1 and LY2.
  • a thermosetting resin 504 laminated between the adjacent conductive layers LY2, LY3 and the like, and a via 503 connecting the conductors are provided.
  • the thermoplastic resin 501 and the thermosetting resin 504 are alternately stacked between the conductors 502.
  • the thermoplastic resin 501 and the thermosetting resin 504 are alternately stacked between the conductors 502, the present invention is not limited thereto. That is, only the thermoplastic resin 501 may be used, or only the thermosetting resin 504 may be used.
  • a liquid crystal polymer is used as the thermoplastic resin 501, it is not limited thereto.
  • attachment is used as the thermosetting resin 504, it is not limited to this.
  • openings 506 and 507 are formed in the conductor 502 (conductive layers LY1 to LY3) and the conductor 502 (conductive layers LY8 to LY10).
  • the thermoplastic resin 501 is exposed as a cover lay 508 on the surface of the openings 506 and 507, and a flexible wiring portion 509 is formed.
  • a cover coat 505 is stacked on the surface of the conductor 502 (conductive layers LY1 and LY10) other than the opening, and a rigid wiring portion 510 is formed.
  • the cover lay 508 is a soft film for protecting the surface of the flexible printed wiring portion 509.
  • thermoplastic resin 501 exposed on the surface of the openings 506 and 507 or the opening 506, Polyimide or the like attached to 507 later is used.
  • the thermosetting resin 504 can not generally be used as the coverlay 508 because the flame retardancy is low.
  • the multilayer board of the present invention can be used also as a rigid wiring board or a flexible wiring board by selecting the above-mentioned production method.
  • the number of layers can be changed because the build-up method using bumps is used.
  • 6 to 10 are views for explaining one embodiment of a method of manufacturing a multilayer substrate according to the present invention.
  • conductors 602 are formed on both sides of a thermoplastic resin 601 to form a stacked unit 600.
  • Bumps 603 are printed inside the thermoplastic resin 601 to form a wiring pattern for connecting two wiring layers (conductive layers LY 3, LY 4, etc.).
  • the bump printing process is performed in the same manner as the processes shown in FIGS. 1 to 4.
  • the conductor 602 on the inner side during lamination is etched before lamination, and the conductor 602 on the outer side during lamination is etched after lamination, but here the description will be described. I omit it.
  • the conductors 602 (conductive layers LY5 and LY6) are formed on both surfaces of the thermoplastic resin 601, and the bumps 603 are printed on the surface on the conductor 602 (conductive layer LY5) side to form a stacked unit 610.
  • conductors 602 are formed on both sides of a thermoplastic resin 601, and a thermosetting resin 604 for bonding is disposed on the surface of the conductor 602 (conductive layer LY2).
  • thermosetting resin 604 when it is desired to form a flexible wiring portion 609 described later, an opening is provided in the thermosetting resin 604, and a polyimide film or the like is disposed as the spacer 605 in the opening so that peeling can be performed after lamination. Keep it.
  • an opening is provided in the thermosetting resin 604, the conductor 602 (conductive layer LY2), and the conductor 602 (conductive layer LY3) shown in FIG. 7B described later.
  • the above-mentioned lamination unit 600, 610 is sandwiched between the thermosetting resin 604 for adhesion and laminated, and the bump 603 is printed on the surface on the side of the conductor 602 (conductive layer LY3).
  • the conductor 602 (conductive layers LY7 and LY8) is formed on both sides of the thermoplastic resin 601, and the bumps 603 are printed on the surface on the conductor 602 (conductive layer LY8) side to create a stacked unit 740.
  • conductors 602 are formed on both sides of the thermoplastic resin 601, and a thermosetting resin 604 for bonding is disposed on the surface of the conductor 602 (conductive layer LY9),
  • the lamination unit 750 is created.
  • an opening is provided in the thermosetting resin 604 so that the surface of the thermoplastic resin 601 is exposed, and a polyimide film or the like is disposed as the spacer 605 in the opening. And allow them to peel off after lamination.
  • an opening is provided in the thermosetting resin 604, the conductor 602 (conductive layer LY9), and the conductor 602 (conductor layer LY8) illustrated in FIG. 7C described above.
  • the lamination unit 720 and the lamination unit 730 are laminated to form a lamination unit 860.
  • the lamination unit 740 and the lamination unit 750 are laminated, and the bumps 603 are printed on the surface of the conductor 602 (conductive layer LY7) to form a lamination unit 870.
  • the lamination unit 860 and the lamination unit 870 are laminated with the thermosetting resin 604 for bonding interposed therebetween, to form a 10-layer lamination unit 980.
  • the flexible opening is slitted before outer shape processing so that lid removal can be performed.
  • a cover coat and plating treatment are performed, and then lid removal is performed to expose the flexible wiring portion 609, and a rigid flexible wiring board 1090 of 10 layers is completed.
  • a thermoplastic resin 601, polyimide, or the like can be used as the cover lay 608 on the surface of the flexible wiring portion 609. Further, portions other than the flexible wiring portion 609 become the rigid wiring portion 610.
  • the inventors focused attention on the porosity of the portion where wrinkles occur in the substrate from observation of the cross section and the like.
  • the porosity indicates the ratio of a non-patterned portion in a solid GND portion or the like of a substrate, and the same content can also be indicated by the residual copper ratio when the conductor 602 is copper.
  • FIG. 11 is a schematic view showing some examples of mesh patterns formed on the entire surface of the pattern in the multilayer substrate of the present invention.
  • the mesh pattern 1100 is a mesh pattern of 0.1 mm width ⁇ 0.7 mm pitch and 74% of porosity
  • the mesh pattern 1110 is porosity of 0.5 mm width ⁇ 3.0 mm pitch
  • the mesh pattern is a 69% mesh pattern
  • the mesh pattern 1120 is a 0.1 mm width ⁇ 0.4 mm pitch mesh pattern with a porosity of 51%
  • the mesh pattern 1130 is 0.5 mm width ⁇ 1.5 mm pitch
  • the mesh pattern is a mesh pattern with a porosity of 45%
  • the mesh pattern 1140 is a mesh pattern with a 0.2 mm width ⁇ 0.4 mm pitch and an porosity of 18%
  • the mesh pattern 1150 is a 1.0 mm width ⁇ 1 .5 mm pitch and 12% porosity mesh pattern.
  • the present invention by providing a mesh pattern on the entire surface of the pattern, problems such as distortion and wrinkles of the substrate that occur when laminating low-permittivity materials such as liquid crystal polymers and thin materials are realized. It is possible to reduce the thickness of the multilayer substrate compared to the present.
  • Laminated unit 101 100, 110, 220, 230, 340, 350, 460, 600, 610, 720, 730, 740, 750, 860, 870, 980
  • Laminated unit 101 501, 601

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention a pour objet un substrat multicouche qui, en dépit d'une épaisseur réduite, ne connaît pas de problèmes de déformation, notamment de distorsion et d'ondulation, ainsi que son procédé de fabrication. Un substrat multicouche, ledit substrat multicouche présentant une structure multicouche comprenant successivement une couche conductrice et une couche isolante superposées en alternance, et son procédé de fabrication sont caractérisés en ce que, lors de la superposition, un motif qui accroît la porosité sur toute sa surface est formé dans la couche conductrice de façon à empêcher la déformation du substrat formant la structure multicouche.
PCT/JP2013/082364 2013-12-02 2013-12-02 Substrat multicouche et son procédé de fabrication WO2015083216A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015551279A JPWO2015083216A1 (ja) 2013-12-02 2013-12-02 多層基板、及び、その製造方法
PCT/JP2013/082364 WO2015083216A1 (fr) 2013-12-02 2013-12-02 Substrat multicouche et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/082364 WO2015083216A1 (fr) 2013-12-02 2013-12-02 Substrat multicouche et son procédé de fabrication

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WO2015083216A1 true WO2015083216A1 (fr) 2015-06-11

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160163611A1 (en) * 2014-12-03 2016-06-09 International Business Machines Corporation Laminate substrates having radial cut metallic planes
WO2022234748A1 (fr) * 2021-05-07 2022-11-10 株式会社村田製作所 Élément d'antenne, appareil électronique et procédé de fabrication d'élément d'antenne

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH085579Y2 (ja) * 1990-02-08 1996-02-14 新光電気工業株式会社 薄膜配線基板
JPH11135949A (ja) * 1997-10-29 1999-05-21 Ibiden Co Ltd 多層プリント配線板
JP2004040032A (ja) * 2002-07-08 2004-02-05 Ngk Spark Plug Co Ltd 配線基板及び配線基板の製造方法
JP2009290193A (ja) * 2008-04-28 2009-12-10 Cmk Corp リジッドフレックス多層プリント配線板とその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4728054B2 (ja) * 2005-06-17 2011-07-20 株式会社フジクラ 多層配線用基材および多層配線用基材の製造方法および多層配線板
JP2007059645A (ja) * 2005-08-25 2007-03-08 Sony Chemical & Information Device Corp 複合配線基板
JP2012094646A (ja) * 2010-10-26 2012-05-17 Daisho Denshi Co Ltd 特性インピーダンスコントロール対応プリント配線基板
JP5541122B2 (ja) * 2010-11-30 2014-07-09 山一電機株式会社 フレキシブル配線板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH085579Y2 (ja) * 1990-02-08 1996-02-14 新光電気工業株式会社 薄膜配線基板
JPH11135949A (ja) * 1997-10-29 1999-05-21 Ibiden Co Ltd 多層プリント配線板
JP2004040032A (ja) * 2002-07-08 2004-02-05 Ngk Spark Plug Co Ltd 配線基板及び配線基板の製造方法
JP2009290193A (ja) * 2008-04-28 2009-12-10 Cmk Corp リジッドフレックス多層プリント配線板とその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160163611A1 (en) * 2014-12-03 2016-06-09 International Business Machines Corporation Laminate substrates having radial cut metallic planes
US9818682B2 (en) * 2014-12-03 2017-11-14 International Business Machines Corporation Laminate substrates having radial cut metallic planes
WO2022234748A1 (fr) * 2021-05-07 2022-11-10 株式会社村田製作所 Élément d'antenne, appareil électronique et procédé de fabrication d'élément d'antenne
JP7420315B2 (ja) 2021-05-07 2024-01-23 株式会社村田製作所 アンテナ素子、電子機器及びアンテナ素子の製造方法

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