WO2011118307A1 - Procédé de fabrication de substrat avec condensateur intégré ainsi que procédé de fabrication de feuille d'élément utilisable dans ce procédé de fabrication de substrat avec condensateur intégré - Google Patents

Procédé de fabrication de substrat avec condensateur intégré ainsi que procédé de fabrication de feuille d'élément utilisable dans ce procédé de fabrication de substrat avec condensateur intégré Download PDF

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Publication number
WO2011118307A1
WO2011118307A1 PCT/JP2011/053639 JP2011053639W WO2011118307A1 WO 2011118307 A1 WO2011118307 A1 WO 2011118307A1 JP 2011053639 W JP2011053639 W JP 2011053639W WO 2011118307 A1 WO2011118307 A1 WO 2011118307A1
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WIPO (PCT)
Prior art keywords
capacitor
dielectric layer
layer
metal foil
substrate
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PCT/JP2011/053639
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English (en)
Japanese (ja)
Inventor
仁志 野口
直樹 田中
達也 仲村
賢一 江崎
一也 二木
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三洋電機株式会社
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Publication of WO2011118307A1 publication Critical patent/WO2011118307A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/236—Terminals leading through the housing, i.e. lead-through
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672—Superposed layout, i.e. in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points

Definitions

  • the present invention relates to a method for manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in an insulating substrate, and a method for manufacturing an element sheet that can be used in the manufacturing method.
  • capacitors are provided at a plurality of locations in a surface region (305) (upper surface in FIG. 17; hereinafter referred to as “upper surface”) on which a semiconductor element such as a CPU is mounted.
  • a ground terminal (306) and a power supply terminal (307) to which both electrode layers (301) and (302) of the element (300) are to be electrically connected are formed.
  • the capacitor element (300) is embedded in the insulating substrate (304) so that both electrode layers (301) and (302) are substantially parallel to the upper surface (305) of the insulating substrate (304).
  • the first electrode layer (301) and each ground terminal (306) are electrically connected to each other through conductive vias (308) and (309) formed in the insulating substrate (304).
  • the second electrode layer (302) of (300) and each power supply terminal (307) are electrically connected to each other through a conductive via (310) formed in the insulating substrate (304).
  • the capacitor element (300) is mounted on one of the two insulating substrates constituting the insulating substrate (304), and then the other insulating substrate. Is laminated on one insulating substrate.
  • the capacitor element (300) mounted on the insulating base material has a small thickness and is in the form of a sheet.
  • Such a capacitor element (300) requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements (300) to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements (300) on the insulating base material becomes complicated.
  • a metal foil is pasted on the insulating base material, and then the metal foil is etched to thereby form the capacitor element on the insulating base material.
  • a first electrode layer (301) is formed, and then a dielectric layer (303) and a second electrode layer (302) are formed on the first electrode layer (301).
  • a dielectric layer (303) and a second electrode layer (302) are formed on the first electrode layer (301).
  • the dielectric layer (303) and the second electrode layer (302) of the capacitor element (300) must be formed on an insulating substrate.
  • a film forming method such as a sputtering method, a vacuum evaporation method, or a sol-gel method is used.
  • the dielectric material or metal material for forming the dielectric layer (303) and the second electrode layer (302) of the capacitor element (300) may be mixed into another component such as an insulating base material. It was.
  • it is necessary to perform heat treatment to form the capacitor element (300) there is a possibility that another component may be adversely affected by the heat treatment. Therefore, in the above method, it is difficult to mount the capacitor element (300) in a good state on the insulating substrate.
  • the first electrode layer (301) is formed at a plurality of locations on the insulating substrate, a dielectric film is formed on the first electrode layer (301) by using a film formation method such as sputtering, vacuum deposition, or sol-gel method.
  • a film formation method such as sputtering, vacuum deposition, or sol-gel method.
  • the body layer (303) is formed, only the dielectric layer having the same composition and the same thickness dimension is formed on the first electrode layer (301). For this reason, when a plurality of capacitor elements (300) having different capacitances are built in the insulating substrate (304), the film formation area of the dielectric layer (303) of each capacitor element (300) must be changed. It was.
  • the dielectric layer (303) is formed on the first electrode layer (301) by using a film forming method such as sputtering, vacuum deposition, or sol-gel method, before the dielectric layer (303) is formed. It is necessary to mask a region different from the film formation region of the dielectric layer. For this reason, manufacture of a substrate with a built-in capacitor becomes complicated, and the yield of the substrate with a built-in capacitor may be reduced.
  • a film forming method such as sputtering, vacuum deposition, or sol-gel method
  • the film forming method is different on the first electrode layer (301) by repeatedly performing the film forming method by changing the kind of the dielectric material and / or re-forming the masking. It is possible to form dielectric layers of components and / or different thickness dimensions. However, in this method, it is necessary to re-form the masking, and therefore the manufacture of the capacitor built-in substrate becomes complicated.
  • the object of the present invention is a manufacturing method capable of manufacturing a capacitor-embedded substrate by mounting a capacitor element having a desired capacitance at a predetermined position on an insulating substrate, despite being a simple method. And the manufacturing method of the element sheet
  • a method for manufacturing a capacitor-embedded substrate according to the present invention includes one or a plurality of capacitor elements having a dielectric layer interposed between a first electrode layer and a second electrode layer, and an insulating substrate.
  • This is a method for manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in the insulating substrate by embedding the capacitor element, and includes an element sheet manufacturing step, a pasting step, an etching step, and a laminating step.
  • the element sheet manufacturing step using a metal foil, a powder spray coating method is used on one or a plurality of predetermined regions to be the first electrode layer of the one or more capacitor elements.
  • an element sheet having one or a plurality of element portions made of the metal layer formed on the dielectric layer is prepared.
  • the element sheet is affixed on one insulating base material among the two insulating base materials constituting the insulating substrate.
  • the metal foil is etched to leave the one or more predetermined regions on the one insulating base material, so that one or more elements of the element sheet are formed on the one insulating substrate.
  • the one or a plurality of capacitor elements each having a portion are formed.
  • the insulating substrate is formed by laminating the other insulating base material on the one insulating base material.
  • the capacitor element is mounted at a predetermined position on the insulating substrate.
  • the dielectric layer is formed using a powder spray coating method.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • a dielectric layer having a desired film formation area and / or a desired thickness dimension can be formed in a predetermined region regardless of whether or not the surface of the metal foil is masked. Is possible. Therefore, even when a dielectric layer is formed on a plurality of predetermined regions of the metal foil, the film formation area and / or thickness dimension of the dielectric layer can be changed for each predetermined region, and the change can be easily performed. Can be done. Further, according to the powder spray coating method, the type of dielectric material sprayed for each predetermined region can be changed, and the change can be easily performed.
  • a capacitor element having a desired capacitance can be mounted at a predetermined position on the insulating substrate. Therefore, even when the design related to the capacitance of the capacitor element is changed, it is only necessary to change at least one of the type of dielectric material constituting the dielectric layer, the film formation area of the dielectric layer, and the thickness dimension. There is no need to redesign the arrangement of the capacitor elements. Further, the dielectric layer can be formed without masking the metal foil, and therefore the yield of the capacitor built-in substrate can be improved.
  • the capacitor element mounted on the insulating substrate in the above manufacturing method has a small thickness dimension and is in the form of a sheet.
  • Such a capacitor element requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements on the insulating base material becomes complicated.
  • the capacitor element is formed by performing the etching process, and the capacitor element is handled as an element sheet until the etching process is performed. Therefore, it is not necessary to handle the capacitor elements individually, and the process of mounting the capacitor elements on the insulating substrate is simplified.
  • condenser element are formed on this metal foil, and the element sheet
  • etching step a part of the surface on the metal layer side of the predetermined region to be left in the metal foil is covered with the metal layer. Etching is performed on the metal foil.
  • the element sheet manufacturing step in the element sheet manufacturing step, a plurality of film formation areas and / or thickness dimensions different from each other on the plurality of predetermined regions of the metal foil using the powder spray coating method.
  • the dielectric layer is formed, and then the metal layer is formed on each dielectric layer, thereby producing an element sheet having the plurality of element portions.
  • the element sheet manufacturing method produces an element sheet having one or more element portions to be one or more capacitor elements in which a dielectric layer is interposed between the first electrode layer and the second electrode layer. And a dielectric layer forming step and a metal layer forming step.
  • a metal foil is used, and a powder spray coating method is performed on one or a plurality of predetermined regions to be the first electrode layer of the one or more capacitor elements in the metal foil.
  • a metal layer to be the second electrode layer is formed on the dielectric layer.
  • the element portion of the element sheet includes a predetermined area of the metal foil, a dielectric layer formed on the predetermined area, and a metal layer formed on the dielectric layer.
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • a dielectric layer having a desired film formation area and / or a desired thickness dimension can be formed in a predetermined region regardless of whether or not the surface of the metal foil is masked. Is possible. Therefore, even when a dielectric layer is formed on a plurality of predetermined regions of the metal foil, the film formation area and / or thickness dimension of the dielectric layer can be changed for each predetermined region, and the change can be easily performed. Can be done. Further, according to the powder spray coating method, the type of dielectric material sprayed for each predetermined region can be changed, and the change can be easily performed.
  • the element sheet manufacturing method can be used as an element sheet manufacturing step included in the capacitor-embedded substrate manufacturing method.
  • the film formation area and / or the thickness dimension of each of the plurality of predetermined regions of the metal foil are mutually different using the powder spray coating method.
  • a plurality of different dielectric layers are formed, and the metal layer is formed on each dielectric layer in the metal layer forming step.
  • the manufacturing method of the present invention it is possible to manufacture a capacitor built-in substrate by mounting a capacitor element having a desired capacitance on a predetermined position on an insulating base material in spite of a simple method. .
  • FIG. 1 is a cross-sectional view showing a capacitor built-in substrate.
  • FIG. 2 is an enlarged view of a region A shown in FIG.
  • FIG. 3 is a plan view of the capacitor element built in the capacitor built-in substrate as seen from the second electrode layer side.
  • FIG. 4 is a diagram showing impedance characteristics of the capacitor built-in substrate.
  • FIG. 5A is a perspective view used for explaining the dielectric layer forming step of the method for manufacturing a capacitor-embedded substrate
  • FIG. 5B is a cross-sectional view taken along the line BB shown in FIG. It is sectional drawing which follows a line.
  • FIG. 6 is a diagram showing a film forming apparatus used in the aerosol deposition method.
  • FIG. 6 is a diagram showing a film forming apparatus used in the aerosol deposition method.
  • FIG. 7 is a diagram showing a film forming apparatus used in the powder jet deposition method.
  • FIG. 8 is a perspective view used for explaining the annealing step in the method for manufacturing the capacitor built-in substrate.
  • FIG. 9 is a perspective view used for explaining the resist forming process of the method for manufacturing the capacitor built-in substrate.
  • FIG. 10 is a perspective view used for explaining the plating process of the method for manufacturing the capacitor built-in substrate.
  • FIG. 11 is a plan view showing the state of the second sheet for element formation after execution of the plating step.
  • FIG. 12 is a plan view used for explaining the resist stripping process in the method for manufacturing the capacitor built-in substrate.
  • 13 is a cross-sectional view taken along the line CC shown in FIG. FIG.
  • FIG. 14 is a cross-sectional view used for explaining the affixing process of the method for manufacturing a capacitor built-in substrate.
  • FIG. 15 is a cross-sectional view used for explaining the etching process of the method for manufacturing the capacitor built-in substrate.
  • FIG. 16 is a cross-sectional view used for explaining the stacking process of the method for manufacturing the capacitor-embedded substrate.
  • FIG. 17 is a cross-sectional view showing a conventional capacitor built-in substrate.
  • FIG. 18 is a cross-sectional view showing a conventional capacitor mounting board.
  • FIG. 1 is a cross-sectional view showing an example of a capacitor built-in substrate manufactured by the manufacturing method according to the present invention.
  • the substrate with a built-in capacitor includes an insulating substrate (2).
  • the insulating substrate (2) includes a first electrode layer (11), a second electrode layer (12), and a plurality of portions in the insulating substrate (2).
  • a capacitor element (1) having a dielectric layer (13) interposed therebetween is embedded between them, whereby a plurality of capacitor elements (1) are built in the insulating substrate (2).
  • Each capacitor element (1) is embedded in the insulating substrate (2) in such a posture that the surfaces of both electrode layers (11), (12) are substantially parallel to the surface of the insulating substrate (2). Further, the right side capacitor element (1) in FIG. 1 has a smaller thickness dimension T of the dielectric layer (13) than the left side capacitor element (1). That is, in the present embodiment, a plurality of capacitor elements (1) having different thickness dimensions T of the dielectric layer (13) are embedded in the insulating substrate (2).
  • each dielectric layer (13) is composed of barium titanate (BaTiO3), lithium niobate (LiNbO3), lithium borate (Li2B4O7), lead zirconate titanate (PbZrTiO3), strontium titanate (SrTiO3), titanium It is formed from various dielectric materials mainly composed of lead lanthanum zirconate (PbLaZrTiO3), lithium tantalate (LiTaO3), zinc oxide (ZnO), tantalum oxide (Ta2O5) and the like.
  • the dielectric layer (13) may contain an additive to improve dielectric properties, insulating properties, strength, and the like.
  • the insulating substrate (2) is formed from a material having flame retardancy, for example, a material of FR-4 (Flame Retardant Type 4).
  • FR-4 Flame Retardant Type 4
  • the material of FR-4 is a flame retardant material made of, for example, a composite material of glass fiber and epoxy resin.
  • the first electrode layer (11) of the capacitor element (1) is formed of a metal foil.
  • the metal foil is formed of a metal material that can form a foil and can be an electrode layer, such as copper (Cu), nickel (Ni), aluminum (Al), platinum (Pt), or the like.
  • the metal foil can be handled by itself, for example, can hold itself.
  • the thickness dimension of the metal foil is preferably 1 ⁇ m or more.
  • copper (Cu) is used as the metal material of the metal foil forming the first electrode layer (11).
  • the second electrode layer (12) of the capacitor element (1) is formed of a metal thin film.
  • the metal thin film is a metal film formed thinly on the surface of the base material such as the dielectric layer (13), and a thin film such as copper (Cu) can be formed and can be an electrode layer. It is formed from a metal material. Therefore, the metal thin film is difficult to handle by itself, and is handled integrally with the base material.
  • the thickness dimension of the metal thin film is preferably 20 ⁇ m or less.
  • copper (Cu) is used as the metal material of the metal thin film that forms the second electrode layer (12).
  • FIG. 2 is an enlarged view of area A shown in FIG.
  • FIG. 3 is a plan view of the capacitor element (1) shown in FIG. 2 as viewed from the second electrode layer (12) side.
  • the first electrode layer (11) of the capacitor element (1) has a surface (111) on the second electrode layer (12) side (upper surface in FIG. 2; hereinafter referred to as “upper surface”). Is covered with the second electrode layer (12).
  • the first electrode layer (11) has a substantially square shape
  • the second electrode layer (12) has a substantially square shape having a smaller area than the first electrode layer (11).
  • the second electrode layer (12) covers the central region of the upper surface (111) of the first electrode layer (11).
  • the dielectric layer (13) is a region (112) covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). It is not formed on the region (113) formed above and not covered by the second electrode layer (12).
  • a first conductive via (31) and a second conductive via (32) are formed in the insulating substrate (2).
  • the first conductive via (31) is electrically connected to a region (113) not covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11).
  • the second conductive via (32) is electrically connected to the surface (121) of the second electrode layer (12) opposite to the first electrode layer (11) (the upper surface in FIG. 2).
  • the two conductive vias 31 and 32 are formed on the surface region 21 on the second electrode layer 12 side of the capacitor element 1 in the surface of the insulating substrate 2 (the upper surface in FIG. 2).
  • both conductive vias (31) and (32) are exposed in the surface region (21).
  • a conductive material such as copper (Cu) is used to form both conductive vias (31) and (32).
  • the first conductive is provided at 12 locations on the region (113) not covered by the second electrode layer (12) among the upper surface (111) of the first electrode layer (11).
  • Vias (31) are formed, and second conductive vias (32) are formed at four locations on the upper surface (121) of the second electrode layer (12).
  • (31) and the second conductive vias (32) to (32) are arranged in a 4 ⁇ 4 matrix on the paper surface of FIG.
  • a ground terminal (41) and a power supply terminal (42) are formed on the upper surface (21) of the insulating substrate (2).
  • the tip of each first conductive via (31) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected to the ground terminal (41), and the power terminal (42)
  • the tip of each second conductive via (32) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected. Therefore, an electrical path is formed between the ground terminal (41) and the power supply terminal (42) via the capacitor element (1).
  • the tip of each second conductive via (32) may be connected to the ground terminal (41), and the tip of each first conductive via (31) may be connected to the power supply terminal (42).
  • each first conductive via (31) extends toward the upper surface (21) of the insulating substrate (2) without being in electrical contact with the second electrode layer (12), and is formed on the upper surface (21).
  • the front end portion of the first conductive via (31) can be exposed. Therefore, the conductive via to be electrically connected to the conventional capacitor-embedded substrate, specifically the first electrode layer (11), is the first electrode of the capacitor element (1) in the surface of the insulating substrate (2).
  • the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced. This improves the impedance characteristics of the capacitor built-in substrate in the high frequency region.
  • FIG. 4 is a graph (91) showing the impedance characteristics obtained by simulation for the capacitor built-in substrate shown in FIG.
  • the impedance characteristic of the conventional capacitor mounting board is also shown by a graph (92).
  • a chip-like capacitor element (316) is mounted on the lower surface (311) of the insulating substrate (304).
  • an electrical path is formed between the power supply terminal (306) and the ground terminal (307) formed on the upper surface (305) of the insulating substrate (304) via the capacitor element (316).
  • the element sheet manufacturing process the attaching process, the etching process, and the laminating process are executed in this order.
  • a dielectric layer forming process an annealing process, a resist forming process, a plating process, and a resist stripping process are executed in this order.
  • FIG. 5 (a) is a perspective view used for explaining the dielectric layer forming step
  • FIG. 5 (b) is a cross-sectional view taken along the line BB shown in FIG. 5 (a).
  • a metal foil (50) is prepared, and the surface (501) of the metal foil (50), specifically, the A dielectric layer (13) is formed on the predetermined region (54) to be the first electrode layer (11) of each capacitor element (1) in the metal foil (50) by using a powder spray coating method.
  • the dielectric layer (13) is formed on each predetermined region (54) so as to cover a part of the predetermined region (54).
  • a film forming apparatus (7) is used for forming the dielectric layer (13).
  • predetermined regions (54) are set in 11 locations of one metal foil (50) formed of copper (Cu), and each predetermined region (54) is set on each predetermined region (54).
  • a dielectric layer (13) having a square shape is formed using a powder spray coating method. At this time, the dielectric layer (13) is formed on each predetermined region (54) so as to cover the central portion of the predetermined region (54).
  • the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas.
  • the powder spray coating method includes various film forming methods such as an aerosol deposition method and a powder jet deposition method.
  • FIG. 6 is a view showing a film forming apparatus (7) used in the aerosol deposition method.
  • the film forming apparatus (7) maintains the inside in a vacuum state by an aerosol generator (71) that stirs and mixes powder with high-pressure gas to form an aerosol, and a vacuum pump (73).
  • the film forming chamber (72) that can be connected is connected by a thin transfer tube (74).
  • the inside of the film formation chamber (72) is maintained in a vacuum state, whereby the space (high pressure space) in the aerosol generator (71) into which the high pressure gas flows and the film formation chamber (72) There will be a pressure difference between this space (low pressure space). Accordingly, the powder aerosolized by the aerosol generator (71) flows in the transfer tube (74) toward the film forming chamber (72).
  • a stage (75) for installing a target having a surface on which a thin film is to be formed is provided, and the stage (75) is an installation surface on which the target is installed ( 751), a translation in the XY plane, translation in the Z-axis direction perpendicular to the XY plane, and rotation around the Z-axis are possible.
  • One end of the transfer tube (74) is disposed in the film forming chamber (72), and at one end, a slit-like nozzle (76) is attached with its tip directed toward the installation surface (751) of the stage (75). It has been.
  • the nozzle (76) has a shape capable of accelerating the powder discharged from one end of the transfer tube (74) to about 100 m / sec.
  • the powder discharged at high speed from the tip of the nozzle (76) is sprayed onto the surface of the target on the stage (75).
  • FIG. 7 is a view showing a film forming apparatus (7) used in the powder jet deposition method.
  • the film forming apparatus (7) includes a stepped nozzle (81) having two regions (811) and (812) having different inner diameters, and the nozzle (81) has an inner diameter.
  • a through hole (82) for supplying powder is formed at a position close to the second region (812) having a small inner diameter in the large first region (811).
  • the discharged powder is sprayed onto the surface of the target on the stage (75) as in the film forming apparatus (FIG. 6) used in the aerosol deposition method.
  • the powdery dielectric material is sprayed onto the predetermined region (54) of the metal foil (50) using the powder spray coating method. Thereby, the powdery dielectric material collides with the predetermined region (54) and is crushed, and the powdery dielectric material collides with and crushes on the predetermined region (54).
  • a fine dielectric material is densely deposited on each predetermined region (54) of the metal foil (50) to form a dielectric layer (13).
  • each predetermined region (54) is desired without masking the surface (501) of the metal foil (50). It is possible to form a dielectric layer (13) having a thickness dimension T of. Specifically, the thickness dimension T of the dielectric layer (13) can be easily changed by adjusting the number of scans, scan speed, discharge speed, etc. of the film forming apparatus (7). Accordingly, even when the dielectric layer (13) is formed on the plurality of predetermined regions (54) of the metal foil (50), the dielectric layer (13) is provided for each predetermined region (54) as shown in FIG. The thickness dimension T can be changed, and the change can be easily performed. Further, according to the above-described powder spray coating method, the type of dielectric material sprayed for each predetermined region (54) can be changed, and the change can be easily performed.
  • the dielectric layer forming step masking may be performed on a region different from the region on each predetermined region (54) in the surface (501) of the metal foil (50). Even in this case, it is possible to form the dielectric layer (13) having a desired thickness dimension T on each predetermined region (54) by using the powder spray coating method. Further, on the plurality of predetermined regions (54) of the metal foil (50), not only the plurality of dielectric layers (13) having different thickness dimensions T but also the film forming areas and / or thickness dimensions T are different from each other. A plurality of dielectric layers (13) may be formed.
  • FIG. 8 is a perspective view used for explaining the annealing process.
  • each dielectric layer (13) is irradiated with a laser, thereby annealing the dielectric layer (13).
  • the annealing step is not an essential step in the method for manufacturing a capacitor-embedded substrate according to the present invention, and the annealing step may be performed only when the characteristics of the dielectric layer (13) are further improved.
  • annealing may be performed by a method such as microwave heating, heating in the atmosphere or nitrogen atmosphere (using a furnace or the like), or the like.
  • FIG. 9 is a perspective view used for explaining the resist formation process.
  • a masking process is performed on the first element forming sheet (61).
  • a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next.
  • the dielectric layer (13 The resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.
  • FIG. 10 is a perspective view used for explaining the plating process.
  • the element forming second sheet (62) is subjected to electroless plating by immersing the element forming second sheet (62) in a plating solution (9).
  • a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) is formed on each dielectric layer (13).
  • copper (Cu) is used as the metal material for the electroless plating process.
  • the metal thin film (53) can be formed by a sputtering method, a vapor deposition method, a screen printing method, an ink jet method, or the like.
  • FIG. 12 is a plan view used for explaining the resist stripping process.
  • FIG. 13 is a cross-sectional view taken along the line CC shown in FIG.
  • the resist (52) (see FIG. 11) formed on the surface (501) of the metal foil (50) is stripped to remove the metal foil (50).
  • the resist (52) is removed from the surface (501).
  • An element sheet (6) having a plurality of element parts (5) consisting of (53) is formed.
  • a chemical method can be used for removing the resist (52).
  • FIG. 14 is a cross-sectional view used for explaining the pasting process. As shown in FIG. 14, in the pasting process, the surface of one insulating base material (20) of the two insulating base materials (20), (20) (see FIG. 16) constituting the insulating substrate (2) is applied. The element sheet (6) is pasted.
  • FIG. 15 is a cross-sectional view used for explaining the etching process. As shown in FIG. 15, in the etching step, pattern etching is performed on the metal foil (50) (see FIG. 14) of the element sheet (6) to thereby form each predetermined region set in the metal foil (50) (see FIG. 15). 54) is left on the insulating substrate (20).
  • each predetermined region (54) left on the insulating base (20) is a part of the surface on the metal thin film (53) side, specifically, the central region on the surface on the metal thin film (53) side. It will be covered by the metal thin film (53).
  • the metal thin film (53) a part of the surface on the metal thin film (53) side of the predetermined region (54) to be left out of the metal foil (50) is covered with the metal thin film (53).
  • pattern etching is performed on the metal foil (50).
  • the plurality of element portions (5) of the element sheet (6) are left at predetermined positions on the insulating base (20), and as a result, each element left on the insulating base (20).
  • the capacitor element (1) is formed from the portion (5). Specifically, a predetermined region (54) of the metal foil (50) left on the insulating substrate (20) in each element part (5) becomes the first electrode layer (11) of the capacitor element (1).
  • the metal thin film (53) formed on the predetermined region (54) becomes the second electrode layer (12) of the capacitor element (1).
  • a dielectric is formed between the electrode layers (11) and (12).
  • the capacitor element (1) with the layer (13) interposed is formed.
  • each capacitor element (1) is mounted at a predetermined position on the insulating substrate (20). Further, in the present embodiment, as shown in FIG. 15, the right-side capacitor element (1) and the left-side capacitor element (1) have different thickness dimensions T of the dielectric layer (13). The capacitor elements (1) have different capacitances.
  • the insulating substrate (2) As shown in FIG. 15, in the etching process of the present embodiment, by performing pattern etching on the metal foil (50), in addition to the first electrode layer (11) of the capacitor element (1), the insulating substrate (2) An electrode pattern (55) such as a power supply pattern and a ground pattern to be formed therein is also formed.
  • FIG. 16 is a cross-sectional view used for explaining the lamination process.
  • another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20).
  • the insulating substrate (2) is formed by the two insulating base materials (20) laminated.
  • a first conductive via (31) and a second conductive via (32) corresponding to each capacitor element (1) are formed on the insulating substrate (2), and the insulating substrate (2).
  • a ground terminal (41) and a power supply terminal (42) corresponding to each capacitor element (1) are formed on the upper surface (21).
  • the capacitor built-in substrate is completed.
  • the dielectric layer (13) is formed using a powder spray coating method.
  • the powder spray coating method as described above, even when the dielectric layer (13) is formed on the plurality of predetermined regions (54) of the metal foil (50), as shown in FIG. As described above, the film formation area and / or the thickness dimension T of the dielectric layer (13) can be changed for each predetermined region (54), and the change can be easily performed. Further, according to the powder spray coating method, the type of the dielectric material sprayed for each predetermined region (54) can be changed, and the change can be easily performed.
  • the capacitor element (1) having a desired capacitance can be mounted at a predetermined position on the insulating substrate (20). . Therefore, even when the design related to the capacitance of the capacitor element (1) is changed, the type of the dielectric material constituting the dielectric layer (13), the film formation area of the dielectric layer, and the dielectric layer (13) It is only necessary to change at least one of the thickness dimensions T, and it is not necessary to redesign the arrangement of the capacitor element (1). In addition, the dielectric layer (13) can be formed without masking the metal foil (50), and therefore the yield of the capacitor built-in substrate can be improved.
  • the capacitor element (1) mounted on the insulating substrate (20) in the above manufacturing method has a small thickness and is in the form of a sheet.
  • Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the process of mounting the capacitor elements (1) on the insulating base material (20) becomes complicated.
  • the capacitor element (1) is formed by performing the etching process, and the capacitor element (1) is handled as the element sheet (6) until the etching process is performed. Therefore, it is not necessary to handle the capacitor elements (1) individually, and the process of mounting the capacitor elements on the insulating substrate (20) is simplified.
  • the dielectric layer (13) constituting the capacitor element (1) is formed on the metal foil (50). And the element thin film (53) is formed, and the element sheet
  • substrate with a built-in capacitor exists in the range of 5 micrometers or more and 100 micrometers or less. This is because, when the thickness is smaller than 5 ⁇ m, handling of the element sheet (6) becomes difficult and problems such as an increase in resistance occur. Further, when the thickness dimension is larger than 100 ⁇ m, the thickness of the capacitor element (1) affects the surface of the insulating base material (20), so that irregularities are formed on the surface of the insulating base material (20). This is because it becomes difficult to laminate another insulating base material (20) thereon.
  • the above manufacturing method can also be applied to the manufacture of a capacitor built-in substrate in which the capacitor element (1) is embedded only at one location in the insulating substrate (2).
  • the above manufacturing method can also be applied to the manufacture of a capacitor built-in substrate in which the capacitor element (1) is embedded only at one location in the insulating substrate (2).
  • the etching step only the first electrode layer (11) constituting the capacitor element (1) may be formed from the metal foil (50) without forming the electrode pattern (55).
  • the second electrode layer (12) of the capacitor element (1) may be formed of a metal foil.
  • the shape of the first electrode layer (11) and the second electrode layer (12) of the capacitor element (1) is not limited to a substantially square shape, but the first electrode layer (11) and the second electrode layer (12). ) Various shapes can be used.
  • Capacitor element (11) First electrode layer (12) Second electrode layer (13) Dielectric layer (2) Insulating substrate (20) Insulating substrate (31) First conductive via (32) Second conductive via (41) Ground terminal (42) Power supply terminal (5) Element section (50) Metal foil (53) Metal thin film (metal layer) (54) Predetermined area (6) Element sheet (7) Deposition system

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Capacitors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

Le procédé de fabrication de l'invention comporte : une étape de production d'une feuille d'élément, une étape de collage, une étape de gravure, et une étape de stratification. Lors de l'étape de production de la feuille d'élément, une couche diélectrique (13) est formée à l'aide d'une feuille métallique (50) par processus de revêtement par injection de poudre, sur une région prédéfinie (54) consistant en une première couche d'électrode d'un élément de condensateur, à l'intérieure de ladite feuille métallique (50); puis la feuille d'élément comportant une partie élément est produite par formation sur ladite couche diélectrique (13) d'une couche métallique consistant en une seconde couche d'électrode de l'élément de condensateur. Lors de l'étape de collage, la feuille d'élément est collée sur un matériau de base isolant. Lors de l'étape de gravure, l'élément de condensateur constitué de la partie élément de la feuille d'élément, est formé sur le matériau de base isolant par application d'une gravure sur la feuille métallique (50). Lors de l'étape de stratification, un autre matériau de base isolant est stratifié sur le matériau de base isolant.
PCT/JP2011/053639 2010-03-26 2011-02-21 Procédé de fabrication de substrat avec condensateur intégré ainsi que procédé de fabrication de feuille d'élément utilisable dans ce procédé de fabrication de substrat avec condensateur intégré WO2011118307A1 (fr)

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JP2010071840A JP2013127992A (ja) 2010-03-26 2010-03-26 コンデンサ内蔵基板の製造方法、及び該製造方法に使用可能な素子シートの製造方法
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WO2018034753A3 (fr) * 2016-08-18 2018-06-14 Qualcomm Incorporated Condensateur mim à densité multiple pour performance améliorée de multiplexeur passif sur verre (pog)

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US9349788B2 (en) * 2013-08-08 2016-05-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Thin film capacitors embedded in polymer dielectric

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JP2004342831A (ja) * 2003-05-15 2004-12-02 Fujitsu Ltd 回路基板、電子装置、及び回路基板の製造方法
JP2005294674A (ja) * 2004-04-02 2005-10-20 Matsushita Electric Ind Co Ltd 多層基板、半導体パッケージおよびモジュールの製造方法
JP2006196886A (ja) * 2004-12-21 2006-07-27 E I Du Pont De Nemours & Co 電力コアデバイス及びその作製方法
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JP2011228390A (ja) * 2010-04-16 2011-11-10 Fujitsu Ltd キャパシタ及びその製造方法
WO2018034753A3 (fr) * 2016-08-18 2018-06-14 Qualcomm Incorporated Condensateur mim à densité multiple pour performance améliorée de multiplexeur passif sur verre (pog)
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