WO2011118307A1

WO2011118307A1 - Production method for substrate with built-in capacitor and production method for element sheets that can be used in aforementioned production method

Info

Publication number: WO2011118307A1
Application number: PCT/JP2011/053639
Authority: WO
Inventors: 仁志野口; 直樹田中; 達也仲村; 賢一江崎; 一也二木
Original assignee: 三洋電機株式会社
Priority date: 2010-03-26
Filing date: 2011-02-21
Publication date: 2011-09-29
Also published as: JP2013127992A

Abstract

Disclosed is a production method comprising an element sheet manufacturing step, a pasting step, an etching step, and a laminating step. In the element sheet manufacturing step, a metal foil (50) is used and a dielectric layer (13) is formed by the use of a power injection coating method on a predetermined region (54) in said metal foil (50), whereby said region becomes a first electrode layer for a capacitor element. A metal layer that acts as a second electrode layer for the capacitor element is then formed on said dielectric layer (13) to produce an element sheet with elements. In the pasting step, the element sheet is pasted on an insulation base material. In the etching step, a capacitor element composed of element sheet elements is formed on the insulation base material by etching on the metal foil (50). In the laminating step, a separate insulation base material is laminated on the insulation base material.

Description

Manufacturing method of substrate with built-in capacitor, and manufacturing method of element sheet usable for manufacturing method

The present invention relates to a method for manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in an insulating substrate, and a method for manufacturing an element sheet that can be used in the manufacturing method.

2. Description of the Related Art Conventionally, in order to reduce the size and thickness of a circuit board, an electronic component built-in board in which an electronic component is embedded in an insulating substrate by embedding the electronic component in the insulating substrate has been proposed. In particular, as a technique related to the present application, as shown in FIG. 17, a dielectric layer (303) is interposed between the first electrode layer (301) and the second electrode layer (302) in the insulating substrate (304). A capacitor built-in substrate in which the capacitor element (300) is embedded has been proposed (see, for example, Patent Document 1).

Specifically, among the surfaces of the insulating substrate (304), capacitors are provided at a plurality of locations in a surface region (305) (upper surface in FIG. 17; hereinafter referred to as “upper surface”) on which a semiconductor element such as a CPU is mounted. A ground terminal (306) and a power supply terminal (307) to which both electrode layers (301) and (302) of the element (300) are to be electrically connected are formed. The capacitor element (300) is embedded in the insulating substrate (304) so that both electrode layers (301) and (302) are substantially parallel to the upper surface (305) of the insulating substrate (304). 300) the first electrode layer (301) and each ground terminal (306) are electrically connected to each other through conductive vias (308) and (309) formed in the insulating substrate (304). The second electrode layer (302) of (300) and each power supply terminal (307) are electrically connected to each other through a conductive via (310) formed in the insulating substrate (304).

In the process of manufacturing the capacitor built-in substrate, the capacitor element (300) is mounted on one of the two insulating substrates constituting the insulating substrate (304), and then the other insulating substrate. Is laminated on one insulating substrate.

JP 2004-103967 A JP 2008-218753 A

However, the capacitor element (300) mounted on the insulating base material has a small thickness and is in the form of a sheet. Such a capacitor element (300) requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements (300) to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements (300) on the insulating base material becomes complicated.

Therefore, in the step of mounting the capacitor element (300) on the insulating base material, first, a metal foil is pasted on the insulating base material, and then the metal foil is etched to thereby form the capacitor element on the insulating base material. (300) a first electrode layer (301) is formed, and then a dielectric layer (303) and a second electrode layer (302) are formed on the first electrode layer (301). (For example, refer to Patent Document 2). This eliminates the need to handle the capacitor elements (300) individually.

However, in such a method, the dielectric layer (303) and the second electrode layer (302) of the capacitor element (300) must be formed on an insulating substrate. Here, for the formation of the dielectric layer (303) and the second electrode layer (302), a film forming method such as a sputtering method, a vacuum evaporation method, or a sol-gel method is used. For this reason, there is a possibility that the dielectric material or metal material for forming the dielectric layer (303) and the second electrode layer (302) of the capacitor element (300) may be mixed into another component such as an insulating base material. It was. In addition, when it is necessary to perform heat treatment to form the capacitor element (300), there is a possibility that another component may be adversely affected by the heat treatment. Therefore, in the above method, it is difficult to mount the capacitor element (300) in a good state on the insulating substrate.

In addition, when the first electrode layer (301) is formed at a plurality of locations on the insulating substrate, a dielectric film is formed on the first electrode layer (301) by using a film formation method such as sputtering, vacuum deposition, or sol-gel method. When the body layer (303) is formed, only the dielectric layer having the same composition and the same thickness dimension is formed on the first electrode layer (301). For this reason, when a plurality of capacitor elements (300) having different capacitances are built in the insulating substrate (304), the film formation area of the dielectric layer (303) of each capacitor element (300) must be changed. It was.

Therefore, every time the design related to the capacitance of the capacitor element (300) is changed, the film formation area of the dielectric layer (303) is changed, and therefore the design related to the arrangement of the capacitor element (300) needs to be changed. there were. Therefore, the manufacture of the substrate with a built-in capacitor has been complicated.

Further, when the dielectric layer (303) is formed on the first electrode layer (301) by using a film forming method such as sputtering, vacuum deposition, or sol-gel method, before the dielectric layer (303) is formed. It is necessary to mask a region different from the film formation region of the dielectric layer. For this reason, manufacture of a substrate with a built-in capacitor becomes complicated, and the yield of the substrate with a built-in capacitor may be reduced.

Even when the film forming method is used, the film forming method is different on the first electrode layer (301) by repeatedly performing the film forming method by changing the kind of the dielectric material and / or re-forming the masking. It is possible to form dielectric layers of components and / or different thickness dimensions. However, in this method, it is necessary to re-form the masking, and therefore the manufacture of the capacitor built-in substrate becomes complicated.

Accordingly, the object of the present invention is a manufacturing method capable of manufacturing a capacitor-embedded substrate by mounting a capacitor element having a desired capacitance at a predetermined position on an insulating substrate, despite being a simple method. And the manufacturing method of the element sheet | seat which can be used for this manufacturing method is provided.

A method for manufacturing a capacitor-embedded substrate according to the present invention includes one or a plurality of capacitor elements having a dielectric layer interposed between a first electrode layer and a second electrode layer, and an insulating substrate. This is a method for manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in the insulating substrate by embedding the capacitor element, and includes an element sheet manufacturing step, a pasting step, an etching step, and a laminating step. Here, in the element sheet manufacturing step, using a metal foil, a powder spray coating method is used on one or a plurality of predetermined regions to be the first electrode layer of the one or more capacitor elements. Forming a dielectric layer, and then forming a metal layer to be the second electrode layer on the dielectric layer, whereby the predetermined region of the metal foil and the dielectric layer formed on the predetermined region Then, an element sheet having one or a plurality of element portions made of the metal layer formed on the dielectric layer is prepared. In the affixing step, the element sheet is affixed on one insulating base material among the two insulating base materials constituting the insulating substrate. In the etching step, the metal foil is etched to leave the one or more predetermined regions on the one insulating base material, so that one or more elements of the element sheet are formed on the one insulating substrate. The one or a plurality of capacitor elements each having a portion are formed. In the laminating step, the insulating substrate is formed by laminating the other insulating base material on the one insulating base material.

By carrying out the above manufacturing method, the capacitor element is mounted at a predetermined position on the insulating substrate.

In the above manufacturing method, the dielectric layer is formed using a powder spray coating method. Here, the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas. According to the powder spray coating method, a dielectric layer having a desired film formation area and / or a desired thickness dimension can be formed in a predetermined region regardless of whether or not the surface of the metal foil is masked. Is possible. Therefore, even when a dielectric layer is formed on a plurality of predetermined regions of the metal foil, the film formation area and / or thickness dimension of the dielectric layer can be changed for each predetermined region, and the change can be easily performed. Can be done. Further, according to the powder spray coating method, the type of dielectric material sprayed for each predetermined region can be changed, and the change can be easily performed.

Therefore, according to the manufacturing method of the present invention, although it is a simple method, a capacitor element having a desired capacitance can be mounted at a predetermined position on the insulating substrate. Therefore, even when the design related to the capacitance of the capacitor element is changed, it is only necessary to change at least one of the type of dielectric material constituting the dielectric layer, the film formation area of the dielectric layer, and the thickness dimension. There is no need to redesign the arrangement of the capacitor elements. Further, the dielectric layer can be formed without masking the metal foil, and therefore the yield of the capacitor built-in substrate can be improved.

In addition, the capacitor element mounted on the insulating substrate in the above manufacturing method has a small thickness dimension and is in the form of a sheet. Such a capacitor element requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements on the insulating base material becomes complicated.

According to the above manufacturing method, the capacitor element is formed by performing the etching process, and the capacitor element is handled as an element sheet until the etching process is performed. Therefore, it is not necessary to handle the capacitor elements individually, and the process of mounting the capacitor elements on the insulating substrate is simplified.

Furthermore, in the said manufacturing method, before sticking metal foil on an insulating base material, the dielectric material layer and metal layer which comprise a capacitor | condenser element are formed on this metal foil, and the element sheet | seat is produced. . Therefore, it is not necessary to form the dielectric layer and the metal layer on the insulating substrate. Therefore, there is no possibility that the dielectric material or the metal material for forming the dielectric layer and the metal layer is mixed into another component such as an insulating base material. Further, even when it is necessary to perform a heat treatment to form the capacitor element, there is no possibility that the heat treatment adversely affects another component.

In the specific configuration of the manufacturing method, in the etching step, a part of the surface on the metal layer side of the predetermined region to be left in the metal foil is covered with the metal layer. Etching is performed on the metal foil.

In another specific configuration of the above manufacturing method, in the element sheet manufacturing step, a plurality of film formation areas and / or thickness dimensions different from each other on the plurality of predetermined regions of the metal foil using the powder spray coating method. The dielectric layer is formed, and then the metal layer is formed on each dielectric layer, thereby producing an element sheet having the plurality of element portions.

The element sheet manufacturing method according to the present invention produces an element sheet having one or more element portions to be one or more capacitor elements in which a dielectric layer is interposed between the first electrode layer and the second electrode layer. And a dielectric layer forming step and a metal layer forming step. Here, in the dielectric layer forming step, a metal foil is used, and a powder spray coating method is performed on one or a plurality of predetermined regions to be the first electrode layer of the one or more capacitor elements in the metal foil. To form a dielectric layer. In the metal layer forming step, a metal layer to be the second electrode layer is formed on the dielectric layer. The element portion of the element sheet includes a predetermined area of the metal foil, a dielectric layer formed on the predetermined area, and a metal layer formed on the dielectric layer.

Here, the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas. According to the powder spray coating method, a dielectric layer having a desired film formation area and / or a desired thickness dimension can be formed in a predetermined region regardless of whether or not the surface of the metal foil is masked. Is possible. Therefore, even when a dielectric layer is formed on a plurality of predetermined regions of the metal foil, the film formation area and / or thickness dimension of the dielectric layer can be changed for each predetermined region, and the change can be easily performed. Can be done. Further, according to the powder spray coating method, the type of dielectric material sprayed for each predetermined region can be changed, and the change can be easily performed.

The element sheet manufacturing method can be used as an element sheet manufacturing step included in the capacitor-embedded substrate manufacturing method.

In the specific configuration of the element sheet manufacturing method, in the dielectric layer forming step, the film formation area and / or the thickness dimension of each of the plurality of predetermined regions of the metal foil are mutually different using the powder spray coating method. A plurality of different dielectric layers are formed, and the metal layer is formed on each dielectric layer in the metal layer forming step.

According to the manufacturing method of the present invention, it is possible to manufacture a capacitor built-in substrate by mounting a capacitor element having a desired capacitance on a predetermined position on an insulating base material in spite of a simple method. .

FIG. 1 is a cross-sectional view showing a capacitor built-in substrate. FIG. 2 is an enlarged view of a region A shown in FIG. FIG. 3 is a plan view of the capacitor element built in the capacitor built-in substrate as seen from the second electrode layer side. FIG. 4 is a diagram showing impedance characteristics of the capacitor built-in substrate. FIG. 5A is a perspective view used for explaining the dielectric layer forming step of the method for manufacturing a capacitor-embedded substrate, and FIG. 5B is a cross-sectional view taken along the line BB shown in FIG. It is sectional drawing which follows a line. FIG. 6 is a diagram showing a film forming apparatus used in the aerosol deposition method. FIG. 7 is a diagram showing a film forming apparatus used in the powder jet deposition method. FIG. 8 is a perspective view used for explaining the annealing step in the method for manufacturing the capacitor built-in substrate. FIG. 9 is a perspective view used for explaining the resist forming process of the method for manufacturing the capacitor built-in substrate. FIG. 10 is a perspective view used for explaining the plating process of the method for manufacturing the capacitor built-in substrate. FIG. 11 is a plan view showing the state of the second sheet for element formation after execution of the plating step. FIG. 12 is a plan view used for explaining the resist stripping process in the method for manufacturing the capacitor built-in substrate. 13 is a cross-sectional view taken along the line CC shown in FIG. FIG. 14 is a cross-sectional view used for explaining the affixing process of the method for manufacturing a capacitor built-in substrate. FIG. 15 is a cross-sectional view used for explaining the etching process of the method for manufacturing the capacitor built-in substrate. FIG. 16 is a cross-sectional view used for explaining the stacking process of the method for manufacturing the capacitor-embedded substrate. FIG. 17 is a cross-sectional view showing a conventional capacitor built-in substrate. FIG. 18 is a cross-sectional view showing a conventional capacitor mounting board.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an example of a capacitor built-in substrate manufactured by the manufacturing method according to the present invention. As shown in FIG. 1, the substrate with a built-in capacitor includes an insulating substrate (2). The insulating substrate (2) includes a first electrode layer (11), a second electrode layer (12), and a plurality of portions in the insulating substrate (2). A capacitor element (1) having a dielectric layer (13) interposed therebetween is embedded between them, whereby a plurality of capacitor elements (1) are built in the insulating substrate (2).

Each capacitor element (1) is embedded in the insulating substrate (2) in such a posture that the surfaces of both electrode layers (11), (12) are substantially parallel to the surface of the insulating substrate (2). Further, the right side capacitor element (1) in FIG. 1 has a smaller thickness dimension T of the dielectric layer (13) than the left side capacitor element (1). That is, in the present embodiment, a plurality of capacitor elements (1) having different thickness dimensions T of the dielectric layer (13) are embedded in the insulating substrate (2). Here, each dielectric layer (13) is composed of barium titanate (BaTiO3), lithium niobate (LiNbO3), lithium borate (Li2B4O7), lead zirconate titanate (PbZrTiO3), strontium titanate (SrTiO3), titanium It is formed from various dielectric materials mainly composed of lead lanthanum zirconate (PbLaZrTiO3), lithium tantalate (LiTaO3), zinc oxide (ZnO), tantalum oxide (Ta2O5) and the like. The dielectric layer (13) may contain an additive to improve dielectric properties, insulating properties, strength, and the like.

The insulating substrate (2) is formed from a material having flame retardancy, for example, a material of FR-4 (Flame Retardant Type 4). Here, the material of FR-4 is a flame retardant material made of, for example, a composite material of glass fiber and epoxy resin.

The first electrode layer (11) of the capacitor element (1) is formed of a metal foil. Here, the metal foil is formed of a metal material that can form a foil and can be an electrode layer, such as copper (Cu), nickel (Ni), aluminum (Al), platinum (Pt), or the like. . Further, the metal foil can be handled by itself, for example, can hold itself. The thickness dimension of the metal foil is preferably 1 μm or more. In the present embodiment, copper (Cu) is used as the metal material of the metal foil forming the first electrode layer (11).

On the other hand, the second electrode layer (12) of the capacitor element (1) is formed of a metal thin film. Here, the metal thin film is a metal film formed thinly on the surface of the base material such as the dielectric layer (13), and a thin film such as copper (Cu) can be formed and can be an electrode layer. It is formed from a metal material. Therefore, the metal thin film is difficult to handle by itself, and is handled integrally with the base material. The thickness dimension of the metal thin film is preferably 20 μm or less. In the present embodiment, copper (Cu) is used as the metal material of the metal thin film that forms the second electrode layer (12).

FIG. 2 is an enlarged view of area A shown in FIG. FIG. 3 is a plan view of the capacitor element (1) shown in FIG. 2 as viewed from the second electrode layer (12) side. As shown in FIG. 3, the first electrode layer (11) of the capacitor element (1) has a surface (111) on the second electrode layer (12) side (upper surface in FIG. 2; hereinafter referred to as “upper surface”). Is covered with the second electrode layer (12). Specifically, the first electrode layer (11) has a substantially square shape, while the second electrode layer (12) has a substantially square shape having a smaller area than the first electrode layer (11). The second electrode layer (12) covers the central region of the upper surface (111) of the first electrode layer (11).

In the present embodiment (see FIG. 2), the dielectric layer (13) is a region (112) covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). It is not formed on the region (113) formed above and not covered by the second electrode layer (12).

As shown in FIG. 2, a first conductive via (31) and a second conductive via (32) are formed in the insulating substrate (2). The first conductive via (31) is electrically connected to a region (113) not covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). The second conductive via (32) is electrically connected to the surface (121) of the second electrode layer (12) opposite to the first electrode layer (11) (the upper surface in FIG. 2). Connected. The two

conductive vias

31 and 32 are formed on the surface region 21 on the second electrode layer 12 side of the capacitor element 1 in the surface of the insulating substrate 2 (the upper surface in FIG. 2). (Hereinafter referred to as “upper surface”), and the front end portions of both conductive vias (31) and (32) are exposed in the surface region (21). Here, a conductive material such as copper (Cu) is used to form both conductive vias (31) and (32).

In the present embodiment (see FIG. 3), the first conductive is provided at 12 locations on the region (113) not covered by the second electrode layer (12) among the upper surface (111) of the first electrode layer (11). Vias (31) are formed, and second conductive vias (32) are formed at four locations on the upper surface (121) of the second electrode layer (12). (31) and the second conductive vias (32) to (32) are arranged in a 4 × 4 matrix on the paper surface of FIG.

As shown in FIG. 2, a ground terminal (41) and a power supply terminal (42) are formed on the upper surface (21) of the insulating substrate (2). Here, the tip of each first conductive via (31) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected to the ground terminal (41), and the power terminal (42) The tip of each second conductive via (32) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected. Therefore, an electrical path is formed between the ground terminal (41) and the power supply terminal (42) via the capacitor element (1). Of course, the tip of each second conductive via (32) may be connected to the ground terminal (41), and the tip of each first conductive via (31) may be connected to the power supply terminal (42).

In the capacitor built-in substrate, a region (113) not covered with the second electrode layer (12) is formed on the upper surface (111) of the first electrode layer (11), and a plurality of regions (113) are formed in the region (113). The first conductive vias (31) to (31) are electrically connected. Accordingly, each first conductive via (31) extends toward the upper surface (21) of the insulating substrate (2) without being in electrical contact with the second electrode layer (12), and is formed on the upper surface (21). The front end portion of the first conductive via (31) can be exposed. Therefore, the conductive via to be electrically connected to the conventional capacitor-embedded substrate, specifically the first electrode layer (11), is the first electrode of the capacitor element (1) in the surface of the insulating substrate (2). The capacitor built-in shown in FIG. 2 as compared to the capacitor built-in substrate (see FIG. 17) routed to the surface region (22) on the layer (11) side (the lower surface in FIG. 2; hereinafter referred to as “lower surface”). In the substrate, the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced. This improves the impedance characteristics of the capacitor built-in substrate in the high frequency region.

The inventor of the present application has confirmed by simulation that the impedance characteristics in the high frequency region of the capacitor built-in substrate shown in FIG. 2 are improved. FIG. 4 is a graph (91) showing the impedance characteristics obtained by simulation for the capacitor built-in substrate shown in FIG.

In FIG. 4, as shown in FIG. 18, the impedance characteristic of the conventional capacitor mounting board is also shown by a graph (92). Here, in the conventional capacitor mounting substrate, as shown in FIG. 18, a pair of conductive vias (314) (315) penetrating from the upper surface (305) to the lower surface (311) at a plurality of locations on the insulating substrate (304). ) And a chip-like capacitor element (316) is mounted on the lower surface (311) of the insulating substrate (304). As a result, an electrical path is formed between the power supply terminal (306) and the ground terminal (307) formed on the upper surface (305) of the insulating substrate (304) via the capacitor element (316). Yes.

By comparing the two graphs (91) and (92) shown in FIG. 4, it can be seen that the impedance characteristics in the high frequency region are improved in the capacitor built-in substrate shown in FIG.

Next, a method for manufacturing the capacitor built-in substrate will be specifically described with reference to the drawings. In the manufacturing method, the element sheet manufacturing process, the attaching process, the etching process, and the laminating process are executed in this order. In the element sheet manufacturing process, a dielectric layer forming process, an annealing process, a resist forming process, a plating process, and a resist stripping process are executed in this order.

FIG. 5 (a) is a perspective view used for explaining the dielectric layer forming step, and FIG. 5 (b) is a cross-sectional view taken along the line BB shown in FIG. 5 (a). As shown in FIGS. 5A and 5B, in the dielectric layer forming step, first, a metal foil (50) is prepared, and the surface (501) of the metal foil (50), specifically, the A dielectric layer (13) is formed on the predetermined region (54) to be the first electrode layer (11) of each capacitor element (1) in the metal foil (50) by using a powder spray coating method. At this time, the dielectric layer (13) is formed on each predetermined region (54) so as to cover a part of the predetermined region (54). Thereby, the first sheet for element formation (61) in which a plurality of dielectric layers (13) are formed on the surface (501) of the metal foil (50) is formed. A film forming apparatus (7) is used for forming the dielectric layer (13).

In the present embodiment (see FIG. 5 (a)), predetermined regions (54) are set in 11 locations of one metal foil (50) formed of copper (Cu), and each predetermined region (54) is set on each predetermined region (54). A dielectric layer (13) having a square shape is formed using a powder spray coating method. At this time, the dielectric layer (13) is formed on each predetermined region (54) so as to cover the central portion of the predetermined region (54).

Here, the powder spray coating method is a film forming method in which a thin film is formed on a target by spraying various powders mixed with the gas onto the target using the flow of the gas. The powder spray coating method includes various film forming methods such as an aerosol deposition method and a powder jet deposition method.

FIG. 6 is a view showing a film forming apparatus (7) used in the aerosol deposition method. As shown in FIG. 6, the film forming apparatus (7) maintains the inside in a vacuum state by an aerosol generator (71) that stirs and mixes powder with high-pressure gas to form an aerosol, and a vacuum pump (73). The film forming chamber (72) that can be connected is connected by a thin transfer tube (74). During film formation, the inside of the film formation chamber (72) is maintained in a vacuum state, whereby the space (high pressure space) in the aerosol generator (71) into which the high pressure gas flows and the film formation chamber (72) There will be a pressure difference between this space (low pressure space). Accordingly, the powder aerosolized by the aerosol generator (71) flows in the transfer tube (74) toward the film forming chamber (72).

Inside the film formation chamber (72), a stage (75) for installing a target having a surface on which a thin film is to be formed is provided, and the stage (75) is an installation surface on which the target is installed ( 751), a translation in the XY plane, translation in the Z-axis direction perpendicular to the XY plane, and rotation around the Z-axis are possible.

One end of the transfer tube (74) is disposed in the film forming chamber (72), and at one end, a slit-like nozzle (76) is attached with its tip directed toward the installation surface (751) of the stage (75). It has been. The nozzle (76) has a shape capable of accelerating the powder discharged from one end of the transfer tube (74) to about 100 m / sec.

Therefore, the powder discharged at high speed from the tip of the nozzle (76) is sprayed onto the surface of the target on the stage (75).

FIG. 7 is a view showing a film forming apparatus (7) used in the powder jet deposition method. As shown in FIG. 7, the film forming apparatus (7) includes a stepped nozzle (81) having two regions (811) and (812) having different inner diameters, and the nozzle (81) has an inner diameter. A through hole (82) for supplying powder is formed at a position close to the second region (812) having a small inner diameter in the large first region (811).

Therefore, by flowing compressed gas from the second region (812) toward the first region (811) in the nozzle (81), negative pressure is generated at a position near the outlet of the second region (812) where the inner diameter changes. A pressure is generated, and the powder is sucked into the nozzle (81) by the negative pressure. As a result, the sucked powder is discharged from the tip (813) of the nozzle (81) at a high speed together with the compressed gas.

The discharged powder is sprayed onto the surface of the target on the stage (75) as in the film forming apparatus (FIG. 6) used in the aerosol deposition method.

In the dielectric layer forming step, the powdery dielectric material is sprayed onto the predetermined region (54) of the metal foil (50) using the powder spray coating method. Thereby, the powdery dielectric material collides with the predetermined region (54) and is crushed, and the powdery dielectric material collides with and crushes on the predetermined region (54). A fine dielectric material is densely deposited on each predetermined region (54) of the metal foil (50) to form a dielectric layer (13).

According to the above powder spray coating method, as shown in FIGS. 5 (a) and 5 (b), each predetermined region (54) is desired without masking the surface (501) of the metal foil (50). It is possible to form a dielectric layer (13) having a thickness dimension T of. Specifically, the thickness dimension T of the dielectric layer (13) can be easily changed by adjusting the number of scans, scan speed, discharge speed, etc. of the film forming apparatus (7). Accordingly, even when the dielectric layer (13) is formed on the plurality of predetermined regions (54) of the metal foil (50), the dielectric layer (13) is provided for each predetermined region (54) as shown in FIG. The thickness dimension T can be changed, and the change can be easily performed. Further, according to the above-described powder spray coating method, the type of dielectric material sprayed for each predetermined region (54) can be changed, and the change can be easily performed.

In the dielectric layer forming step, masking may be performed on a region different from the region on each predetermined region (54) in the surface (501) of the metal foil (50). Even in this case, it is possible to form the dielectric layer (13) having a desired thickness dimension T on each predetermined region (54) by using the powder spray coating method. Further, on the plurality of predetermined regions (54) of the metal foil (50), not only the plurality of dielectric layers (13) having different thickness dimensions T but also the film forming areas and / or thickness dimensions T are different from each other. A plurality of dielectric layers (13) may be formed.

FIG. 8 is a perspective view used for explaining the annealing process. As shown in FIG. 8, in the annealing step, each dielectric layer (13) is irradiated with a laser, thereby annealing the dielectric layer (13). Thereby, the characteristics of the dielectric layer (13) can be further improved. The annealing step is not an essential step in the method for manufacturing a capacitor-embedded substrate according to the present invention, and the annealing step may be performed only when the characteristics of the dielectric layer (13) are further improved. In addition to the laser irradiation, annealing may be performed by a method such as microwave heating, heating in the atmosphere or nitrogen atmosphere (using a furnace or the like), or the like.

FIG. 9 is a perspective view used for explaining the resist formation process. As shown in FIG. 9, in the resist forming step, a masking process is performed on the first element forming sheet (61). Specifically, a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next. In the present embodiment, in order to deposit the plating only on the surface (131) of the dielectric layer (13) in the plating step, the dielectric layer (13 The resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.

FIG. 10 is a perspective view used for explaining the plating process. As shown in FIG. 10, in the plating process, the element forming second sheet (62) is subjected to electroless plating by immersing the element forming second sheet (62) in a plating solution (9). As a result, as shown in FIG. 11, a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) is formed on each dielectric layer (13). In the present embodiment, copper (Cu) is used as the metal material for the electroless plating process. In addition to the plating process, the metal thin film (53) can be formed by a sputtering method, a vapor deposition method, a screen printing method, an ink jet method, or the like.

FIG. 12 is a plan view used for explaining the resist stripping process. FIG. 13 is a cross-sectional view taken along the line CC shown in FIG. As shown in FIGS. 12 and 13, in the resist stripping step, the resist (52) (see FIG. 11) formed on the surface (501) of the metal foil (50) is stripped to remove the metal foil (50). The resist (52) is removed from the surface (501). Thus, each predetermined region (54) of the metal foil (50), the dielectric layer (13) formed on the predetermined region (54), and the metal thin film formed on the dielectric layer (13) An element sheet (6) having a plurality of element parts (5) consisting of (53) is formed. For removing the resist (52), for example, a chemical method can be used.

FIG. 14 is a cross-sectional view used for explaining the pasting process. As shown in FIG. 14, in the pasting process, the surface of one insulating base material (20) of the two insulating base materials (20), (20) (see FIG. 16) constituting the insulating substrate (2) is applied. The element sheet (6) is pasted.

FIG. 15 is a cross-sectional view used for explaining the etching process. As shown in FIG. 15, in the etching step, pattern etching is performed on the metal foil (50) (see FIG. 14) of the element sheet (6) to thereby form each predetermined region set in the metal foil (50) (see FIG. 15). 54) is left on the insulating substrate (20).

Here, on each predetermined region (54), a dielectric layer (13) is formed at the center of the predetermined region (54), and a metal thin film (53) is formed on the dielectric layer (13). ing. Accordingly, each predetermined region (54) left on the insulating base (20) is a part of the surface on the metal thin film (53) side, specifically, the central region on the surface on the metal thin film (53) side. It will be covered by the metal thin film (53). In other words, in the etching process, a part of the surface on the metal thin film (53) side of the predetermined region (54) to be left out of the metal foil (50) is covered with the metal thin film (53). Similarly, pattern etching is performed on the metal foil (50).

By performing the etching process, the plurality of element portions (5) of the element sheet (6) are left at predetermined positions on the insulating base (20), and as a result, each element left on the insulating base (20). The capacitor element (1) is formed from the portion (5). Specifically, a predetermined region (54) of the metal foil (50) left on the insulating substrate (20) in each element part (5) becomes the first electrode layer (11) of the capacitor element (1). The metal thin film (53) formed on the predetermined region (54) becomes the second electrode layer (12) of the capacitor element (1). As a result, a dielectric is formed between the electrode layers (11) and (12). The capacitor element (1) with the layer (13) interposed is formed.

Thereby, each capacitor element (1) is mounted at a predetermined position on the insulating substrate (20). Further, in the present embodiment, as shown in FIG. 15, the right-side capacitor element (1) and the left-side capacitor element (1) have different thickness dimensions T of the dielectric layer (13). The capacitor elements (1) have different capacitances.

As shown in FIG. 15, in the etching process of the present embodiment, by performing pattern etching on the metal foil (50), in addition to the first electrode layer (11) of the capacitor element (1), the insulating substrate (2) An electrode pattern (55) such as a power supply pattern and a ground pattern to be formed therein is also formed.

FIG. 16 is a cross-sectional view used for explaining the lamination process. As shown in FIG. 16, in the laminating step, another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20). Thereby, the insulating substrate (2) is formed by the two insulating base materials (20) laminated.

Thereafter, as shown in FIG. 2, a first conductive via (31) and a second conductive via (32) corresponding to each capacitor element (1) are formed on the insulating substrate (2), and the insulating substrate (2). A ground terminal (41) and a power supply terminal (42) corresponding to each capacitor element (1) are formed on the upper surface (21). As a result, the capacitor built-in substrate is completed.

In the above manufacturing method, the dielectric layer (13) is formed using a powder spray coating method. Here, according to the powder spray coating method, as described above, even when the dielectric layer (13) is formed on the plurality of predetermined regions (54) of the metal foil (50), as shown in FIG. As described above, the film formation area and / or the thickness dimension T of the dielectric layer (13) can be changed for each predetermined region (54), and the change can be easily performed. Further, according to the powder spray coating method, the type of the dielectric material sprayed for each predetermined region (54) can be changed, and the change can be easily performed.

Therefore, according to the above manufacturing method, although it is a simple method, the capacitor element (1) having a desired capacitance can be mounted at a predetermined position on the insulating substrate (20). . Therefore, even when the design related to the capacitance of the capacitor element (1) is changed, the type of the dielectric material constituting the dielectric layer (13), the film formation area of the dielectric layer, and the dielectric layer (13) It is only necessary to change at least one of the thickness dimensions T, and it is not necessary to redesign the arrangement of the capacitor element (1). In addition, the dielectric layer (13) can be formed without masking the metal foil (50), and therefore the yield of the capacitor built-in substrate can be improved.

Further, the capacitor element (1) mounted on the insulating substrate (20) in the above manufacturing method has a small thickness and is in the form of a sheet. Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the process of mounting the capacitor elements (1) on the insulating base material (20) becomes complicated.

According to the above manufacturing method, the capacitor element (1) is formed by performing the etching process, and the capacitor element (1) is handled as the element sheet (6) until the etching process is performed. Therefore, it is not necessary to handle the capacitor elements (1) individually, and the process of mounting the capacitor elements on the insulating substrate (20) is simplified.

Further, in the above manufacturing method, before the metal foil (50) is attached to the insulating base (20), the dielectric layer (13) constituting the capacitor element (1) is formed on the metal foil (50). And the element thin film (53) is formed, and the element sheet | seat (6) is produced. Therefore, it is not necessary to form the dielectric layer (13) and the metal thin film (53) on the insulating substrate (20). Therefore, there is no possibility that the dielectric material or the metal material for forming the dielectric layer (13) and the metal thin film (53) is mixed into another component such as the insulating base (20). Further, even when it is necessary to perform a heat treatment, specifically, the above-described annealing step, in order to form the capacitor element (1), there is no possibility that another component is adversely affected by the heat treatment.

In addition, it is preferable that the thickness dimension of the capacitor | condenser element (1) used for preparation of the said board | substrate with a built-in capacitor exists in the range of 5 micrometers or more and 100 micrometers or less. This is because, when the thickness is smaller than 5 μm, handling of the element sheet (6) becomes difficult and problems such as an increase in resistance occur. Further, when the thickness dimension is larger than 100 μm, the thickness of the capacitor element (1) affects the surface of the insulating base material (20), so that irregularities are formed on the surface of the insulating base material (20). This is because it becomes difficult to laminate another insulating base material (20) thereon.

The configuration of each part of the present invention is not limited to the above-described embodiment, and various modifications can be made within the technical scope described in the claims. For example, the above manufacturing method can also be applied to the manufacture of a capacitor built-in substrate in which the capacitor element (1) is embedded only at one location in the insulating substrate (2). In the etching step, only the first electrode layer (11) constituting the capacitor element (1) may be formed from the metal foil (50) without forming the electrode pattern (55).

Furthermore, in the capacitor built-in substrate, the second electrode layer (12) of the capacitor element (1) may be formed of a metal foil. Further, the shape of the first electrode layer (11) and the second electrode layer (12) of the capacitor element (1) is not limited to a substantially square shape, but the first electrode layer (11) and the second electrode layer (12). ) Various shapes can be used.

(1) Capacitor element
(11) First electrode layer
(12) Second electrode layer
(13) Dielectric layer
(2) Insulating substrate
(20) Insulating substrate
(31) First conductive via
(32) Second conductive via
(41) Ground terminal
(42) Power supply terminal
(5) Element section
(50) Metal foil
(53) Metal thin film (metal layer)
(54) Predetermined area
(6) Element sheet
(7) Deposition system

Claims

One or a plurality of capacitor elements having a dielectric layer interposed between the first electrode layer and the second electrode layer, and an insulating substrate, and by embedding the capacitor element in the insulating substrate, a capacitor is provided on the insulating substrate. A method of manufacturing a capacitor-embedded substrate with a built-in element,
Using a metal foil, a dielectric layer is formed on the one or more predetermined regions to be the first electrode layer of the one or more capacitor elements by using a powder spray coating method. Forming a metal layer to be the second electrode layer on the dielectric layer, thereby forming a predetermined region of the metal foil, a dielectric layer formed on the predetermined region, and the dielectric layer; An element sheet manufacturing step of manufacturing an element sheet having one or a plurality of element portions made of the formed metal layer;
An affixing step of affixing the element sheet on one insulating base material of two insulating base materials constituting the insulating substrate;
Etching the metal foil to leave the one or more predetermined regions on the one insulating substrate, thereby forming the one or more element portions of the element sheet on the one insulating substrate. An etching step of forming one or more capacitor elements;
A method of manufacturing a capacitor built-in substrate, comprising: a step of forming the insulating substrate by laminating the other insulating substrate on the one insulating substrate.
In the etching step, the metal foil is etched so that a part of the metal layer side surface of the predetermined region to be left out of the metal foil is covered with the metal layer. The manufacturing method of the board | substrate with a built-in capacitor | condenser of Claim 1.
In the element sheet manufacturing step, a plurality of dielectric layers having different film formation areas and / or thickness dimensions are formed on the plurality of predetermined regions of the metal foil using the powder spray coating method,
The method for manufacturing a capacitor built-in substrate according to claim 1, wherein an element sheet having the plurality of element portions is formed by forming the metal layer on each dielectric layer.
A method for producing an element sheet having one or a plurality of element portions to be one or a plurality of capacitor elements in which a dielectric layer is interposed between a first electrode layer and a second electrode layer,
A dielectric using a metal foil to form a dielectric layer on the one or more predetermined regions to be the first electrode layer of the one or more capacitor elements by using a powder spray coating method. A layer forming step;
A metal layer forming step of forming a metal layer to be the second electrode layer on the dielectric layer, and the element portion of the element sheet is formed on a predetermined area of the metal foil and on the predetermined area. A device sheet manufacturing method comprising: a dielectric layer; and a metal layer formed on the dielectric layer.
In the dielectric layer forming step, a plurality of dielectric layers having different film formation areas and / or thickness dimensions are formed on a plurality of predetermined regions of the metal foil using the powder spray coating method, The element sheet manufacturing method according to claim 4, wherein in the layer forming step, the metal layer is formed on each dielectric layer.