WO2011096545A1 - 過電流保護装置及び過電流保護システム - Google Patents
過電流保護装置及び過電流保護システム Download PDFInfo
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- WO2011096545A1 WO2011096545A1 PCT/JP2011/052434 JP2011052434W WO2011096545A1 WO 2011096545 A1 WO2011096545 A1 WO 2011096545A1 JP 2011052434 W JP2011052434 W JP 2011052434W WO 2011096545 A1 WO2011096545 A1 WO 2011096545A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/06—Details with automatic reconnection
- H02H3/07—Details with automatic reconnection and with permanent disconnection after a predetermined number of reconnection cycles
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/087—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current for dc applications
Definitions
- the present invention is provided with a plurality of systems, and when an overcurrent flows through a load driving circuit including a load, an electronic switch, and an electric wire, the electronic switch of the load driving circuit serving as an overcurrent generation source is interrupted.
- the present invention relates to an electronic switch provided in a circuit for driving a load, an overcurrent protection device for protecting an electric wire, and an overcurrent protection system.
- a load such as a lamp or a motor mounted on a vehicle is connected to a battery via an electronic switch (for example, a MOSFET), and its driving and stopping are controlled by switching on and off of the electronic switch.
- an electronic switch for example, a MOSFET
- the load and the harness for connection may be damaged by heat generation.
- the electronic switch is quickly shut off to protect the electronic switch and the electric wire provided in the circuit from the overcurrent (for example, Patent Documents) 1).
- the timing for turning on each electronic switch is controlled so as to have a time difference (so that each electronic switch does not turn on at the same time), and the inrush current flowing through each load driving circuit is reduced. It has been shown to avoid overlapping. That is, when the retry operation is executed, the electronic switches are not turned on at the same time, but are turned on with a time difference to identify the circuit in which the dead short has occurred.
- Patent Document 1 does not take into account the case where the power supply voltage is significantly lowered and the operational amplifier does not operate normally, such as when a dead short occurs.
- a single overcurrent protection device is used to control the electronic switches of a plurality of load driving circuits, and when an overcurrent occurs, the electronic switches of each circuit are shut off. Since the electronic switch provided in the circuit and the electric wire connected thereto are protected, a time difference can be given to the timing when each electronic switch is turned on during the retry operation. Therefore, it is possible to easily determine the circuit in which the dead short has occurred.
- each overcurrent protection device is provided for one or two load driving circuits, and each overcurrent protection device individually detects the occurrence of overcurrent and performs overcurrent protection. In such a case, it is not easy to give a time difference to the timing of turning on the electronic switch of each circuit when executing the retry operation.
- each electronic switch has the same timing (time difference In such a case, when back electromotive force is generated at the same time as the electronic switch is turned on, it is impossible to determine which circuit is the cause. Had occurred.
- the present invention has been made to solve such a conventional problem, and an object of the present invention is to execute a retry operation between a plurality of overcurrent protection devices connected to the same power source. It is an object of the present invention to provide an overcurrent protection device and an overcurrent protection system that can have a time difference.
- an overcurrent protection device for protecting a DC power source and a load driving circuit having an electronic switch, an electric wire, and a load from the overcurrent.
- Voltage detecting means for detecting the output voltage (VBA) of the power supply, timing means for measuring the elapsed time after the electronic switch is turned on, and when the output voltage of the DC power supply falls below a preset threshold voltage
- a switch control means for turning off the electronic switch and turning on the electronic switch again after a predetermined standby time has elapsed; and when the output voltage drops below the threshold voltage and the electronic switch is turned off. And when the electronic switch is turned on, the output voltage of the DC power supply is set to the threshold voltage.
- a count unit that counts the number of occurrences when the time required for the decrease is equal to or less than a preset threshold time (for example, 400 ⁇ sec), and the switch control unit has a count value by the count unit.
- a preset threshold time for example, 400 ⁇ sec
- the counting means resets the count value when the next count does not occur until the first predetermined time has elapsed after the occurrence count is counted. To do.
- the switch control means increases the output voltage to the threshold voltage after the output voltage of the DC power supply has dropped below the threshold voltage to turn off the electronic switch. The elapsed time is counted from the time point.
- An overcurrent protection system is a drive control circuit comprising a plurality of load driving circuits having electronic switches, electric wires and loads, and a single DC power source connected to each of the load driving circuits.
- each of the load driving circuits has an overcurrent protection device
- the overcurrent protection device provided in one load driving circuit includes: Voltage detecting means for detecting an output voltage (VBA) of the DC power supply, time measuring means for measuring an elapsed time after turning on an electronic switch of the one load driving circuit, and an output voltage of the DC power supply
- Switch control means for turning off the electronic switch of one load driving circuit when the voltage drops below a preset threshold voltage, and turning on the electronic switch again after a predetermined standby time has elapsed; When the output voltage drops below the threshold voltage and the electronic switch of the one load driving circuit is turned off, the predetermined waiting time is provided in another load driving circuit.
- Waiting time determining means for determining to be different from the waiting time of the overcurrent protection device, and from turning on the electronic switch of the one load driving circuit, until the output voltage of the DC power supply drops to the threshold voltage
- a count means for counting the number of occurrences when the required time is equal to or less than a preset threshold time (for example, 400 ⁇ sec), and the switch control means has a count value by the count means as a predetermined count.
- a threshold value for example, 7 times
- the counting means of the circuit for driving one load does not generate the next count until the first predetermined time elapses after the occurrence count is counted.
- the count value is reset.
- the switch control means increases the output voltage to the threshold voltage after the output voltage of the DC power supply has dropped below the threshold voltage to turn off the electronic switch. The elapsed time is counted from the time point.
- the electronic switch when the output voltage of the DC power source is detected by the voltage detection means and the detected output voltage falls below a threshold voltage (for example, 3.3 V), the electronic switch is turned off, and then randomly The operation of turning on the electronic switch is repeated after a predetermined waiting time has elapsed.
- a threshold voltage for example, 3.3 V
- the electronic switch is turned off, and then randomly The operation of turning on the electronic switch is repeated after a predetermined waiting time has elapsed.
- the threshold time for example, 400 ⁇ sec
- the number of times is counted, and the count value becomes the count threshold (for example, 7
- the electronic switch is kept in the off state. Therefore, when a dead short circuit occurs in the load driving circuit, this can be detected promptly and the circuit can be kept off, and the electronic switch and the electric wire provided in the circuit are protected from heat generation due to the dead short circuit. be able to.
- the standby time is randomly determined, when a plurality of overcurrent protection devices are connected in parallel to one DC power supply, a dead short occurs in one circuit.
- the output voltage of the DC power supply decreases, other overcurrent protection devices turn off the electronic switch, but when the standby time has passed and the power switch is turned on again, the output voltage of the DC power supply falls within the threshold time thereafter. Does not drop below the threshold voltage, the count value is not incremented and the count threshold is not reached. Therefore, it is possible to continuously drive a circuit in which no dead short occurs.
- the count value if the count value does not reach the count threshold before the first predetermined time elapses, the count value is reset, so that the output voltage is set to the threshold for reasons other than dead short.
- the voltage is lower than the voltage, it is possible to prevent erroneous disconnection of the load driving circuit.
- the waiting time is started to be counted. It is possible to accurately determine the time for starting the time measurement.
- the output voltage of the DC power supply is detected by the voltage detection means of the overvoltage protection device connected to the circuit for driving one load, and the detected output voltage is less than the threshold voltage (for example, 3.3 V).
- the threshold voltage for example, 3.3 V.
- the electronic switch of one load driving circuit is turned off, and thereafter, the operation of turning on the electronic switch is repeated after a standby time randomly determined for each overcurrent protection device has elapsed.
- the required time from when the electronic switch of one load driving circuit is turned on until the output voltage drops below the threshold voltage is less than the threshold time (for example, 400 ⁇ sec), this number is counted.
- the electronic switch of one load driving circuit is held in the OFF state. Therefore, when a dead short circuit occurs in one load driving circuit, this can be detected quickly and the circuit can be kept in an off state, and the electronic switch and electric wire provided in the circuit can generate heat due to the dead short circuit. Can be protected from.
- the standby time is randomly determined for each overcurrent protection device, when a dead short occurs in one load driving circuit and the output voltage of the common DC power supply decreases, In other overcurrent protection devices, the electronic switch is turned off, but when the standby time is turned on and turned on again, the output voltage of the DC power supply does not drop below the threshold voltage within the threshold time thereafter. Is not incremented and the count threshold is not reached. Therefore, it is possible to continuously drive a circuit in which no dead short occurs.
- the overcurrent protection device provided in the circuit for driving one load, if the count value does not reach the count threshold before the first predetermined time elapses, Since the count value is reset, it is possible to prevent the circuit from being erroneously shut down when the output voltage is equal to or lower than the threshold voltage for reasons other than dead short.
- FIG. 1 is a circuit diagram showing a configuration of an overcurrent protection system in which a plurality of overcurrent protection devices according to an embodiment of the present invention are connected.
- 1 is a circuit diagram of an overcurrent protection device according to an embodiment of the present invention and a load driving circuit to which the overcurrent protection device is connected.
- FIG. 3 is a first partial view of a flowchart showing a processing operation of the overcurrent protection device according to the embodiment of the present invention. It is a 2nd division figure of the flowchart which shows the processing operation of the overcurrent protection apparatus which concerns on one Embodiment of this invention.
- FIG. 1 It is a timing chart which shows the relationship between the voltage which determines with the overcurrent immediately after turning on an electronic switch, and elapsed time of the overcurrent protection apparatus which concerns on one Embodiment of this invention. It is a timing chart which shows the relationship between the voltage determined to be an overcurrent, and elapsed time of the overcurrent protection apparatus which concerns on one Embodiment of this invention. It is a timing chart which shows the relationship between the voltage determined to be an overcurrent, and elapsed time of the overcurrent protection apparatus which concerns on one Embodiment of this invention. It is a characteristic view which shows the fluctuation
- FIG. 5 is a characteristic diagram showing a relationship between a change in load current and a reference voltage Vref1 and a double voltage Vref2 when driving a horn mounted on a vehicle.
- FIG. 5 is a characteristic diagram showing a relationship between a change in load current and a reference voltage Vref1 and a double voltage Vref2 when driving a horn mounted on a vehicle.
- FIG. 6 is a characteristic diagram showing a relationship between a change in load current and a reference voltage Vref1 when driving a horn mounted on a vehicle. It is a flowchart which shows the processing operation of the VBA monitor circuit of the overcurrent protection apparatus which concerns on one Embodiment of this invention.
- FIG. 5 is a characteristic diagram showing a relationship between a change in load current and a reference voltage Vref1 and a double voltage Vref2 when driving a horn mounted on a vehicle.
- FIG. 5 is a characteristic diagram showing a relationship between a change in load current and a reference
- FIG. 13A is a timing chart showing changes in the output signal of the VBA monitor circuit in each overcurrent protection device according to an embodiment of the present invention
- FIG. 13A is a characteristic diagram showing changes in the output voltage VBA of the battery VB
- 13B shows a change in the signal input to the VBA monitor circuit 15 provided in the IC circuit 51-1 (CH 1)
- FIG. 13C shows a change in the output signal
- FIG. 13D shows the IC circuit 51.
- -2 (CH2) shows a change in the output signal of the VBA monitor circuit 15 provided in FIG. 13
- FIG. 13 (e) shows a change in the output signal of the VBA monitor circuit 15 provided in the IC circuit 51-3.
- It is a block diagram which shows the detailed structure of the VBA monitor circuit of each overcurrent protection apparatus which concerns on one Embodiment of this invention.
- FIG. 1 is a configuration diagram of an overcurrent protection system according to an embodiment of the present invention.
- loads RL for load driving for driving loads RL (RL1 to RL3) such as lamps, motors, and horns mounted on a vehicle.
- an electronic switch Q1a provided in the circuit by cutting off the load driving circuit when an overcurrent flows, and the circuit (VB, Q1a, RL1 and the circuit connecting the wires) It has a function to protect electric wires from overheating.
- this embodiment demonstrates the protection system which protects the circuit for load drive of 3 systems as an example, this invention is not limited to 3 systems.
- this overcurrent protection system includes three IC circuits 51-1 to 51-3, and each of the IC circuits 51-1 to 51-3 includes a terminal D1 and a large current fuse Fu. Is connected to a battery (DC power supply) VB. Each IC circuit 51-1 to 51-3 is connected to a load RL (RL1 to RL3) via terminals D5 to D7, and controls driving and stopping of each load RL.
- the IC circuits 51-1 to 51-3 are connected to terminals D2 to D4 via input I / Fs 54 to 56, and drive signals are input from the terminals D2 to D4.
- FIG. 2 is a circuit diagram showing a detailed configuration of the IC circuit 51-1 shown in FIG. Since the three IC circuits 51-1 to 51-3 have the same configuration, the configuration of the IC circuit 51-1 will be described below.
- the IC circuit 51-1 is roughly divided into an overcurrent protection device 100 and a multi-source FET (Q1; hereinafter simply referred to as “FET” (Q1)).
- FET multi-source FET
- an N-type MOSFET is used as the FET (Q1), but a P-type MOSFET can also be used.
- the FET (Q1) is provided between the battery VB connected via the terminal D1 and the load RL1 connected via the terminal D5.
- a sub-FET (Q1b; hereinafter simply referred to as “FET (Q1b)”) which is a multi-source MOSFET having a common drain and gate. Then, the driving and stopping of the load RL1 are controlled by switching the FET (Q1a) on and off.
- the overcurrent protection device 100 has an AND circuit AND1 and a buffer 11 connected to the output terminal of the AND circuit AND1, and the output terminal of the buffer 11 is connected to the gate of the FET (Q1).
- a charge pump 13 is connected to the buffer 11.
- one input terminal of the AND circuit AND1 is connected to the terminal D2, and the other input terminal is connected to the Q output of the flip-flop circuit 12. Therefore, when an H level signal is supplied to the terminal D2, since the output signal of the flip-flop circuit 12 is normally at the H level, the output signal of the AND circuit AND1 becomes the H level. Since a predetermined level voltage is applied to the H level signal and supplied to the gate of the FET (Q1), the FET (Q1) is turned on, and the load RL1 can be driven.
- the overcurrent protection device 100 also includes an amplifier AMP1, the negative input terminal of the amplifier AMP1 is connected to the source (voltage Vs) of the FET (Q1a), and the positive input terminal is the source of the FET (Q1b). It is connected to the.
- the output terminal of the amplifier AMP1 is connected to the gate of the N-type MOSFET (Q2), the drain of the MOSFET (Q2) is connected to the source of the FET (Q1b), and the source of the MOSFET (Q2) is the current detection resistor Ris.
- the other end of the current detection resistor Ris is connected to the ground. Therefore, a voltage proportional to the load current I0 (hereinafter referred to as “reference voltage Vp”) is generated at one end of the current detection resistor Ris.
- the overcurrent protection device 100 includes five comparators CMP1 to CMP5.
- the comparator CMP5 has a positive input terminal connected to the power supply Vtf and a negative input terminal FET (Q1a). Connected to the source. Therefore, when the drain-source voltage (VB-Vs) of the FET (Q1a) exceeds the output voltage of the power supply Vtf, the output signal of the comparator CMP5 changes from L level to H level. This output signal is output to the Vds detection circuit 16 and the on-failure detection circuit 17, respectively.
- the four comparators CMP1 to CMP4 are provided for outputting a determination result corresponding to the degree of overcurrent flowing in the load driving circuit.
- the plus side input terminals of the comparators CMP2 to CMP4 are MOSFETs.
- the positive input terminal of the comparator CMP1 is connected to the source of the MOSFET (Q2) via the resistor Rcf.
- the plus side input terminal of the comparator CMP1 is connected to one end of the capacitor Cf, and the other end of the capacitor Cf is connected to the ground. Accordingly, a time constant circuit is formed by the resistor Rcf and the capacitor Cf, and the above-described reference voltage Vp is smoothed by the time constant circuit to generate the low-speed following voltage Vc. Further, when connecting a load that does not require the low-speed following voltage Vc, the capacitor Cf is not connected.
- the output terminal of the comparator CMP1 and the output terminal of the comparator CMP2 are connected to the input terminal of the OR circuit OR1.
- a preset reference voltage Vref1 is supplied to the minus side input terminal of the comparator CMP1, and a double voltage Vref2 that is twice the reference voltage Vref1 is supplied to the minus side input terminal of the comparator CMP2.
- a quadruple voltage Vref4 obtained by quadrupling the reference voltage Vref1 is supplied to the negative side input terminal of the comparator CMP3, and an eighth voltage Vref8 obtained by multiplying the reference voltage Vref1 by 8 is supplied to the negative side input terminal of the comparator CMP4. Supplied.
- the output terminal of the OR circuit OR1 is connected to IN-1 of the logic circuit 14, the output terminal of the comparator CMP2 is connected to IN-2 of the logic circuit 14, and the output terminal of the comparator CMP3 is connected to IN of the logic circuit 14. -4, and the output terminal of the comparator CMP4 is connected to IN-8 of the logic circuit 14.
- the logic circuit 14 includes an overvoltage detection signal, a clock signal, and a drive signal for the FET (Q1) input from the terminal D2. Supplied.
- the logic circuit 14 has a timer function (T1 to T4) and a count function (Ct), and when an overcurrent occurs, the duration of the overcurrent and the number of times the overcurrent has occurred. It has a function to count. Further, the output terminal (OUT) of the logic circuit 14 is connected to one of the three input terminals of the OR circuit OR2, and the FET (Q1) when the output signal of the output terminal (OUT) becomes H level. ) Is set to the H level.
- the logic circuit 14 is connected to the oscillator 18, and a clock signal is supplied from the oscillator 18.
- the oscillator 18 is connected to one end of the capacitor Cosc, and the other end is connected to the ground.
- the logic circuit 14 is connected to the overvoltage detector 19, and even if the output voltage VBA of the battery VB (sometimes referred to as battery voltage VBA) becomes an overvoltage and an overcurrent interruption occurs, the voltage of the battery VB If is restored to normal, the circuit for driving the load is released.
- VBA of the battery VB sometimes referred to as battery voltage VBA
- the second input terminal of the OR circuit OR2 is connected to the VBA monitor circuit 15, and the third input terminal is connected to the Vds detection circuit 16.
- the output terminal of the OR circuit OR2 is connected to the reset input terminal of the flip-flop circuit 12.
- the VBA monitor circuit 15 is a circuit that monitors the voltage of the battery VB, and normally drives the IC circuit 51 when the voltage of the battery VB drops below a preset threshold voltage (for example, 3.3 V). Therefore, it outputs a voltage abnormality signal to the reset input of the flip-flop circuit 12, turns off the FET (Q1), and stops driving the load RL1.
- a preset threshold voltage for example, 3.3 V
- the VBA monitor circuit 15 includes a voltage detection means 15a for detecting the battery voltage VBA, a time measurement means 15b for measuring the elapsed time after turning on the FET (Q1), and a battery voltage VBA. Switch that turns off the FET (Q1) when the voltage drops below a preset threshold voltage (eg, 3.3V) and turns on the FET (Q1) again after a predetermined standby time (Tp) has elapsed.
- a preset threshold voltage eg, 3.3V
- Control unit 15c standby time determination unit 15d for randomly determining a predetermined standby time (Tp) when FET (Q1) is turned off when battery voltage VBA falls below a threshold voltage, and FET ( When the required time from when Q1) is turned on until the battery voltage VBA drops below the threshold voltage is below a preset threshold time (eg, 400 ⁇ sec) , And a counting means 15e for counting the number of occurrences.
- Tp standby time
- the Vds detection circuit 16 determines that the drain-source voltage Vds of the FET (Q1) is abnormal, The FET (Q1) is turned off to stop driving the load RL1.
- the on-failure detection circuit 17 determines whether or not the FET (Q1) is on-failed based on the output signal of the comparator CMP5, and outputs an on-failure detection signal when an on-failure occurs.
- the processing from steps S11 to S32 in FIGS. 3 and 4 is an operation at the time of power-on, and the processing from steps S33 to S58 is an operation at a steady state.
- the amplifier AMP1 causes the reference current Ir to flow through the FET (Q1b) so that the source voltage Vs of the FET (Q1a) is equal to the source voltage of the FET (Q1b).
- This reference current Ir has a current proportional to the load current I0. Further, since the reference current Ir flows to the ground via the current detection resistor Ris (Ris ⁇ Rcf), the reference voltage Vp generated in the current detection resistor Ris has a voltage proportional to the load current I0.
- the magnitude of the overcurrent is determined by comparing the reference voltage Vp with the four types of reference voltage Vref1, the double voltage Vref2, the quadruple voltage Vref4, and the eight-fold voltage Vref8. Then, it is determined whether or not to interrupt the load driving circuit according to the magnitude of the overcurrent and the duration.
- the logic circuit 14 activates a T4 timer that measures time T4 (step S12).
- the time T4 is set to, for example, an inrush current generation time (for example, 2 seconds).
- the logic circuit 14 determines whether at least one of the output signal of the comparator CMP1 or the output signal of the comparator CMP2 has become H level. In other words, it is determined whether or not the reference voltage Vp proportional to the load current I0 exceeds the double voltage Vref2, or whether the voltage (slow-speed tracking voltage) Vc obtained by smoothing the reference voltage Vp exceeds the reference voltage Vref1 ( Step S13).
- the determination of step S13 being YES is referred to as “satisfying overcurrent determination”
- the determination being NO is referred to as “not satisfying overcurrent determination”.
- step S13 When the load current I0 does not satisfy the overcurrent determination (when the output signals of the comparators CMP1 and CMP2 are both at the L level) (NO in step S13), the timing of the time T4 by the logic circuit 14 is completed. If time T4 has elapsed (YES in step S14), the process proceeds to step S33 (FIG. 4) described later. If time T4 has not elapsed (NO in step S14), the process returns to step S13.
- step S13 when the load current I0 satisfies the overcurrent determination (when at least one of the output signals of the comparators CMP1 and CMP2 is at the H level) (YES in step S13), an overcurrent is applied to the load driving circuit. Is generated, and a T1 timer for measuring time T1 (T1 ⁇ T4) is activated (step S15).
- the current flowing in the load driving circuit when driving the horn is as shown by a curve q1 in FIG.
- the waveform fluctuates greatly in the vertical direction in a short time, and the reference voltage Vp generated in the current detection resistor Ris also changes like a curve q1.
- the low-speed following voltage Vc obtained by passing through the time constant circuit has a smoothed waveform as shown by the curve q2.
- the reference voltage Vp proportional to the load current I0 is compared with the 8-fold voltage Vref8 (step S16).
- the logic circuit 14 outputs a stop signal (H level signal) to the OR circuit OR2, and the stop The drive signal for the FET (Q1) is turned off by the signal (step S32). That is, when an excessive load current I0 exceeding the 8-fold voltage Vref8 flows to the load driving circuit, the FET (Q1) is immediately cut off to protect the load driving circuit.
- step S17 it is determined whether or not the time T1 has elapsed. That is, if an overcurrent has occurred but the reference voltage Vp corresponding to the overcurrent has not reached the 8-fold voltage Vref8, the FET (Q1) is kept on until the time T1 elapses. continue.
- step S17 the logic circuit 14 determines whether or not the load current I0 satisfies the overcurrent determination (step S18) as in step S13 described above. That is, it is determined whether or not an overcurrent is still occurring after the time T1 has elapsed.
- step S18 If it is determined that the overcurrent determination is not satisfied (NO in step S18), it is determined that the load current I0 has returned to the steady current, and it is determined whether or not the timing of the time T4 by the logic circuit 14 has ended. If it is determined (step S19) and time T4 has elapsed (YES in step S19), the process proceeds to step S33 (FIG. 4). If time T4 has not elapsed (NO in step S19), the process returns to step S18.
- step S18 when it is determined that the load current I0 satisfies the overcurrent determination (YES in step S18), although the reference voltage Vp is lower than the eightfold voltage Vref8, an overcurrent is still generated in the load driving circuit.
- the T2 timer that counts the time T2 (predetermined time; T1 ⁇ T2 ⁇ T4) is activated (step S20).
- the reference voltage Vp and the quadruple voltage Vref4 are compared (step S21).
- the logic circuit 14 turns off the drive signal of the FET (Q1) and shuts off the FET (Q1). (Step S32). That is, even after the FET (Q1) is turned on, if an overcurrent exceeding the quadruple voltage Vref4 continues to flow over the time T1 to the load driving circuit, the FET (Q1 ) To protect the load drive circuit.
- step S22 it is determined whether or not the time T2 has elapsed. That is, when the load current I0 satisfies the overcurrent determination, but the reference voltage Vp corresponding to the overcurrent is not large enough to reach the quadruple voltage Vref4, the FET (Q1) until the time T2 elapses. ) Is kept on.
- the logic circuit 14 determines whether or not the load current I0 satisfies the overcurrent determination (step S23) as in steps S13 and S18 described above. ). That is, after the time (T1 + T2) elapses after the FET (Q1) is turned on, it is determined whether or not an overcurrent is still occurring.
- step S23 If the load current I0 does not satisfy the overcurrent determination (NO in step S23), it is determined that the load current I0 has returned to the steady current, and whether or not the timing of the time T4 by the logic circuit 14 has ended. (Step S24), and if the time T4 has elapsed (YES in step S24), the process proceeds to step S33 (FIG. 4). If time T4 has not elapsed (NO in step S24), the process returns to step S23.
- the load current I0 satisfies the overcurrent determination (YES in step S23)
- step S26 the reference voltage Vp and the double voltage Vref2 are compared.
- the logic circuit 14 turns off the drive signal of the FET (Q1) and blocks the FET (Q1).
- Step S32 That is, when an overcurrent exceeding the double voltage Vref2 continuously flows over the time (T1 + T2) to the load driving circuit, the FET (Q1) is cut off to protect the load driving circuit. To do.
- step S27 it is determined whether or not the time T3 has elapsed (step S27). That is, when an overcurrent has occurred but the reference voltage Vp corresponding to the overcurrent has not reached the double voltage Vref2, the FET (Q1) is kept on until the time T3 elapses. continue.
- Step S27 the logic circuit 14 determines whether or not the load current I0 satisfies the overcurrent determination, as in steps S13, S18, and S23 described above. (Step S28). That is, after the time (T1 + T2 + T3) elapses after the FET (Q1) is turned on, it is determined whether or not an overcurrent is still occurring.
- step S28 If the load current I0 does not satisfy the overcurrent determination (NO in step S28), it is determined that the load current I0 has returned to the steady current, and whether or not the time measurement by the logic circuit 14 has been completed for the time T4 has been completed. (Step S29), and if the time T4 has passed (YES in step S29), the process proceeds to step S33 (FIG. 4). If time T4 has not elapsed (NO in step S29), the process returns to step S28.
- step S32 the FET (Q1) is shut off (step S32). That is, in the processing of steps S26 to S31, when the reference voltage Vp is smaller than the double voltage Vref2 and the load current I0 satisfies the overcurrent determination, that is, only the output signal of the comparator CMP1 becomes H level.
- FIG. 5 is a timing chart showing the change of the reference voltage Vp with time.
- the count value Ct is not reset unless the elapsed time from turning on the FET (Q1) has reached T4. The count value Ct continues to be counted until time t5.
- the FET (Q1) immediately after turning on the FET (Q1), it is determined whether or not the FET (Q1) is turned off according to the magnitude of the load current I0 and its duration, so that the FET (Q1) is turned on.
- the FET (Q1) and the electric wire can be protected by turning off the FET (Q1).
- the logic circuit 14 determines whether or not the load current I0 satisfies the overcurrent determination (in FIG. Step S33). That is, it is determined whether or not an overcurrent has occurred after time T4 has elapsed after the FET (Q1) is turned on.
- step S33 If it is determined that the overcurrent determination is not satisfied (NO in step S33), it is determined that the load current I0 is a steady current, and it is determined whether the T4 timer by the logic circuit 14 is operating. If it is not in operation (step S34), the T4 timer is activated (step S36), and the process returns to step S33. On the other hand, if the T4 timer is operating, it is determined whether or not the time T4 has been counted (step S35), and the process returns to step S33.
- steps S33 to S36 after the time T4 has elapsed since the FET (Q1) was turned on (when the inrush current converges to become a steady current), the T4 timer is operated again and the time T4 is reached. If time measurement is started and no overcurrent occurs (if the NO state is continued in step S33), the processing in steps S33 to S36 is repeated. That is, when the load driving circuit is operating at a steady current, the ON state of the FET (Q1) is maintained by repeating this process.
- the reference voltage Vp proportional to the load current I0 is compared with the quadruple voltage Vref4 (step S38).
- the logic circuit 14 outputs a stop signal to the OR circuit OR2, and the FET (Q1) is output by the stop signal.
- the FET (Q1) is cut off (step S32 in FIG. 3). That is, when an excessive current exceeding the quadruple voltage Vref4 flows in the load driving circuit in a state where the rush current has converged for a while after the FET (Q1) is turned on, the FET immediately (Q1) is cut off to protect the FET (Q1) and the wire.
- step S39 it is determined whether or not the time T5 (predetermined time) has elapsed (step S39). That is, when the load current I0 satisfies the overcurrent determination, but the reference voltage Vp corresponding to the overcurrent is not higher than the quadruple voltage Vref4, the FET (Q1) has the current until the time T5 elapses. Continue to be on.
- step S39 the logic circuit 14 determines whether or not the load current I0 satisfies the overcurrent determination (step S40) as in step S33 described above. . That is, it is determined whether or not an overcurrent still occurs after the time T5 has elapsed.
- step S40 If it is determined that the overcurrent determination is not satisfied (NO in step S40), it is determined that the load current I0 is a steady current, and whether or not the T4 timer by the logic circuit 14 is operating. Judgment is made (step S41), and if not in operation, the T4 timer is activated (step S43), and then the processing returns to step S40. On the other hand, if the T4 timer is operating, it is determined whether or not the time T4 has been counted (step S42). If the time T4 has elapsed (YES in step S42), step S33 is performed. Return to the process. If time T4 has not elapsed (NO in step S42), the process returns to step S40.
- step S46 If the overcurrent determination is not satisfied (NO in step S46), it is determined that the load current I0 is a steady current, and it is determined whether the T4 timer by the logic circuit 14 is operating (step S40). S47) If the timer is not in operation, the T4 timer is activated (step S49), and the process returns to step S46. On the other hand, if the T4 timer is operating (YES in step S47), it is determined whether or not the time T4 has been counted (step S48). If the time T4 has elapsed (step S48). YES), the process returns to step S33. If time T4 has not elapsed (NO in step S48), the process returns to step S46. In this process, even if it is determined that no overcurrent has occurred, the count value Ct is maintained when the time T4 has not elapsed, and the count value Ct is reset when the time T4 has elapsed. Will do.
- the overcurrent that is less than the quadruple voltage Vref4 continues for a time T5, and an overcurrent is generated even if this is repeated twice, the T5 timer is activated again, and the T4 timer is activated. Reset the count value Ct.
- step S51 the reference voltage Vp and the double voltage Vref2 are compared (step S51).
- the logic circuit 14 outputs a stop signal to the OR circuit OR2, and the FET (Q1) is output by the stop signal.
- the FET (Q1) is cut off (step S32 in FIG. 3). That is, when an overcurrent that is less than the quadruple voltage Vref4 continues for two times of time T5 and then an overcurrent that exceeds the double voltage Vref2 is generated, the FET (Q1) Is cut off to protect the FET (Q1) and the electric wire.
- step S52 when it is determined that the reference voltage Vp does not exceed the double voltage Vref2 (NO in step S51), it is determined whether or not the time T5 has elapsed (step S52). That is, when an overcurrent has occurred but the reference voltage Vp corresponding to the overcurrent is less than the double voltage Vref2, the FET (Q1) is kept on until the time T5 elapses. .
- step S52 the logic circuit 14 determines whether or not the load current I0 satisfies the overcurrent determination, as in steps S33, S40, and S46 described above. (Step S53).
- step S53 if the overcurrent determination is not satisfied (NO in step S53), it is determined that the load current I0 is a steady current, and it is determined whether the T4 timer by the logic circuit 14 is operating ( In step S54), if not in operation, the T4 timer is operated (step S56), and then the process returns to step S53.
- step S54 if the T4 timer is operating (YES in step S54), it is determined whether or not the time T4 has been counted (step S55). If the time T4 has elapsed (step S55). YES), the process returns to step S33. If time T4 has not elapsed (NO in step S55), the process returns to step S53. In this process, even if it is determined that no overcurrent has occurred, the count value Ct is maintained when the time T4 has not elapsed, and the count value Ct is reset when the time T4 has elapsed. Will do.
- step S33 shown in FIG. 4 is summarized as follows (e) to (g).
- FIG. 6 is a timing chart showing the change of the reference voltage Vp with time after the convergence of the inrush current.
- the FET (Q1) is turned off according to the magnitude of the load current I0 and its duration.
- the FET (Q1) can be turned off to protect the FET (Q1) and the electric wire.
- the output signal of the comparator CMP2 when the reference voltage Vp exceeds the double voltage Vref2, the output signal of the comparator CMP2 becomes H level, and the low-speed following voltage Vc obtained by smoothing the reference voltage Vp is the reference voltage Vref1.
- the output signal of the comparator CMP1 becomes H level when exceeding. Further, when at least one of these becomes H level, the output signal of the OR circuit OR1 becomes H level, which satisfies the overcurrent determination.
- the reference voltage Vp is directly supplied to the input terminal (+ terminal) of the comparator CMP1 and compared with the reference voltage Vref1 without using a time constant circuit (that is, the reference voltage Vp is equal to the reference voltage Vp).
- the output signal of the comparator CMP1 is at the L level between the times t2 and t3 shown in FIG. 9, but the comparator CMP1 is between the times t1 and t2.
- Output signal becomes H level, satisfies the overcurrent determination, and the FET (Q1) is cut off.
- the reference voltage Vref1 must be set to a large value and set to a level equivalent to the double voltage Vref2 shown in FIG.
- the FET (Q1) is not cut off when the current that is slightly lower than the reference voltage Vref1 flows as indicated by the symbol q13 shown in FIG. Trouble that the temperature rises and overheats occurs.
- the overcurrent determination is satisfied, so that the pulsating current as indicated by the symbol q1 in FIG.
- the FET (Q1) is not erroneously interrupted, and if a low overcurrent continues to flow, the FET (Q1) can be interrupted by detecting this.
- FIG. 13A is a characteristic diagram showing a change in the output voltage VBA of the battery VB
- FIG. 13B is a signal input to the VBA monitor circuit 15 provided in the IC circuit 51-1 (CH1).
- 13C shows the output signal
- FIG. 13D shows the output signal of the VBA monitor circuit 15 provided in the IC circuit 51-2 (CH2)
- FIG. 13E shows the VBA provided in the IC circuit 51-3.
- the output signal of the monitor circuit 15 is shown. Note that the output signals shown in FIGS. 13C to 13E are output to the OR circuit OR2 shown in FIG. 2, so that “ON” is an L level signal and “OFF” is “OFF”. It is an H level signal.
- the VBA monitor circuit 15 monitors the output voltage VBA of the battery VB, and shuts off the FET (Q1) when the battery voltage VBA drops below a predetermined voltage (for example, 3.3 V). If the operation is repeated several times (for example, 7 times) and the battery voltage VBA does not return to the normal voltage, it is assumed that a dead short circuit has occurred in the load driving circuit, and the FET (Q1) is turned off. And a function of protecting the load driving circuit.
- a predetermined voltage for example, 3.3 V.
- step S71 when detecting the input of the drive signal from the terminal D1 at time t11 shown in FIG. 13 (step S71), the VBA monitor circuit 15 waits for the turn-on time Tdon (step S72), and then the FET ( A signal for turning on Q1) is output (step S73). That is, an L level output signal is output to the OR circuit OR2. As a result, the FET (Q1) is turned on, and the load RL1 is driven.
- the VBA monitor circuit 15 starts measuring the first elapsed time Tx after the FET (Q1) is turned on (step S74). Furthermore, the time measurement of the second elapsed time Tr is started (step S75).
- the first elapsed time Tx is used to measure the time from when the FET (Q1) is turned on until the battery voltage VBA drops below 3.3 V, and the second elapsed time Tr is This is used to determine whether or not a preset interval time Tc (first predetermined time, for example, 0.2 seconds) has elapsed since (Q1) was turned on.
- the VBA monitor circuit 15 determines whether or not the second elapsed time Tr is less than the interval time Tc (step S76). When the second elapsed time Tr is equal to or longer than the interval time Tc (NO in step S76), the count value N indicating the number of times the FET (Q1) is turned off is reset to 0 (step S77).
- step S78 it is determined whether or not the battery voltage VBA is less than 3.3 V set as the predetermined voltage. In this process, it is determined whether or not a dead short circuit has occurred in the load driving circuit. If a dead short circuit has occurred in the load driving circuit, the FET (Q1) is turned on. At this time, a back electromotive force is generated in the circuit for driving the load, and the battery voltage VBA rapidly decreases, so that the voltage decreases to less than 3.3V.
- step S78 If no dead short has occurred in the load driving circuit and the battery voltage VBA is 3.3 V or higher (NO in step S78), the processing in steps S76 to S78 is repeated, and the FET ( The on state of Q1) is maintained.
- Step S79 the VBA monitor circuit 15 turns off the FET (Q1). That is, the output signal of the VBA monitor circuit 15 is set to H level, the output signal of the OR circuit OR2 is set to H level, the output of the flip-flop circuit 12 is set to L level, and the FET (Q1) is turned off.
- the VBA monitor circuit 15 sets a waiting time Tp that is randomly determined by a random value (step S80).
- This random value can be set to any numerical value based on, for example, the data latch (0, 1, 2, 3) of the charge pump 13 shown in FIG. 2, and the standby time Tp is set to a random time. Will be.
- the VBA monitor circuit 15 determines whether or not the first elapsed time Tx measured in the process of step S74 is less than a preset threshold time of 400 ⁇ sec (step S81). That is, in the IC circuit 51-1, whether or not the first elapsed time Tx from when the FET (Q1) is turned on to when the battery voltage VBA decreases and falls below 3.3V is less than 400 ⁇ sec set as the threshold time. Is judged.
- step S86 it is determined whether or not the battery voltage VBA exceeds 3.3V set as the threshold voltage (step S86), and the battery voltage VBA is If the voltage does not exceed 3.3V (NO in step S86), the process waits until battery voltage VBA exceeds 3.3V. Thereafter, when the battery voltage VBA exceeds 3.3 V at time t14 in FIG. 13 (YES in step S86), the process waits for the standby time Tp determined in the process of step S80, and then returns to the process of step S73. The FET (Q1) is turned on again.
- the battery voltage VBA is also applied to the VBA monitor circuit 15 of the other two IC circuits 51-2 (CH2) and 51-3 (CH3). Therefore, each FET (Q1) is turned off to protect the FET (Q1) and the electric wire. That is, the FETs (Q1) of all the IC circuits 51-1 to 51-3 are turned off at the time t13.
- step S87 in FIG. 12 the standby time Tp is randomly set based on the random number value, so that the standby time Tp is different for each of the IC circuits 51-1 to 51-3.
- the FET (Q1) provided in each of the IC circuits 51-1 to 51-3 is not turned on at the same time after being turned off at the time t13, but turned on with a time difference.
- the standby time is set to Tp1, Tp4, and Tp6 in the IC circuit 51-1, and the standby time is set to Tp2 (> Tp1) and Tp7 in the IC circuit 51-2.
- the standby time is set to Tp3 ( ⁇ Tp3), Tp5, and Tp8.
- the FET (Q1) of the IC circuit 51-2 is turned on again at a time t16 later than the time t15 when the FET (Q1) of the IC circuit 51-1 is turned on again. It is said.
- the FET (Q1) of the IC circuit 51-3 is turned on again at a time t17 earlier than the time t15 when the FET (Q1) of the IC circuit 51-1 is turned on again. It is said.
- the timings at which the FETs (Q1) of the IC circuits 51-1 to 51-3 are turned on do not match and do not turn on at the same time, so the inrush currents do not match and the IC circuits 51-1 to 51-
- the inrush current at 3 can be avoided from overlapping.
- the battery voltage VBA does not drop below 3.3 V after the IC circuit 51-1 that is the source of the dead short is turned off, the normally operating IC circuit 51-2, After the FET (Q1) 51-3 is turned on, the on state is maintained and the driving of the loads RL2 and RL3 is continued.
- the required time y4 until the FET (Q1) is turned on at time t19 and the battery voltage VBA decreases to less than 3.3 V is 400 ⁇ sec or more.
- the count value N is reset when the interval time Tc set in step S76 in FIG. 12 has elapsed. Therefore, if the battery voltage VBA does not decrease continuously, the count value N is reset after the interval time Tc has elapsed. Therefore, when the battery voltage VBA decreases for a reason other than dead short, load driving is performed. Therefore, it is possible to prevent the malfunction of holding the circuit for use in the off state.
- each IC circuit 51- Each FET (Q1) provided in 1 to 51-3 is turned off to shut off each load driving circuit. Further, the elapsed time from when the FET (Q1) is turned on until the battery voltage VBA drops below 3.3 V is counted, and when the threshold time is less than 400 ⁇ sec, the count value N is incremented. Then, after the standby time Tp (Tp1 to Tp8) set at random has elapsed, the FET (Q1) of each of the IC circuits 51-1 to 51-3 is turned on.
- the count value N is not incremented and the count value N does not reach 7, so that the ON state is continued.
- the timing for performing the retry operation is set randomly by a plurality of overcurrent protection devices, it is possible to avoid the FET (Q1; electronic switch) provided in each load driving circuit from being turned on simultaneously. Thus, it is possible to easily determine the load driving circuit in which the dead short has occurred.
- the count value N is reset when the count value N does not reach 7 times within the interval time Tc (for example, 0.2 seconds), and therefore, when the battery voltage VBA is reduced due to a cause other than dead short, It is possible to prevent the drive circuit from being erroneously cut off.
- the IC circuits 51-1 to 51-3 can match the time when the standby time Tp starts to be measured, and can accurately count the standby time Tp.
- the overcurrent protection device and the overcurrent protection system of the present invention have been described based on the illustrated embodiment.
- the present invention is not limited to this, and the configuration of each part is an arbitrary function having the same function. It can be replaced with that of the configuration.
- the present invention includes three IC circuits. It is not limited.
- the present invention can be used for FET (Q1) that drives a load mounted on a vehicle and overcurrent protection of electric wires.
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Abstract
Description
(a)FET(Q1)をオンとした後、負荷電流I0が過電流判定を満たし、更に、参照電圧Vpが8倍電圧Vref8を超えた場合には、即時にFET(Q1)をオフとする。図5は時間経過に対する参照電圧Vpの変化を示すタイミングチャートであり、図5に示す時刻t0でFET(Q1)をオンとし、時刻t0~t1の時間帯でVpがVref8を超えた場合に、FET(Q1)をオフとする。
12 フリップフロップ回路
13 チャージポンプ
14 ロジック回路
15 VBAモニタ回路
16 Vds検出回路
17 オン故障検出回路
18 発振器
19 過電圧検出器
51-1~53-3 IC回路
VB バッテリ(直流電源)
Q1 マルチソースFET
Q1a メインFET
Q1b サブFET
CMP1~CMP5 比較器
AMP1 アンプ
OR1 オア回路
OR2 オア回路
AND1 アンド回路
Ris 電流検出抵抗
Claims (6)
- 直流電源と、電子スイッチ、電線、及び負荷を有する負荷駆動用の回路を過電流から保護する過電流保護装置において、
前記直流電源の出力電圧を検出する電圧検出手段と、
前記電子スイッチをオンとした後の経過時間を計時する計時手段と、
前記直流電源の出力電圧が予め設定した閾値電圧以下に低下した場合に、前記電子スイッチをオフとし、所定の待機時間が経過した後に、該電子スイッチを再度オンとするスイッチ制御手段と、
前記出力電圧が前記閾値電圧以下に低下して、前記電子スイッチがオフとされた際に、前記所定の待機時間を、ランダムに決定する待機時間決定手段と、
前記電子スイッチをオンとしてから、前記直流電源の出力電圧が前記閾値電圧に低下するまでの所要時間が予め設定した閾値時間以下である場合に、この発生回数をカウントするカウント手段と、を有し、
前記スイッチ制御手段は、前記カウント手段によるカウント値が所定のカウント閾値に達した場合には、前記所定の待機時間の経過に関わらず前記電子スイッチのオフ状態を保持する過電流保護装置。 - 前記カウント手段は、前記発生回数がカウントされた後、第1の所定時間が経過するまで次回のカウントが発生しなかった場合に、前記カウント値をリセットする請求項1に記載の過電流保護装置。
- 前記スイッチ制御手段は、前記直流電源の出力電圧が前記閾値電圧以下に低下して前記電子スイッチをオフとした後、出力電圧が前記閾値電圧まで上昇した時点から、前記待機時間の経過を計時する請求項1または請求項2のいずれかに記載の過電流保護装置。
- 電子スイッチ及び負荷を有する複数の負荷駆動用の回路と、前記各負荷駆動用の回路に接続された唯一の直流電源とを備えた駆動制御回路の電線を、過電流から保護する過電流保護システムにおいて、
前記各負荷駆動用の回路は、それぞれ過電流保護装置を有し、一の負荷駆動用の回路に設けられる前記過電流保護装置は、
前記直流電源の出力電圧を検出する電圧検出手段と、
前記一の負荷駆動用の回路の電子スイッチをオンとした後の経過時間を計時する計時手段と、
前記直流電源の出力電圧が予め設定した閾値電圧以下に低下した場合に、一の負荷駆動用の回路の電子スイッチをオフとし、所定の待機時間が経過した後に、前記電子スイッチを再度オンとするスイッチ制御手段と、
前記出力電圧が前記閾値電圧以下に低下して、前記一の負荷駆動用の回路の電子スイッチがオフとされた際に、前記所定の待機時間を、他の負荷駆動用の回路に設けられた過電流保護装置の待機時間と相違するように決定する待機時間決定手段と、
前記一の負荷駆動用の回路の電子スイッチをオンとしてから、前記直流電源の出力電圧が前記閾値電圧に低下するまでの所要時間が予め設定した閾値時間以下である場合に、この発生回数をカウントするカウント手段と、を有し、
前記スイッチ制御手段は、前記カウント手段によるカウント値が所定のカウント閾値に達した場合には、前記所定の待機時間の経過に関わらず前記電子スイッチのオフ状態を保持する過電流保護システム。 - 一の負荷駆動用の回路の前記カウント手段は、前記発生回数がカウントされた後、第1の所定時間が経過するまで次回のカウントが発生しなかった場合に、前記カウント値をリセットする請求項4に記載の過電流保護システム。
- 前記スイッチ制御手段は、前記直流電源の出力電圧が前記閾値電圧以下に低下して前記電子スイッチをオフとした後、出力電圧が前記閾値電圧まで上昇した時点から、前記待機時間の経過を計時する請求項4または請求項5のいずれかに記載の過電流保護システム。
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JP2021034892A (ja) * | 2019-08-26 | 2021-03-01 | 株式会社デンソー | 制御装置 |
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EP2472691A1 (en) | 2012-07-04 |
JP2011166872A (ja) | 2011-08-25 |
JP5351793B2 (ja) | 2013-11-27 |
EP2472691B1 (en) | 2016-09-07 |
EP2472691A4 (en) | 2014-07-23 |
US8547676B2 (en) | 2013-10-01 |
CN102576998B (zh) | 2014-03-26 |
US20120170166A1 (en) | 2012-07-05 |
CN102576998A (zh) | 2012-07-11 |
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