Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
  • C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
  • C09J5/06—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/93—Batch processes
  • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/93—Batch processes
  • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
  • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
  • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
  • C09J2301/00—Additional features of adhesives in the form of films or foils
  • C09J2301/50—Additional features of adhesives in the form of films or foils characterized by process specific features
  • C09J2301/502—Additional features of adhesives in the form of films or foils characterized by process specific features process for debonding adherents
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/561—Batch processing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/565—Moulds
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
  • H01L2224/0554—External layer
  • H01L2224/0556—Disposition
  • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
  • H01L2224/13001—Core members of the bump connector
  • H01L2224/13005—Structure
  • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/8119—Arrangement of the bump connectors prior to mounting
  • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/812—Applying energy for connecting
  • H01L2224/81201—Compression bonding
  • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/818—Bonding techniques
  • H01L2224/81801—Soldering or alloying
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8319—Arrangement of the layer connectors prior to mounting
  • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8319—Arrangement of the layer connectors prior to mounting
  • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/93—Batch processes
  • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/11—Manufacturing methods
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01042—Molybdenum [Mo]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01043—Technetium [Tc]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/013—Alloys
  • H01L2924/014—Solder alloys
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/146—Mixed devices
  • H01L2924/1461—MEMS
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19041—Component type being a capacitor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/20—Parameters
  • H01L2924/201—Temperature ranges
  • H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K

Definitions

• Disclosed embodiments relate to integrated circuit (IC) assembly processing, and more particularly to bonding die or wafers to TSV comprising wafers.
• IC integrated circuit
• the assembly is conventionally performed in a sequential manner by bonding a first thinned IC die then a second thinned IC die (e.g., a thinned die 25 to 150 ⁇ thick) onto a package substrate (e.g., PCB).
• the first IC die can be a TSV comprising die that is mounted face (i.e. active circuit/top side) up on the surface of a package substrate where the TSVs form joints with pads on the package substrate surface.
• Capillary underfill is then generally performed.
• the second IC die is then generally flip-chip (FC) mounted to the top side of the first IC die.
• Stacked die can also be formed by die-to- wafer methods (D2W).
• D2W die-to- wafer methods
• die-wafer stacks are formed by thinning a TSV wafer (e.g. to ⁇ 100 ⁇ thick) using a carrier wafer bonded to the top side of the TSV wafer to expose the TSVs tips on the bottom side of the TSV wafer.
• the carrier wafer is then removed and then the IC die are bonded to the top side of the thinned TSV wafer.
• warpage of the thinned TSV wafer can complicate jointing/bonding with the IC die.
• warpage results in misaligned joints which reduces contact area which increases contact resistance of the joint, particularly for fine pitched pads, and can even cause open circuited contacts.
• Disclosed embodiments provide solutions to the problems of warpage/bow, and scratching described above when bonding die or wafers to TSV comprising wafers to form stacked TSV wafer comprising electronic articles, which can be singulated to form thin die stacks including at least one TSV die.
• a first carrier wafer is mounted to the top surface of a TSV wafer comprising a plurality of IC die using a first adhesive material having a first debonding temperature.
• the TSV wafer is then thinned from its bottom side to form a thinned TSV wafer to expose the embedded TSV tips. Since a flat carrier wafer supports the TSV wafer during thinning, the resulting TSV tip height variation is significantly reduced as compared to the second D2W method described above.
• a second carrier wafer is then mounted to the bottom side of the TSV wafer using a second adhesive material to sandwich the TSV wafer.
• the second adhesive material has a second debonding temperature that is higher as compared to the debonding temperature of the first adhesive.
• the first carrier wafer is then selectively removed from the top side of the TSV wafer by heating to a temperature that is above the first debonding temperature, but is below the second debonding temperature so that the second carrier wafer remains attached to the TSV wafer.
• At least one second IC die which can comprise singulated IC die or a wafer is then bonded to the plurality TSV die on the top side of the thinned TSV wafer to form a stacked TSV wafer comprising electronic article. Since the TSV wafer is supported by the second carrier wafer during bonding of the singulated IC die or wafer, warpage/bow is significantly reduced which reduces the contact resistance of the joints, and as a result improves circuit performance and reliability of singulated stacked IC die generated by singulation (e.g. sawing) of the stacked TSV wafer comprising electronic article.
• singulation e.g. sawing
• FIG. 1 is a flow chart that shows steps in an example method for forming a stacked TSV wafer comprising electronic article from a TSV wafer including a plurality of TSV die that each include TSV precursors having embedded TSV tips and at least one second IC die, according to a disclosed embodiment.
• FIGS. 2A-G show successive cross-sectional depictions associated with an example dual carrier FC method for forming die-TSV wafer stacks or wafer- TSV wafer stacks, according to a disclosed embodiment.
• FIGS. 3A-H show successive cross section depictions associated with example mold-free assembly flows for forming singulated die stacks from a die-wafer stack, and then bonding the singulated die stack to a package substrate, according to a disclosed embodiment.
• FIGS. 4A-I show successive cross section depictions associated with example mold comprising assembly flows for forming singulated die stacks from a die-wafer stack, and then bonding the singulated die stack to a package substrate, according to a disclosed embodiment.
• FIG. 5 is an example viscosity vs. temperature plot showing some adhesive materials that provide different debonding temperatures that can be used with disclosed embodiments.
• Disclosed embodiments include dual carrier wafer methods for forming stacked
• TSV wafer comprising electronic articles that upon singulation provide a plurality of singulated stacked IC die.
• a "TSV wafer” includes a top side including a plurality of TSV die formed thereon comprising active circuitry and "TSV precursors" including embedded TSV tips, and a bottom side.
• TSV precursor refers to a structure that following thinning from the bottom side of the TSV wafer is sufficient to provide electrical access to the TSV tips so that the TSV precursors provide through substrate electrical connectivity.
• active circuitry generally comprises circuit elements including transistors, diodes, capacitors, and resistors, as well as signal lines and other conductors that interconnect these various circuit elements.
• FIG. 1 is a flow chart that shows steps in an example dual carrier method 100 for forming stacked TSV wafer comprising electronic articles from a TSV wafer, according to a disclosed embodiment.
• Step 101 comprises mounting a first carrier wafer onto a top side of the TSV wafer using a first adhesive material that has a first debonding temperature.
• the carrier wafer can comprise quartz or silicon, for example.
• the TSV wafer is generally a thick wafer defined herein to have a thickness of at least 100 ⁇ , that is typically at least 200 ⁇ (e.g. 500 to 800 ⁇ ) thick.
• the TSV wafer is thinned from its bottom side to form a thinned TSV wafer.
• the TSV wafer is generally thinned to a thickness of at least 25 ⁇ , typically from 25 ⁇ to 150 ⁇ .
• the thinning includes exposing the embedded TSV tips from the bottom side of the thinned TSV wafer to form exposed TSV tips.
• the exposed TSV tips protrude from the bottom side of the TSV wafer at least 5 ⁇ , such as 5 to 50 ⁇ .
• the TSV tips do not protrude from the bottom side of the wafer, and a redistribution layer (RDL) on the bottom side of the wafer provides contact to the exposed TSV tips.
• RDL redistribution layer
• Step 103 comprises mounting a second carrier wafer to the bottom side of the thinned TSV wafer using a second adhesive material.
• the second adhesive material has a second debonding temperature that is higher as compared to the first debonding temperature so that the second adhesive maintains attachment of its carrier wafer while the first adhesive debonds to allow removal of the first carrier wafer.
• the difference in debonding temperatures is generally at least 10 °C, and is more typically at least 20 °C, such as 50 °C, or more.
• the respective adhesives can be selected from thermoplastics, thermosets, with the option for light (e.g. UV) curable polymers in each case.
• light e.g. UV
• Step 104 comprises heating the thinned TSV wafer to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer.
• the temperature in step 104 is low enough to maintain the second adhesive in place so that the second carrier wafer remains attached. For example, in one embodiment, once the viscosity of the first adhesive falls to approximately 100 Pa S (or lower), such as by heating to about 250 °C, with the second adhesive selected to be stable at the selected debonding temperature, selective debonding of the first adhesive can take place. Solvent treatment may be applied to remove residual first adhesive.
• Step 105 comprises bonding a second IC die to the TSV die formed on the top surface of the thinned TSV wafer to form stacked TSV wafer comprising electronic article.
• the second IC die can comprises one or more singulated second IC die.
• the stacked TSV wafer comprising electronic article comprises a die-TSV wafer stack.
• the second IC die can also comprise a wafer that comprises a plurality of second IC die.
• the stacked TSV wafer comprising electronic article comprises a wafer- TSV wafer stack.
• the bonding can be FC bonding. In other embodiments, such as when the second
• the second IC die can be bonded top side (i.e. active circuit side) up on the top surface of the TSV wafer.
• top side i.e. active circuit side
• die or wafer stacks comprising a plurality of stacked second IC die (e.g., stacks of 2, 3 or more die and/or wafers) may be bonded to the thinned TSV wafer based on methodologies disclosed herein.
• the second carrier wafer can then be removed from the stacked TSV wafer comprising electronic article.
• the second adhesive can be removed in a variety of ways, including thermally and non-thermally (e.g. laser removal).
• the TSV wafer comprising electronic article can be singulated (e.g. sawed) to form a plurality of stacked IC die which can then be mounted onto a package substrate (e.g. organic substrate) as described below with respect to several example embodiments.
• FIGS. 2A-G show successive cross-sectional depictions associated with an example dual carrier FC method for forming TSV wafer comprising electronic articles, according to a disclosed embodiment.
• the conventional dielectric liner and the metal diffusion barrier layer that is present for TSVs having metal fillers such as copper are both not shown in the drawings provided herein.
• disclosed embodiments may generally be described as being FC assembly methods, when the second IC die or wafer including second IC die mounted onto the thinned TSV wafer itself includes TSVs, the second die can be mounted top side/face up.
• FIG. 2A After completing wafer Fab processing (e.g., passivation processing), a TSV wafer 202 having embedded TSVs 203 and a plurality of TSV die is shown in FIG. 2A.
• "FS" in the FIGS corresponds to the front/top side of the die or wafer, while "BS" corresponds to the /bottom side of the die or wafer.
• a first carrier wafer 205 is mounted to a top side of the TSV wafer 202 using a first adhesive material 206 that has a first debonding temperature.
• FIG. 2C shows a depiction after thinning of the TSV wafer (e.g. backgrinding) to form a thinned TSV wafer 202' comprising TSVs 203 having exposed TSV tips 203(a).
• FIG. 2D shows a cross-sectional depiction after mounting a second carrier wafer
• FIG. 2E show a cross-sectional depiction after heating allowing removal of the first carrier wafer 205 from the thinned TSV wafer 202'.
• the second carrier wafer 215 remains attached to the thinned TSV wafer 202' by second adhesive 207.
• the second IC die can comprises one or more singulated IC die.
• the stacked TSV wafer comprising electronic article formed comprises a die-TSV wafer stack.
• FIG. 2F shows a cross-sectional depiction after bonding singulated second IC die shown as Die 2 218 to the front side of a plurality of TSV Die formed on the top side of the thinned TSV wafer 202' to form a die- wafer stack.
• Die 2 218 is shown having a plurality of bonding conductors (bumps) 210 for FC jointing.
• Die 2 can be a semiconductor IC, MEMS device or MEMS comprising IC, or a passive device.
• the second IC die can also comprise a wafer that comprises a plurality of second IC die.
• the stacked TSV wafer comprising electronic article formed comprises a wafer-TSV wafer stack.
• FIG. 2G shows a cross-sectional depiction after bonding a wafer 261 comprising a plurality of second IC die shown as Die 2 218 to the front side of a plurality of TSV Die formed on the top side of the thinned TSV wafer 202' to form a wafer-TSV wafer stack.
• Die 2 218 is shown having a plurality of bonding conductors (bumps) 210 for FC jointing.
• Die 2 218 can be a semiconductor IC, MEMS device or MEMS comprising IC, or a passive device.
• a curable dielectric film (CDF) 213 is shown between Die 2 218 in FIG. 2F and the FS of thinned TSV wafer 202' and between wafer 261 in FIG.
• the CDF 213 allows compression bonding to simultaneously form joints as well as form an underfill material using a pressing force (pressure) sufficient to result in the bumps 210 for FC jointing on the Die 2 218 penetrating into the CDF layer 213 to form metallic joints between the bumps 210 and the bonding features on the FS of the TSV Die on the top side of the thinned TSV wafer 202', with a heat sufficient to result in the CDF 213 forming an underfill layer (e.g., cross-linking).
• a pressing force pressure
• Typical heat pressing conditions during compression bonding can comprise a temperature of 150-180 °C, force/area (pressure) during pressing of 35-133 Kgf/cm , and a pressing time between 100-180 sec. Accordingly, in this embodiment a conventional underfill process, such as capillary underfill or a non-conductive paste (NCP) process, is unnecessary.
• NCP non-conductive paste
• the CDF 213 can be applied (e.g., laminated) to the top/front side (FS) of the Die
• the CDF material prior to curing generally provides a low melt viscosity, such as lower than 500 to 1,000 Pascal-second (Pa » s), and fast curability, such as a 30 second cure time for a temperature of at least 180 °C.
• the CDF 213 can include an optional filler, with the wt. % of the filler in one embodiment based on matching the coefficient of thermal expansion (CTE) of the CDF to the CTE of the lamination area surface.
• the thickness of the CDF 213 is generally calculated to fill nominal underfill gap area with an additional thickness amount to reflect a manufacturability margin. For example, if the underfill gap is 10 ⁇ , the thickness of the CDF can be from 15 to 20 ⁇ .
• the CDF material can include flux.
• a flux refers to a chemically- or physically-active formulation capable of cleaning oxides and enabling wetting of metals (e.g., copper) with solder.
• Flux is generally included in the CDF when the bonding conductors include highly oxidizable metals, such as copper. Metallic joints are not formed at this step.
• the CDF enables heat pressing to form an underfill layer and provides bonding in a single assembly step.
• FIGS. 3A-H show successive cross section depictions associated with example mold-free assembly flows for forming singulated die stacks from a die-wafer stack, and then bonding the singulated die stack to a package substrate, according to a disclosed embodiment.
• the package substrate can comprise an organic or ceramic printed circuit board (PCB), for example.
• FIG. 3A shows a cross-sectional depiction depicting the removal of the second carrier wafer 215 from the die- wafer stack shown in FIG. 2F.
• FIG. 3B shows a cross-sectional depiction depicting the mounting of the carrier waferless die- wafer stack onto a dicing film 315.
• FIGS. 3C-E depict a mold-free capillary underfill flow assembly option.
• FIG. 3C depicts the result following wafer sawing the die-wafer stack shown in FIG. 3B to provide a plurality of singulated stacked die.
• FIG. 3D depicts mounting singulated stacked die onto a package substrate 301 that includes pads 302 using a process comprising TC bonding or mass reflow.
• FIG. 3E depicts the resulting structure after capillary underfill to dispose underfill 313 in the gap region between the bottom of the singulated stacked die and the surface of the substrate 301.
• FIGS. 3F-H depict a mold-free pre-applied underfill assembly option.
• FIG. 3F depicts placing a CDF film 321 between the die- wafer stack shown in FIG. 2F and a dicing film 315.
• FIG. 3G depicts wafer a singulated stacked die provided following sawing the die- wafer stack shown in FIG. 3F.
• FIG. 3H depicts the resulting structure after placing of singulated stacked die on a package substrate and compression bonding that results in bonding of the singulated stacked die to pads on the package substrate and also the formation of an underfill material from the CDF 321 between the singulated stacked die and the package substrate.
• FIGS. 4A-I show successive cross section depictions associated with example mold comprising assembly flows for forming singulated die stacks from a die-wafer stack, and then bonding the singulated die stack to a package substrate, according to a disclosed embodiment.
• FIG. 4A shows a depiction after application of a mold material 410 to the die- wafer stack shown in FIG. 2F.
• FIG. 4B shows a cross- sectional depiction depicting the removal of the second carrier wafer 215 from the die-wafer stack.
• FIG. 4C depicts mounting the molded die- wafer stack TSV tip 203(a) side up on a dicing film 315.
• FIGS. 4D-E depict a mold comprising capillary underfill flow assembly option.
• FIG. 4D depicts the result following wafer sawing the molded die-wafer stack shown in FIG. 4C to provide a plurality of mold comprising singulated stacked die.
• FIG. 4E depicts mounting the mold comprising singulated stacked die onto a package substrate 301 that includes pads 302 using a process comprising TC bonding or mass reflow.
• FIG. 4F depicts the resulting structure after capillary underfill to dispose underfill 313 in the gap region between the bottom of the singulated stacked die and the surface of the substrate 301.
• FIGS. 4G-I depict a mold-free pre-applied underfill assembly option.
• FIG. 4G depicts the structure after placing a CDF film 321 on the TSV tip side of molded die- wafer stack and mounting of the molded wafer stack TSV tip side up on a dicing film 315.
• FIG. 4H depicts a molded singulated stacked die provided following sawing the molded die-wafer stack on the dicing film 315 shown in FIG. 4G.
• the TSVs 209 are electrically accessible from the bottom side of the TSV wafer, but do not protrude from the bottom side of the wafer, such as when an RDL is included.
• FIG. 5 is a graph of viscosity vs. temperature (°C) for three different example adhesive materials that can generally be used as the bonding adhesives described herein.
• Adhesive A can be used for the lower debonding temperature adhesive, and adhesives B or C for the higher debonding temperature adhesive.
• Softening temperature as used herein refers to the temperature at which the viscosity is the minimum viscosity required to stand against debonding, such at least 200 Pa S.
• Curve A is the viscosity curve for the Brewer Science WaferBONDTM HT-10.10 coating manufactured by Brewer Science, Inc., Springfield, MO.
• Curves B and C provide other viscosity curves for other materials that provide a higher debonding temp as compared to that shown in Curve A.
• One example higher debonding temperature adhesive is from Sumitomo 3M, which is a UV-curing adhesive.
• the UV-curing liquid adhesive can be used analogous to HT10.10 for carrier wafer attachment. With this UV-curing adhesive is possible to remove from the glass or other carrier by laser exposing to form small bubbles on the boundary to the glass, followed by removal from the wafer by removal tape.
• Sumitomo 3M is manufactured by Sumitomo 3M Ltd. has heat proof capability against debonding of about 250 °C as shown for curves B and C in FIG. 5.
• the higher debonding temperature second adhesive is added to a TSV wafer having the lower bonding temperature adhesive on the other side, analogous to that shown in FIG.
• the second adhesive is then UV cured.
• the first adhesive is then selectively removed, such as around 200 °C for the first adhesive HT10.10, while leaving the second carrier wafer attached by the second adhesive.
• laser exposing can be used for forming bubbles to remove the glass carrier and the UV cured material from die-wafer stack prior to singulation of the die-wafer stack to form singulated stacked die.
• Embodiments of the invention can be integrated into a variety of process flows to form a variety of devices and related products.
• the semiconductor substrates may include various elements therein and/or layers thereon. These can include barrier layers, other dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
• embodiments of the invention can be used in a variety of processes including bipolar, CMOS, BiCMOS and MEMS.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Organic Chemistry (AREA)
• Wire Bonding (AREA)
• Dicing (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (2)

Family

ID=44309261

Family Applications (1)

Country Status (4)

Cited By (2)

Families Citing this family (41)

Family Cites Families (13)

• 2010
  • 2010-01-26 US US12/694,012 patent/US8017439B2/en active Active
  • 2010-12-17 CN CN2010800658302A patent/CN102844859A/zh active Pending
  • 2010-12-17 WO PCT/US2010/060927 patent/WO2011093955A2/en not_active Ceased
  • 2010-12-17 JP JP2012551156A patent/JP2013518432A/ja active Pending

Also Published As

Similar Documents

Legal Events