WO2014078130A1 - Semiconductor device package with a die to interposer wafer first bond - Google Patents

Semiconductor device package with a die to interposer wafer first bond Download PDF

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Publication number
WO2014078130A1
WO2014078130A1 PCT/US2013/068510 US2013068510W WO2014078130A1 WO 2014078130 A1 WO2014078130 A1 WO 2014078130A1 US 2013068510 W US2013068510 W US 2013068510W WO 2014078130 A1 WO2014078130 A1 WO 2014078130A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
interposer wafer
interposer
utilizing
bonding
Prior art date
Application number
PCT/US2013/068510
Other languages
French (fr)
Inventor
Michael G. Kelly
Ronald Patrick Huemoeller
Won Chul Do
David Jon Hiner
Original Assignee
Amkor Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/678,012 external-priority patent/US8796072B2/en
Priority claimed from US13/678,046 external-priority patent/US9040349B2/en
Priority claimed from US13/678,058 external-priority patent/US9136159B2/en
Application filed by Amkor Technology, Inc. filed Critical Amkor Technology, Inc.
Priority to KR1020157015867A priority Critical patent/KR101709029B1/en
Publication of WO2014078130A1 publication Critical patent/WO2014078130A1/en

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Definitions

  • Certain embodiments of the invention relate to semiconductor chip packaging. More specifically, certain embodiments of the invention relate to a method and system for a semiconductor device package with a die to interposer wafer first bond.
  • Semiconductor packaging protects integrated circuits, or chips, from physical damage and external stresses. In addition, it can provide a thermal conductance path to efficiently remove heat generated in a chip, and also provide electrical connections to other components such as printed circuit boards, for example.
  • Materials used for semiconductor packaging typically comprises ceramic or plastic, and form-factors have progressed from ceramic flat packs and dual in-line packages to pin grid arrays and leadless chip carrier packages, among others.
  • FIG. 1 A is a schematic illustrating an integrated circuit package configured with a die-to-wafer first bond, in accordance with an example embodiment of the invention.
  • FIG. 1 B is a schematic illustrating an integrated circuit package configured with a die to interposer wafer first bond and stacked die, in accordance with an example embodiment of the invention.
  • FIGS. 1 C-1 E illustrate example steps for bonding multiple die utilizing an adhesive film, in accordance with an example embodiment of the invention.
  • FIGS. 2A-2F illustrate example steps in a die to interposer wafer first bond structure, in accordance with an example embodiment of the invention.
  • FIG. 3 is a schematic illustrating example steps in a die to interposer wafer first bond process, in accordance with an example embodiment of the invention
  • FIG. 4 is a diagram illustrating a mechanical planarizing apparatus, in accordance with an example embodiment of the invention.
  • FIG. 5 is a diagram illustrating a vacuum planarizing apparatus, in accordance with an example embodiment of the invention.
  • FIGS. 6A-6E illustrate example steps for debonding wafers with large backside bumps, in accordance with an example embodiment of the invention.
  • FIG. 7 is a diagram illustrating die bonding utilizing a patterned underfill layer, in accordance with an example embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION
  • Certain aspects of the invention may be found in a method and system for a semiconductor device package with a die to interposer wafer first bond.
  • Example aspects of the invention may comprise bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the plurality of semiconductor die and the interposer wafer.
  • a mold material may be applied to encapsulate the plurality of semiconductor die.
  • the interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs.
  • TSVs through-silicon-vias
  • the interposer wafer may be singulated to generate a plurality of assemblies each comprising one or more of the plurality of semiconductor die and an interposer die.
  • the one or more of the plurality of assemblies may be bonded to one or more packaging substrates.
  • the plurality of die may be placed on the interposer wafer for the bonding utilizing an adhesive film.
  • the interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process.
  • the underfill material may be applied utilizing a capillary underfill process.
  • the plurality of semiconductor die may be bonded to the interposer wafer utilizing a mass reflow process or a thermal compression process.
  • the one or more additional die may be bonded to the plurality of semiconductor die utilizing a mass reflow process or a thermal compression process.
  • the mold material may comprise a polymer.
  • the one or more additional die may comprise micro-bumps for coupling to the plurality of semiconductor die.
  • FIG. 1 A is a schematic illustrating an integrated circuit package configured with a die-to-wafer first bond, in accordance with an example embodiment of the invention.
  • a package 100 comprising die 101 , a packaging substrate 103, passive devices 105, an interposer 107, solder balls 1 1 1 , a lid 1 13, and thermal interface material 1 18.
  • the die 101 may comprise integrated circuit die that have been separated from one or more semiconductor wafers.
  • the die 101 may comprise electrical circuitry such as digital signal processors (DSPs), network processors, power management units, audio processors, RF circuitry, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits, for example.
  • DSPs digital signal processors
  • SoC wireless baseband system-on-chip
  • the die 101 may comprise micro-bumps 109 for providing electrical contact between the circuitry in the die 101 and contact pads on the surface of the interposer 107.
  • the interposer 107 may comprise a semiconductor wafer, such as a silicon wafer, with through-silicon-vias (TSVs) 1 15 that provide electrically conductive paths from one surface of the interposer 107 to the opposite surface.
  • TSVs through-silicon-vias
  • the interposer 107 may also comprise backside bumps 1 17 for making electrical and mechanical contact to the packaging substrate 103.
  • the interposer 107 may comprise glass or an organic laminate material, either of which may be capable of large panel formats on the order of 500 x 500 mm, for example.
  • the packaging substrate 103 may comprise a mechanical support structure for the interposer 107, the die 101 , the passive devices 105, and the lid 1 13.
  • the packaging substrate 103 may comprise solder balls 1 1 1 on the bottom surface for providing electrical contact to external devices and circuits, for example.
  • the packaging substrate 103 may also comprise conductive traces in a non-conductive material for providing conductive paths from the solder balls to the die 101 via pads that are configured to receive the backside bumps 1 17 on the interposer 107.
  • the packaging substrate 103 may comprise pads 1 19 for receiving the solder balls 1 1 1 .
  • the pads 1 19 may comprise one or more under-bump metals, for example, for providing a proper electrical and mechanical contact between the packaging substrate 103 and the solder balls 1 1 1 .
  • the passive devices 105 may comprise electrical devices such as resistors, capacitors, and inductors, for example, which may provide functionality to devices and circuits in the die 101 .
  • the passive devices 105 may comprise devices that may be difficult to integrate in the integrated circuits in the die 101 , such as high value capacitors or inductors.
  • the passive devices 105 may comprise one or more crystal oscillators for providing one or more clock signals to the die 101 .
  • the lid 1 13 may provide a hermetic seal for the devices within the cavity defined by the lid 1 10 and the packaging substrate 103. A thermal interface may be created for heat transfer out of the die 101 to the lid 1 13 via the thermal interface material 1 18, which may also act as an adhesive.
  • the package 100 may be fabricated by first bonding the die 101 to the interposer 107 when the interposer is still part of a full wafer of interposer die, and may be bonded utilizing a mass reflow or thermal compression process.
  • the interposer wafer with attached die 101 may be processed for further assembly.
  • the interposer wafer may be thinned and the backside bumps 1 17 may be deposited.
  • a capillary underfill material may be placed between the die 101 and the interposer before a mold process is utilized to encapsulate the die 101 on the individual interposer die in the interposer wafer.
  • An assembly comprising the die 101 and the interposer wafer may be singulated and the singulated assembly may then be bonded to the packaging substrate 103 utilizing either mass reflow or thermal compression.
  • the lid 1 13 may be placed on the bonded assembly to provide a hermetic seal and protect the circuitry from the external environment. Finally, electrical tests may be performed following the bonding processes to verify that proper electrical connections were made and no shorts or open circuits exist.
  • FIG. 1 B is a schematic illustrating an integrated circuit package configured with a die to interposer wafer first bond and stacked die, in accordance with an example embodiment of the invention.
  • a package 150 comprising the die 101 , the packaging substrate 103, the passive devices 105, the interposer 107, and a stack of dynamic random access memory (DRAM) 121 .
  • the die 101 , the packaging substrate 103, the passive devices 105, and the interposer 107 may be substantially as described with respect to FIG. 1 A, for example, but with different electrical connectivity for the different die 101 and the stack of DRAM 121 .
  • the DRAM 121 may comprise a stack of die for providing a high density memory for circuitry in the die 101 or external to the package 150.
  • the DRAM 121 may be stacked front-to-back and therefore comprise TSV's for providing electrical connectivity between the individual die.
  • the package 150 may be fabricated by first bonding the die 101 and the DRAM 121 to the interposer 107 when still in wafer form, i.e. before singulation into individual interposer die.
  • the die 101 and the DRAM 121 may be bonded utilizing mass reflow or thermal compression process.
  • the interposer wafer and bonded die may be singulated into separate functional die/interposer die assemblies before being bonded to the packaging substrate 103.
  • a capillary underfill process may follow the bonding processes for mechanical and insulating purposes. Electrical tests may be performed following the bonding processes to verify that proper electrical connections were made and no shorts or open circuits exist.
  • FIGS. 1 C-1 E illustrate example steps for bonding multiple die utilizing an adhesive film, in accordance with an example embodiment of the invention.
  • a plurality of die 121 and an adhesive layer 129 there is shown a plurality of die 121 and an adhesive layer 129.
  • Each of the plurality of die 121 may comprise metal interconnects 123 for subsequent bonding to other die.
  • the metal interconnects 123 may comprise microbumps or copper pillars, for example.
  • the adhesive film 129 may comprise an adhesive tape, for example, to which the plurality of die 121 may be bonded, as illustrated in FIG. 1 C.
  • the adhesive film 129 may be a temporary adhesive for attaching multiple die to other die within a wafer.
  • the interposer 127 may comprise a wafer of individual interposer die (in which case the interposer 127 comprises an "interposer wafer").
  • the plurality of die 121 may be placed temporarily on the adhesive film 129. While FIG. 1 C illustrates the plurality of die 121 as consisting of three die, more or less die (including a single die) are also possible and contemplated.
  • An optional underfill material 125 may also be placed on the interposer wafer 127 as illustrated by underfill material 125 in FIG. 1 D, before bonding the plurality of die 121 to the interposer 127 utilizing the adhesive film 129.
  • the underfill material 125 may be for subsequent thermal compression bonding processes, for example, and may allow instant underfill through a snap cure during a subsequent thermal compression bonding process. This may improve bonding yields since a single underfill process may be utilized for the plurality of die 121 as compared to a separate place and underfill process for each of the die 121 .
  • the plurality of die 121 may be placed face up so that the metal interconnects 123 may be coupled to a receiving die.
  • the plurality of die 121 on the adhesive film 129 may then be placed on the interposer 127, as shown in FIGS. 1 D and 1 E, where the initial placement of the plurality of die 121 on the adhesive film 129 may enable fine control of the spacing and alignment of the plurality of die 121 with the interposer 127.
  • the interposer 127 may comprise metal pads 131 for receiving the metal interconnects 123.
  • a thermal compression bond process may be performed for proper electrical and mechanical bonds between the metal interconnects 123 and the metal pads 131 .
  • the adhesive film 129 may be removed resulting in the structure shown in FIG. 1 E.
  • FIGS. 2A-2F illustrate example steps in a die to interposer wafer first bond structure, in accordance with an example embodiment of the invention.
  • the die 203A-203C may comprise integrated circuit die that have been separated from one or more semiconductor wafers.
  • the die 203A-203C may comprise electrical circuitry such as digital signal processors (DSPs), network processors, power management units, audio processors, RF circuitry, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits, for example.
  • the die 203A-203C may comprise micro-bumps 205 for providing electrical contact between the circuitry in the die 203A-203C and front side pads 209 on the surface of the interposer wafer 201 .
  • the interposer wafer 201 may comprise a plurality of individual interposer die, each of which may be coupled to one or more die, such as the die 203A-203C.
  • the interposer wafer 201 may also comprise front side pads 209 for providing electrical contact to the die 203A-203C.
  • the interposer wafer 201 may comprise through-silicon-vias (TSVs) 207 for providing electrically conductive paths from one surface of the interposer to the other, once the interposer wafer 201 has been thinned.
  • TSVs through-silicon-vias
  • the die 203A-203C may be placed on the interposer wafer 201 and bonded using a thermal compression bonding technique, for example.
  • a mass reflow process may be utilized to bond the die 203A-203C.
  • a non-conductive paste (NCP) may also be utilized to assist in forming the bonds.
  • a capillary underfill may then be applied and may fill the volume between the die 203A-203C and the interposer wafer 201 .
  • FIG. 2B illustrates the die 203A-203C bonded to the interposer wafer 201 with underfill material 210.
  • the space between the die 203A-203C may be filled with a mold material 21 1 , as illustrated in FIG. 2C.
  • the mold material 21 1 may comprise a polymer material, for example, that may provide a non-conductive structural support for die bonded to the interposer wafer 201 , protecting the die in subsequent processing steps and when diced into individual packages.
  • the interposer wafer 201 may be thinned utilizing a back side polish or grind, for example, to expose the TSVs.
  • the interposer wafer 201 may be thinned to a thickness where the TSVs are still slightly covered, which may then be etched selectively in areas covering the TSVs. A protective layer may then be deposited over the remaining silicon and a polish of the exposed TSVs may be performed for improved contact to the TSVs. Additionally, metal pads may be deposited on the polished TSVs for better contact with the backside bumps 213.
  • the backside bumps 213 may be deposited, as shown in FIG. 2D, for making contact between the TSVs and subsequently bonded substrates, such as packaging substrates.
  • the molded assembly may then be singulated utilizing a cutting technology such as reactive ion etching, plasma etching (e.g. an inductively coupled plasma), laser cutting, or mechanical saw.
  • a cutting technology such as reactive ion etching, plasma etching (e.g. an inductively coupled plasma), laser cutting, or mechanical saw.
  • the molded assembly may be partially cut and the separated with a mechanical pulling apart of the die.
  • the singulated molded die/interposer assembly comprising the die 203A- 203B and the interposer die 201 A may then be bonded to the packaging substrate 215 via the backside bumps 213, as illustrated in FIG. 2E.
  • the packaging substrate 215 may comprise contact pads 219 for making contact with the backside bumps 213 on the interposer die 201 A and for subsequent placement of solder balls 227 as shown in FIG. 2F.
  • the lid 221 may be placed on the package assembly with a hermetic seal made with an adhesive 225 at the surface of the packaging substrate 215, which may also comprise a thermal interface material. Accordingly, the lid 221 may make contact with the top surfaces of the die 203A and 203B for thermal heat sinking purposes.
  • the solder balls 227 may comprise metal spheres for making electrical and mechanical contact with a printed circuit board, for example.
  • FIG. 3 is a schematic illustrating example steps in a die to interposer wafer first bond process, in accordance with an example embodiment of the invention.
  • a die to interposer wafer process beginning with a die to interposer wafer attach and underfill step 301 A.
  • the one or more die may be bonded utilizing a thermal compression bonding technique, for example. Additional die may also be bonded to the first bonded die, such as illustrated by the DRAM stack 121 shown in FIG. 1 B, or the interposer wafer as shown in FIG. 1 A, in the next die to interposer wafer attach and underfill step 301 B.
  • a capillary underfill process may be utilized following the bonding process, which may provide an insulating barrier between contacts and may fill the volume between the die and the interposer wafer. It should be noted that the process is not limited to a thermal compression technique. Accordingly, a mass reflow process may be utilized, for example. Thermal compression bonding techniques may be advantageous at 40 micron pitch or less and white bumps, i.e. high-k dielectric layer delamination, may be eliminated with thermal compression bonding. In addition, flatness may be improved with thermal compression bonding, resulting in fewer open circuit connections due to excessive gaps.
  • a molding step 303 may then be utilized to package the die/interposer assembly before thinning the interposer substrate to expose the TSVs in the backside finish step 305.
  • backside contacts may be applied to the exposed TSVs in the interposer wafer.
  • the molded die/interposer wafer assembly may then be singulated into a plurality of molded die on interposer die assemblies in the singulate step 307.
  • Singulation may be performed via laser cutting, plasma etching, reactive ion etching, or a sawing technique, for example.
  • the singulated assemblies may then be attached to packaging substrates in step 309 utilizing the deposited backside contacts.
  • the die/interposer/packaging substrate assembly may then be subjected to a reflow step 31 1 where the interposer die to packaging substrate contacts may be reflowed resulting in proper electrical and physical contact. This may be followed by a capillary underfill process where the volume between the interposer die and the packaging substrate, providing an insulating material between the contacts and filling the void to reject contamination.
  • the bonded package may be subjected to a final test step 315 for assessing the performance of the electronic circuitry in the bonded die and to test the electrical contacts made in the bonding processes.
  • FIG. 4 is a diagram illustrating a mechanical planarizing apparatus, in accordance with an example embodiment of the invention.
  • a boat 401 there is shown a boat 401 , clips 403, a plurality of die 405, and an interposer 407.
  • the boat 401 may comprise a rigid support structure in which a die/interposer assembly may be placed and held in place by the clips 403.
  • the boat 401 may be capable of withstanding high temperatures, above 200 C, for example used for processing the die/interposer assembly.
  • the plurality of die 405 may be bonded to the interposer 407 via a thermal compression bonding, technique, for example, prior to being placed in the boat 401 .
  • a thermal compression bonding technique, for example, prior to being placed in the boat 401 .
  • the curvature of an assembly comprising the plurality of die 405 and the interposer 407 may flatten with the clips 403 providing a downward force at the outer edges of the assembly.
  • the increased length in the lateral direction may be accommodated by sliding under the clips 403.
  • the boat 401 provides mechanical support in conjunction with the downward force of the clips 403, thereby planarizing the assembly.
  • the boat 401 and clips 403 may permit the partially assembled package to heat up in normal fashion, but when the die/interposer assembly has become flat with increased temperature, the boat 401 and clips 403 resist the normal progression of the warpage, holding the partially assembled package, flattening it during heating and then maintaining that flatness of the silicon interposer as temperatures climb higher.
  • FIG. 5 is a diagram illustrating a vacuum planarizing apparatus, in accordance with an example embodiment of the invention. Referring to FIG. 5, there is shown a boat 501 , a plurality of die 505, an interposer 507, vacuum sealing rings 1009, vacuum channels 51 1 , a valve 513, and a vacuum supply 515.
  • the boat 501 comprises a vacuum system to flatten the partially assembled package comprising the plurality of die 505 and the interposer 507.
  • the vacuum-mechanical system permits the partially assembled package to heat up in normal fashion, but when the partially assembled package has become flat, the vacuum-mechanical system resists the normal progression of the warpage, holding the partially assembled package in a flattened configuration during heating and then maintains that flatness of the silicon interposer 507 as temperatures increases.
  • the vacuum may be applied at room temperature or slightly elevated temperatures utilizing the vacuum supply 515 via the valve 513 and the vacuum channels 51 1 , and may be held utilizing the high-temperature sealing rings 509 so that the vacuum-mechanical boat 501 may travel through a standard reflow furnace and still maintain sufficient vacuum to maintain interposer silicon top surface planarity.
  • FIGS. 6A-6E illustrate example steps for debonding wafers with large backside bumps, in accordance with an example embodiment of the invention.
  • a carrier wafer 601 there is show a carrier wafer 601 , a wafer 603 with backside bumps 605, and a polymer layer 607.
  • the wafer 603 may comprise an electronics, or functional, wafer or an interposer wafer, for example, which may comprise large backside bumps 605 that may be susceptible to damage in debond processes.
  • the polymer layer 607 may be applied to protect the backside bumps 605 during debond processes.
  • the polymer layer 607 may comprise a resist material or an adhesive film or tape, for example, that may be applied on the wafer 603 over the backside bumps 605.
  • FIG. 6B A subsequent chuck attachment, such as with a vacuum technique, to the carrier wafer 601 and the top surface of the polymer layer 607 is shown in FIG. 6B.
  • the top chuck 609A may be moved in one lateral direction while the bottom chuck 609B may be moved in the opposite direction to separate the carrier wafer 601 from the wafer 603.
  • the polymer layer 607 may enable a proper vacuum seal to the surface, where there may be a poor seal when applied directly to the backside bumps 605.
  • FIG. 6C shows the resulting structure following debond from the carrier wafer 601 . Any adhesive residue remaining from the carrier wafer 601 may be removed in a cleaning process while still attached to the top chuck 609A.
  • the cleaned structure may then be affixed to a film frame 61 1 with the backside bumps 605 facing up, as shown in FIG. 6D, for example.
  • the polymer layer 607 may then be removed either chemically or thermally followed by a surface clean, resulting in the bonded wafer 603 shown in FIG. 6E, for example.
  • the film frame 61 1 may enable further processing and ease of transport for the bonded wafer 603.
  • FIG. 7 is a diagram illustrating die bonding utilizing a patterned underfill layer, in accordance with an example embodiment of the invention. Referring to FIG. 7, there is shown a top die 701 with microbumps 703 and a bottom die 705 comprising contact pads 707 and an underfill layer 709.
  • the microbumps 703 may comprise copper pillars, for example, and may correspond to the contact pads 707 in the bottom die 705.
  • the bottom die 705 is shown as a single die, in another example scenario, it may comprise an entire wafer of die, with a plurality of top die 701 being bonded to an interposer wafer 705 as opposed to a single die.
  • the underfill layer 709 may comprise a polymer applied to the top surface of the bottom die 705 that the next level die, e.g., the top die 701 , will be bonded to.
  • the polymer may comprise a re-passivation or pre- applied underfill that will flow and bond to both die surfaces negating the need for subsequent underfill processes.
  • the underfill layer 709 may be patterned utilizing photolithography techniques or laser ablation to expose the appropriate contact pads 707 in the bottom die 705, for example by forming wells in the underfill layer 709.
  • the exposed pads may be utilized to align the top die 701 to the bottom die 705.
  • the die may be bonded utilizing a thermal compression or mass reflow technique, for example.
  • a flux dip may be utilized to aid in wetting of solder from one surface to the other and the underfill may "snap-cure" and seal both to the top and bottom die surfaces.
  • the underfill may flow around and under the microbumps 703 and the contact pads 707 during the bond process.
  • aspects of the invention may comprise bonding a plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 comprising electronic devices to an interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, and applying an underfill material 210, 217, 709 between the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 and the interposer wafer.
  • a mold material 21 1 , 303 may be applied to encapsulate the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 .
  • the interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, may be thinned to expose through-silicon-vias (TSVs) and metal contacts 213, 707 may be applied to the exposed TSVs.
  • TSVs through-silicon-vias
  • the interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, may be singulated to generate a plurality of assemblies 100, 150 each comprising one or more of the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 and an interposer die 107, 201 A, 407, 507, 705.
  • the one or more of the plurality of assemblies may be bonded to one or more packaging substrates 103.
  • the plurality of die 101 , 121 , 203A-203C, 405, 505, 701 may be placed on the interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, for the bonding utilizing an adhesive film 61 1 .
  • the interposer wafer 127, 201 and in instances where wafer 603 comprises an interposer wafer, 603, may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process.
  • the underfill material 210, 217, 709 may be applied utilizing a capillary underfill process.
  • the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 may be bonded to the interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, utilizing a mass reflow process or a thermal compression process.
  • the one or more additional die 101 , 121 , 203A-203C, 405, 505, 701 may be bonded to the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 utilizing a mass reflow processor a thermal compression process.
  • the mold material 21 1 , 303 may comprise a polymer.
  • the one or more additional die 101 , 121 , 203A- 203C, 405, 505, 701 may comprise micro-bumps for coupling to the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505.

Abstract

Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

Description

SEMICONDUCTOR DEVICE PACKAGE WITH A DIE TO INTERPOSER WAFER FIRST BOND
[0001]
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY
REFERENCE
[0002] This application makes reference to United States Application Serial No. 13/678,046, Attorney Docket No. 25032US01 , filed on 1 1 /15/2012, United States Application Serial No. 13/678,058, Attorney Docket No. 25031 US01 , filed on 1 1 /15/2012, and United States Application Serial No. 13/678,012, Attorney Docket No. 25963US01 , filed on 1 1 /15/2012.
[0003] Each of the above cited applications is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
[0004] Certain embodiments of the invention relate to semiconductor chip packaging. More specifically, certain embodiments of the invention relate to a method and system for a semiconductor device package with a die to interposer wafer first bond.
BACKGROUND OF THE INVENTION
[0005] Semiconductor packaging protects integrated circuits, or chips, from physical damage and external stresses. In addition, it can provide a thermal conductance path to efficiently remove heat generated in a chip, and also provide electrical connections to other components such as printed circuit boards, for example. Materials used for semiconductor packaging typically comprises ceramic or plastic, and form-factors have progressed from ceramic flat packs and dual in-line packages to pin grid arrays and leadless chip carrier packages, among others. [0006] Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0007] FIG. 1 A is a schematic illustrating an integrated circuit package configured with a die-to-wafer first bond, in accordance with an example embodiment of the invention.
[0008] FIG. 1 B is a schematic illustrating an integrated circuit package configured with a die to interposer wafer first bond and stacked die, in accordance with an example embodiment of the invention.
[0009] FIGS. 1 C-1 E illustrate example steps for bonding multiple die utilizing an adhesive film, in accordance with an example embodiment of the invention.
[0010] FIGS. 2A-2F illustrate example steps in a die to interposer wafer first bond structure, in accordance with an example embodiment of the invention.
[0011] FIG. 3 is a schematic illustrating example steps in a die to interposer wafer first bond process, in accordance with an example embodiment of the invention
[0012] FIG. 4 is a diagram illustrating a mechanical planarizing apparatus, in accordance with an example embodiment of the invention.
[0013] FIG. 5 is a diagram illustrating a vacuum planarizing apparatus, in accordance with an example embodiment of the invention.
[0014] FIGS. 6A-6E illustrate example steps for debonding wafers with large backside bumps, in accordance with an example embodiment of the invention.
[0015] FIG. 7 is a diagram illustrating die bonding utilizing a patterned underfill layer, in accordance with an example embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION
[0016] Certain aspects of the invention may be found in a method and system for a semiconductor device package with a die to interposer wafer first bond. Example aspects of the invention may comprise bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the plurality of semiconductor die and the interposer wafer. A mold material may be applied to encapsulate the plurality of semiconductor die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate a plurality of assemblies each comprising one or more of the plurality of semiconductor die and an interposer die. The one or more of the plurality of assemblies may be bonded to one or more packaging substrates. The plurality of die may be placed on the interposer wafer for the bonding utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The underfill material may be applied utilizing a capillary underfill process. The plurality of semiconductor die may be bonded to the interposer wafer utilizing a mass reflow process or a thermal compression process. The one or more additional die may be bonded to the plurality of semiconductor die utilizing a mass reflow process or a thermal compression process. The mold material may comprise a polymer. The one or more additional die may comprise micro-bumps for coupling to the plurality of semiconductor die.
[0017] FIG. 1 A is a schematic illustrating an integrated circuit package configured with a die-to-wafer first bond, in accordance with an example embodiment of the invention. Referring to FIG. 1 A, there is shown a package 100 comprising die 101 , a packaging substrate 103, passive devices 105, an interposer 107, solder balls 1 1 1 , a lid 1 13, and thermal interface material 1 18.
[0018] The die 101 may comprise integrated circuit die that have been separated from one or more semiconductor wafers. The die 101 may comprise electrical circuitry such as digital signal processors (DSPs), network processors, power management units, audio processors, RF circuitry, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits, for example. In addition, the die 101 may comprise micro-bumps 109 for providing electrical contact between the circuitry in the die 101 and contact pads on the surface of the interposer 107.
[0019] The interposer 107 may comprise a semiconductor wafer, such as a silicon wafer, with through-silicon-vias (TSVs) 1 15 that provide electrically conductive paths from one surface of the interposer 107 to the opposite surface. The interposer 107 may also comprise backside bumps 1 17 for making electrical and mechanical contact to the packaging substrate 103. In another example scenario, the interposer 107 may comprise glass or an organic laminate material, either of which may be capable of large panel formats on the order of 500 x 500 mm, for example.
[0020] The packaging substrate 103 may comprise a mechanical support structure for the interposer 107, the die 101 , the passive devices 105, and the lid 1 13. The packaging substrate 103 may comprise solder balls 1 1 1 on the bottom surface for providing electrical contact to external devices and circuits, for example. The packaging substrate 103 may also comprise conductive traces in a non-conductive material for providing conductive paths from the solder balls to the die 101 via pads that are configured to receive the backside bumps 1 17 on the interposer 107. Additionally, the packaging substrate 103 may comprise pads 1 19 for receiving the solder balls 1 1 1 . The pads 1 19 may comprise one or more under-bump metals, for example, for providing a proper electrical and mechanical contact between the packaging substrate 103 and the solder balls 1 1 1 .
[0021] The passive devices 105 may comprise electrical devices such as resistors, capacitors, and inductors, for example, which may provide functionality to devices and circuits in the die 101 . The passive devices 105 may comprise devices that may be difficult to integrate in the integrated circuits in the die 101 , such as high value capacitors or inductors. In another example scenario, the passive devices 105 may comprise one or more crystal oscillators for providing one or more clock signals to the die 101 . [0022] The lid 1 13 may provide a hermetic seal for the devices within the cavity defined by the lid 1 10 and the packaging substrate 103. A thermal interface may be created for heat transfer out of the die 101 to the lid 1 13 via the thermal interface material 1 18, which may also act as an adhesive.
[0023] In an example scenario, the package 100 may be fabricated by first bonding the die 101 to the interposer 107 when the interposer is still part of a full wafer of interposer die, and may be bonded utilizing a mass reflow or thermal compression process. The interposer wafer with attached die 101 may be processed for further assembly. For example, the interposer wafer may be thinned and the backside bumps 1 17 may be deposited. Furthermore, a capillary underfill material may be placed between the die 101 and the interposer before a mold process is utilized to encapsulate the die 101 on the individual interposer die in the interposer wafer.
[0024] An assembly comprising the die 101 and the interposer wafer may be singulated and the singulated assembly may then be bonded to the packaging substrate 103 utilizing either mass reflow or thermal compression. The lid 1 13 may be placed on the bonded assembly to provide a hermetic seal and protect the circuitry from the external environment. Finally, electrical tests may be performed following the bonding processes to verify that proper electrical connections were made and no shorts or open circuits exist.
[0025] FIG. 1 B is a schematic illustrating an integrated circuit package configured with a die to interposer wafer first bond and stacked die, in accordance with an example embodiment of the invention. Referring to FIG. 1 B, there is shown a package 150 comprising the die 101 , the packaging substrate 103, the passive devices 105, the interposer 107, and a stack of dynamic random access memory (DRAM) 121 . The die 101 , the packaging substrate 103, the passive devices 105, and the interposer 107 may be substantially as described with respect to FIG. 1 A, for example, but with different electrical connectivity for the different die 101 and the stack of DRAM 121 .
[0026] The DRAM 121 may comprise a stack of die for providing a high density memory for circuitry in the die 101 or external to the package 150. The DRAM 121 may be stacked front-to-back and therefore comprise TSV's for providing electrical connectivity between the individual die.
[0027] In an example scenario, the package 150 may be fabricated by first bonding the die 101 and the DRAM 121 to the interposer 107 when still in wafer form, i.e. before singulation into individual interposer die. The die 101 and the DRAM 121 may be bonded utilizing mass reflow or thermal compression process. The interposer wafer and bonded die may be singulated into separate functional die/interposer die assemblies before being bonded to the packaging substrate 103. Furthermore, a capillary underfill process may follow the bonding processes for mechanical and insulating purposes. Electrical tests may be performed following the bonding processes to verify that proper electrical connections were made and no shorts or open circuits exist.
[0028] FIGS. 1 C-1 E illustrate example steps for bonding multiple die utilizing an adhesive film, in accordance with an example embodiment of the invention. Referring to FIG. 1 C, there is shown a plurality of die 121 and an adhesive layer 129. Each of the plurality of die 121 may comprise metal interconnects 123 for subsequent bonding to other die. In another example scenario, the metal interconnects 123 may comprise microbumps or copper pillars, for example.
[0029] The adhesive film 129 may comprise an adhesive tape, for example, to which the plurality of die 121 may be bonded, as illustrated in FIG. 1 C. The adhesive film 129 may be a temporary adhesive for attaching multiple die to other die within a wafer. For example. The interposer 127 may comprise a wafer of individual interposer die (in which case the interposer 127 comprises an "interposer wafer"). In an example scenario, the plurality of die 121 may be placed temporarily on the adhesive film 129. While FIG. 1 C illustrates the plurality of die 121 as consisting of three die, more or less die (including a single die) are also possible and contemplated.
[0030] An optional underfill material 125 may also be placed on the interposer wafer 127 as illustrated by underfill material 125 in FIG. 1 D, before bonding the plurality of die 121 to the interposer 127 utilizing the adhesive film 129. The underfill material 125 may be for subsequent thermal compression bonding processes, for example, and may allow instant underfill through a snap cure during a subsequent thermal compression bonding process. This may improve bonding yields since a single underfill process may be utilized for the plurality of die 121 as compared to a separate place and underfill process for each of the die 121 . The plurality of die 121 may be placed face up so that the metal interconnects 123 may be coupled to a receiving die.
[0031] The plurality of die 121 on the adhesive film 129 may then be placed on the interposer 127, as shown in FIGS. 1 D and 1 E, where the initial placement of the plurality of die 121 on the adhesive film 129 may enable fine control of the spacing and alignment of the plurality of die 121 with the interposer 127. The interposer 127 may comprise metal pads 131 for receiving the metal interconnects 123. Once the plurality of die 121 are placed on the interposer 127, a thermal compression bond process may be performed for proper electrical and mechanical bonds between the metal interconnects 123 and the metal pads 131 . Once bonded, the adhesive film 129 may be removed resulting in the structure shown in FIG. 1 E.
[0032] FIGS. 2A-2F illustrate example steps in a die to interposer wafer first bond structure, in accordance with an example embodiment of the invention. Referring to FIG. 2A, there is shown an interposer wafer 201 and a plurality of die 203A-203C. The die 203A-203C may comprise integrated circuit die that have been separated from one or more semiconductor wafers. The die 203A-203C may comprise electrical circuitry such as digital signal processors (DSPs), network processors, power management units, audio processors, RF circuitry, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits, for example. In addition, the die 203A-203C may comprise micro-bumps 205 for providing electrical contact between the circuitry in the die 203A-203C and front side pads 209 on the surface of the interposer wafer 201 .
[0033] The interposer wafer 201 may comprise a plurality of individual interposer die, each of which may be coupled to one or more die, such as the die 203A-203C. The interposer wafer 201 may also comprise front side pads 209 for providing electrical contact to the die 203A-203C. Furthermore, the interposer wafer 201 may comprise through-silicon-vias (TSVs) 207 for providing electrically conductive paths from one surface of the interposer to the other, once the interposer wafer 201 has been thinned.
[0034] The die 203A-203C may be placed on the interposer wafer 201 and bonded using a thermal compression bonding technique, for example. In another example scenario, a mass reflow process may be utilized to bond the die 203A-203C. A non-conductive paste (NCP) may also be utilized to assist in forming the bonds. In addition, a capillary underfill may then be applied and may fill the volume between the die 203A-203C and the interposer wafer 201 . FIG. 2B illustrates the die 203A-203C bonded to the interposer wafer 201 with underfill material 210.
[0035] The space between the die 203A-203C may be filled with a mold material 21 1 , as illustrated in FIG. 2C. The mold material 21 1 may comprise a polymer material, for example, that may provide a non-conductive structural support for die bonded to the interposer wafer 201 , protecting the die in subsequent processing steps and when diced into individual packages. In an example scenario, the interposer wafer 201 may be thinned utilizing a back side polish or grind, for example, to expose the TSVs.
[0036] In another example scenario, the interposer wafer 201 may be thinned to a thickness where the TSVs are still slightly covered, which may then be etched selectively in areas covering the TSVs. A protective layer may then be deposited over the remaining silicon and a polish of the exposed TSVs may be performed for improved contact to the TSVs. Additionally, metal pads may be deposited on the polished TSVs for better contact with the backside bumps 213.
[0037] After the interposer wafer 201 has been thinned, the backside bumps 213 may be deposited, as shown in FIG. 2D, for making contact between the TSVs and subsequently bonded substrates, such as packaging substrates.
[0038] The molded assembly may then be singulated utilizing a cutting technology such as reactive ion etching, plasma etching (e.g. an inductively coupled plasma), laser cutting, or mechanical saw. In an example scenario, the molded assembly may be partially cut and the separated with a mechanical pulling apart of the die. [0039] The singulated molded die/interposer assembly comprising the die 203A- 203B and the interposer die 201 A may then be bonded to the packaging substrate 215 via the backside bumps 213, as illustrated in FIG. 2E. The packaging substrate 215 may comprise contact pads 219 for making contact with the backside bumps 213 on the interposer die 201 A and for subsequent placement of solder balls 227 as shown in FIG. 2F.
[0040] In addition, the lid 221 may be placed on the package assembly with a hermetic seal made with an adhesive 225 at the surface of the packaging substrate 215, which may also comprise a thermal interface material. Accordingly, the lid 221 may make contact with the top surfaces of the die 203A and 203B for thermal heat sinking purposes. The solder balls 227 may comprise metal spheres for making electrical and mechanical contact with a printed circuit board, for example.
[0041] FIG. 3 is a schematic illustrating example steps in a die to interposer wafer first bond process, in accordance with an example embodiment of the invention. Referring to FIG. 3, there is shown a die to interposer wafer process beginning with a die to interposer wafer attach and underfill step 301 A. The one or more die may be bonded utilizing a thermal compression bonding technique, for example. Additional die may also be bonded to the first bonded die, such as illustrated by the DRAM stack 121 shown in FIG. 1 B, or the interposer wafer as shown in FIG. 1 A, in the next die to interposer wafer attach and underfill step 301 B.
[0042] A capillary underfill process may be utilized following the bonding process, which may provide an insulating barrier between contacts and may fill the volume between the die and the interposer wafer. It should be noted that the process is not limited to a thermal compression technique. Accordingly, a mass reflow process may be utilized, for example. Thermal compression bonding techniques may be advantageous at 40 micron pitch or less and white bumps, i.e. high-k dielectric layer delamination, may be eliminated with thermal compression bonding. In addition, flatness may be improved with thermal compression bonding, resulting in fewer open circuit connections due to excessive gaps. [0043] A molding step 303 may then be utilized to package the die/interposer assembly before thinning the interposer substrate to expose the TSVs in the backside finish step 305. In addition, backside contacts may be applied to the exposed TSVs in the interposer wafer.
[0044] The molded die/interposer wafer assembly may then be singulated into a plurality of molded die on interposer die assemblies in the singulate step 307. Singulation may be performed via laser cutting, plasma etching, reactive ion etching, or a sawing technique, for example.
[0045] The singulated assemblies may then be attached to packaging substrates in step 309 utilizing the deposited backside contacts. The die/interposer/packaging substrate assembly may then be subjected to a reflow step 31 1 where the interposer die to packaging substrate contacts may be reflowed resulting in proper electrical and physical contact. This may be followed by a capillary underfill process where the volume between the interposer die and the packaging substrate, providing an insulating material between the contacts and filling the void to reject contamination.
[0046] Finally, the bonded package may be subjected to a final test step 315 for assessing the performance of the electronic circuitry in the bonded die and to test the electrical contacts made in the bonding processes.
[0047] FIG. 4 is a diagram illustrating a mechanical planarizing apparatus, in accordance with an example embodiment of the invention. Referring to FIG. 4, there is shown a boat 401 , clips 403, a plurality of die 405, and an interposer 407. The boat 401 may comprise a rigid support structure in which a die/interposer assembly may be placed and held in place by the clips 403. The boat 401 may be capable of withstanding high temperatures, above 200 C, for example used for processing the die/interposer assembly.
[0048] The plurality of die 405 may be bonded to the interposer 407 via a thermal compression bonding, technique, for example, prior to being placed in the boat 401 . As the temperature of the boat 401 the plurality of die 405, and the interposer 407 increases, the curvature of an assembly comprising the plurality of die 405 and the interposer 407 may flatten with the clips 403 providing a downward force at the outer edges of the assembly. As the curvature approaches zero, the increased length in the lateral direction may be accommodated by sliding under the clips 403. In addition, the boat 401 provides mechanical support in conjunction with the downward force of the clips 403, thereby planarizing the assembly.
[0049] The boat 401 and clips 403 may permit the partially assembled package to heat up in normal fashion, but when the die/interposer assembly has become flat with increased temperature, the boat 401 and clips 403 resist the normal progression of the warpage, holding the partially assembled package, flattening it during heating and then maintaining that flatness of the silicon interposer as temperatures climb higher.
[0050] FIG. 5 is a diagram illustrating a vacuum planarizing apparatus, in accordance with an example embodiment of the invention. Referring to FIG. 5, there is shown a boat 501 , a plurality of die 505, an interposer 507, vacuum sealing rings 1009, vacuum channels 51 1 , a valve 513, and a vacuum supply 515.
[0051] In an example scenario, the boat 501 comprises a vacuum system to flatten the partially assembled package comprising the plurality of die 505 and the interposer 507. The vacuum-mechanical system permits the partially assembled package to heat up in normal fashion, but when the partially assembled package has become flat, the vacuum-mechanical system resists the normal progression of the warpage, holding the partially assembled package in a flattened configuration during heating and then maintains that flatness of the silicon interposer 507 as temperatures increases.
[0052] The vacuum may be applied at room temperature or slightly elevated temperatures utilizing the vacuum supply 515 via the valve 513 and the vacuum channels 51 1 , and may be held utilizing the high-temperature sealing rings 509 so that the vacuum-mechanical boat 501 may travel through a standard reflow furnace and still maintain sufficient vacuum to maintain interposer silicon top surface planarity.
[0053] FIGS. 6A-6E illustrate example steps for debonding wafers with large backside bumps, in accordance with an example embodiment of the invention. Referring to FIG. 6A, there is show a carrier wafer 601 , a wafer 603 with backside bumps 605, and a polymer layer 607. [0054] The wafer 603 may comprise an electronics, or functional, wafer or an interposer wafer, for example, which may comprise large backside bumps 605 that may be susceptible to damage in debond processes. Accordingly, the polymer layer 607 may be applied to protect the backside bumps 605 during debond processes. The polymer layer 607 may comprise a resist material or an adhesive film or tape, for example, that may be applied on the wafer 603 over the backside bumps 605.
[0055] A subsequent chuck attachment, such as with a vacuum technique, to the carrier wafer 601 and the top surface of the polymer layer 607 is shown in FIG. 6B. The top chuck 609A may be moved in one lateral direction while the bottom chuck 609B may be moved in the opposite direction to separate the carrier wafer 601 from the wafer 603. The polymer layer 607 may enable a proper vacuum seal to the surface, where there may be a poor seal when applied directly to the backside bumps 605.
[0056] FIG. 6C shows the resulting structure following debond from the carrier wafer 601 . Any adhesive residue remaining from the carrier wafer 601 may be removed in a cleaning process while still attached to the top chuck 609A.
[0057] The cleaned structure may then be affixed to a film frame 61 1 with the backside bumps 605 facing up, as shown in FIG. 6D, for example. The polymer layer 607 may then be removed either chemically or thermally followed by a surface clean, resulting in the bonded wafer 603 shown in FIG. 6E, for example. The film frame 61 1 may enable further processing and ease of transport for the bonded wafer 603.
[0058] FIG. 7 is a diagram illustrating die bonding utilizing a patterned underfill layer, in accordance with an example embodiment of the invention. Referring to FIG. 7, there is shown a top die 701 with microbumps 703 and a bottom die 705 comprising contact pads 707 and an underfill layer 709.
[0059] In an example scenario, the microbumps 703 may comprise copper pillars, for example, and may correspond to the contact pads 707 in the bottom die 705. Although the bottom die 705 is shown as a single die, in another example scenario, it may comprise an entire wafer of die, with a plurality of top die 701 being bonded to an interposer wafer 705 as opposed to a single die. The underfill layer 709 may comprise a polymer applied to the top surface of the bottom die 705 that the next level die, e.g., the top die 701 , will be bonded to. The polymer may comprise a re-passivation or pre- applied underfill that will flow and bond to both die surfaces negating the need for subsequent underfill processes.
[0060] Furthermore, the underfill layer 709 may be patterned utilizing photolithography techniques or laser ablation to expose the appropriate contact pads 707 in the bottom die 705, for example by forming wells in the underfill layer 709. The exposed pads may be utilized to align the top die 701 to the bottom die 705. The die may be bonded utilizing a thermal compression or mass reflow technique, for example. A flux dip may be utilized to aid in wetting of solder from one surface to the other and the underfill may "snap-cure" and seal both to the top and bottom die surfaces. Furthermore the underfill may flow around and under the microbumps 703 and the contact pads 707 during the bond process.
[0061] In an embodiment of the invention, a method and system are disclosed for a semiconductor device package 100, 150 with a die to interposer wafer first bond. In this regard, aspects of the invention may comprise bonding a plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 comprising electronic devices to an interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, and applying an underfill material 210, 217, 709 between the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 and the interposer wafer. A mold material 21 1 , 303 may be applied to encapsulate the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 .
[0062] The interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, may be thinned to expose through-silicon-vias (TSVs) and metal contacts 213, 707 may be applied to the exposed TSVs. The interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, may be singulated to generate a plurality of assemblies 100, 150 each comprising one or more of the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 and an interposer die 107, 201 A, 407, 507, 705. The one or more of the plurality of assemblies may be bonded to one or more packaging substrates 103. The plurality of die 101 , 121 , 203A-203C, 405, 505, 701 may be placed on the interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, for the bonding utilizing an adhesive film 61 1 .
[0063] The interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The underfill material 210, 217, 709 may be applied utilizing a capillary underfill process. The plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 may be bonded to the interposer wafer 127, 201 , and in instances where wafer 603 comprises an interposer wafer, 603, utilizing a mass reflow process or a thermal compression process.
[0064] The one or more additional die 101 , 121 , 203A-203C, 405, 505, 701 may be bonded to the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505, 701 utilizing a mass reflow processor a thermal compression process. The mold material 21 1 , 303 may comprise a polymer. The one or more additional die 101 , 121 , 203A- 203C, 405, 505, 701 may comprise micro-bumps for coupling to the plurality of semiconductor die 101 , 121 , 203A-203C, 405, 505.
[0065] While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

CLAIMS What is claimed is:
1 . A method for semiconductor packaging, the method comprising: bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer; applying an underfill material between said plurality of semiconductor die and said interposer wafer; applying a mold material to encapsulate said plurality of semiconductor die; thinning said interposer wafer to expose through-silicon-vias (TSVs); applying metal contacts to said exposed TSVs; singulating said interposer wafer to generate a plurality of assemblies each comprising one or more of said plurality of semiconductor die and an interposer die; and bonding one or more of said plurality of assemblies to one or more packaging substrates.
2. The method according to claim 1 , comprising placing said plurality of die on said interposer wafer for said bonding utilizing an adhesive film.
3. The method according to claim 1 , comprising singulating said interposer wafer utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process.
4. The method according to claim 1 , wherein said underfill material is applied utilizing a capillary underfill process.
5. The method according to claim 1 , comprising bonding said plurality of semiconductor die to said interposer wafer utilizing a mass reflow process.
6. The method according to claim 1 , comprising bonding said plurality of semiconductor die to said interposer wafer utilizing a thermal compression process.
7. The method according to claim 1 , comprising bonding one or more additional die to said plurality of semiconductor die utilizing a mass reflow process.
8. The method according to claim 1 , comprising bonding said one or more additional die to said plurality of semiconductor die utilizing a thermal compression process.
9. The method according to claim 1 , wherein said mold material comprises a polymer.
10. The method according to claim 1 , wherein said one or more additional die comprise micro-bumps for coupling to said plurality of semiconductor die.
1 1 . A method for semiconductor packaging, the method comprising: generating a semiconductor package in a die to interposer wafer first bond process, said process comprising: bonding a plurality of semiconductor die comprising electronic devices to a front side of an interposer wafer; applying an underfill material between said plurality of semiconductor die and said interposer wafer; applying a mold material to encapsulate said plurality of semiconductor die; thinning said interposer wafer to expose through-silicon-vias (TSVs); applying metal contacts to said exposed TSVs; singulating said interposer wafer to generate a plurality of assemblies each comprising one or more of said plurality of semiconductor die and an interposer die; and bonding one or more of said plurality of assemblies to one or more packaging substrates.
12. The method according to claim 1 1 , comprising placing said plurality of die on said interposer wafer for said bonding utilizing an adhesive film.
13. The method according to claim 1 1 , comprising singulating said interposer wafer utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process.
14. The method according to claim 1 1 , wherein said underfill material is applied utilizing a capillary underfill process.
15. The method according to claim 1 1 , comprising bonding said plurality of semiconductor die to said interposer wafer utilizing a mass reflow process.
16. The method according to claim 1 1 , comprising bonding said plurality of semiconductor die to said interposer wafer utilizing a thermal compression process.
17. The method according to claim 1 1 , comprising bonding one or more additional die to said plurality of semiconductor die utilizing a mass reflow process.
18. The method according to claim 1 1 , comprising bonding said one or more additional die to said plurality of semiconductor die utilizing a thermal compression process.
19. The method according to claim 18, wherein said mold material comprises a polymer.
20. A method for semiconductor packaging, the method comprising: generating a semiconductor package in a die to interposer wafer first bond, said process comprising: bonding a plurality of semiconductor die comprising electronic devices to a front side of an interposer wafer; applying an underfill material between said plurality of semiconductor die and said interposer wafer; applying a mold material to encapsulate said plurality of semiconductor die; thinning said interposer wafer to expose through-silicon-vias (TSVs); applying metal contacts to said exposed TSVs; singulating said interposer wafer utilizing a plasma etching process to generate a plurality of assemblies each comprising one or more of said plurality of semiconductor die and an interposer die; and bonding one or more of said plurality of assemblies to one or more packaging substrates.
PCT/US2013/068510 2012-11-15 2013-11-05 Semiconductor device package with a die to interposer wafer first bond WO2014078130A1 (en)

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