WO2014078134A3 - Semiconductor package with a die to die first bond - Google Patents

Semiconductor package with a die to die first bond Download PDF

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Publication number
WO2014078134A3
WO2014078134A3 PCT/US2013/068544 US2013068544W WO2014078134A3 WO 2014078134 A3 WO2014078134 A3 WO 2014078134A3 US 2013068544 W US2013068544 W US 2013068544W WO 2014078134 A3 WO2014078134 A3 WO 2014078134A3
Authority
WO
WIPO (PCT)
Prior art keywords
die
interposer
semiconductor
bonding
semiconductor die
Prior art date
Application number
PCT/US2013/068544
Other languages
French (fr)
Other versions
WO2014078134A2 (en
Inventor
Michael G. Kelly
Ronald Patrick Huemoeller
Won Chul Do
Original Assignee
Amkor Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/678,012 external-priority patent/US8796072B2/en
Priority claimed from US13/678,058 external-priority patent/US9136159B2/en
Priority claimed from US13/678,046 external-priority patent/US9040349B2/en
Application filed by Amkor Technology, Inc. filed Critical Amkor Technology, Inc.
Priority to KR1020177027284A priority Critical patent/KR20170116185A/en
Priority to KR1020177026182A priority patent/KR20170107596A/en
Priority to KR1020157015868A priority patent/KR20150106877A/en
Publication of WO2014078134A2 publication Critical patent/WO2014078134A2/en
Publication of WO2014078134A3 publication Critical patent/WO2014078134A3/en

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Dicing (AREA)

Abstract

Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process.
PCT/US2013/068544 2012-11-15 2013-11-05 Method and system for a semiconductor device package with a die-to-die first bond WO2014078134A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020177027284A KR20170116185A (en) 2012-11-15 2013-11-05 Method for semiconductor device packaging with a die to die first bond
KR1020177026182A KR20170107596A (en) 2012-11-15 2013-11-05 Method And System For Semiconductor Device Package With A Die-To-Die First Bond
KR1020157015868A KR20150106877A (en) 2012-11-15 2013-11-05 Method And System For A Semiconductor Device Package With A Die-To-Die First Bond

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US13/678,012 US8796072B2 (en) 2012-11-15 2012-11-15 Method and system for a semiconductor device package with a die-to-die first bond
US13/678,058 US9136159B2 (en) 2012-11-15 2012-11-15 Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US13/678,058 2012-11-15
US13/678,012 2012-11-15
US13/678,046 2012-11-15
US13/678,046 US9040349B2 (en) 2012-11-15 2012-11-15 Method and system for a semiconductor device package with a die to interposer wafer first bond

Publications (2)

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WO2014078134A2 WO2014078134A2 (en) 2014-05-22
WO2014078134A3 true WO2014078134A3 (en) 2014-07-10

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PCT/US2013/068510 WO2014078130A1 (en) 2012-11-15 2013-11-05 Semiconductor device package with a die to interposer wafer first bond

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US20230326887A1 (en) * 2022-04-11 2023-10-12 Western Digital Technologies, Inc. Clamped semiconductor wafers and semiconductor devices

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Also Published As

Publication number Publication date
KR101709029B1 (en) 2017-02-21
KR20170116185A (en) 2017-10-18
KR20170107596A (en) 2017-09-25
WO2014078130A1 (en) 2014-05-22
KR20150106877A (en) 2015-09-22
WO2014078134A2 (en) 2014-05-22
KR20150087301A (en) 2015-07-29

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