WO2011091750A1 - Procédé pour analyser une carte unique à l'intérieur d'une frontière, son dispositif et sa carte unique - Google Patents

Procédé pour analyser une carte unique à l'intérieur d'une frontière, son dispositif et sa carte unique Download PDF

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Publication number
WO2011091750A1
WO2011091750A1 PCT/CN2011/070643 CN2011070643W WO2011091750A1 WO 2011091750 A1 WO2011091750 A1 WO 2011091750A1 CN 2011070643 W CN2011070643 W CN 2011070643W WO 2011091750 A1 WO2011091750 A1 WO 2011091750A1
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WO
WIPO (PCT)
Prior art keywords
jtag
pld
jacket
detected
cpu
Prior art date
Application number
PCT/CN2011/070643
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English (en)
Chinese (zh)
Inventor
曾文虹
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of WO2011091750A1 publication Critical patent/WO2011091750A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns

Definitions

  • Boundary scanning method, device and single board of the device in the board The application is submitted to the Chinese Patent Office on January 27, 2010, and the application number is 201 01 01 04402. 8.
  • the invention name is "Boundary scanning of the device in the board" The priority of the Chinese Patent Application, the entire disclosure of which is incorporated herein by reference.
  • the present invention relates to the field of communications, and in particular, to a boundary scan method, device, and board for a device in a single board.
  • JTAG Joint Test Action Group
  • TAP Test Access Port
  • JTAG test allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, which can be tested separately for each device. Therefore, in JTAG technology, the JTAG pins of each device on the board need to be connected in series to form a scan chain. Perform a boundary scan on the devices on the scan chain.
  • an aspect of the present invention provides a boundary scan method for devices in a single board, the board including a first programmable logic device PLD, to be Detecting device and first JTAG Jacket; wherein the first JTAG Jacket and the JTAG pin of the device to be detected are respectively connected to an input/output pin Bank of the first programmable logic device; Flattening the operating level of the device to which it is connected, the method includes:
  • a boundary scan device for a device in a single board including: a first programmable logic device PLD, a device to be detected, and a first JTAG Jacket; wherein the first JTAG Jacket and the The JTAG pins of the detecting device are respectively connected to the input and output pin banks of the first programmable logic device; the working level of the bank is the working level of the connected device.
  • a single board including the above-described boundary scanning device.
  • FIG. 1 is a schematic flow chart of a boundary scan method for a device in a single board according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a device in a single board according to another embodiment of the present invention
  • FIG. 3 is a schematic flowchart of a boundary scan method of a device in a single board according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a device in a board after a device to be detected is changed in a boundary scan method of a device in a single board according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a device in a single board in which a boot load is implemented in a boundary scan method of a device in a single board according to an embodiment of the present invention.
  • Embodiments of the present invention provide a boundary scan method for a device in a single board.
  • the single board includes a first programmable logic device (PLD), such as an erasable editable logic device (Erasable Programmable Logic Device). , EPLD), CPLD, Field Programmable Gate Array (FPGA), etc.
  • PLD programmable logic device
  • EPLD erasable editable logic device
  • FPGA Field Programmable Gate Array
  • resources in a logical device can be divided into groups or blocks, which are referred to as banks.
  • the board includes a JTAG EPLD, the device to be detected and the first JTAG Jacket; wherein the JTAG pin of the device to be detected, and the first JTAG Jacket are respectively connected to the input and output pin Bank of the JTAG EPLD;
  • the working level of the bank is the working level of the device connected to the bank.
  • the JTAG Jacket is a JTAG socket and can be connected to the JTAG test device.
  • One or more (two or more) devices can be selected from the device to be tested, with JTAG
  • the Jacket is connected in series to form a JTAG scan chain.
  • the chained solution can be implemented in the EPLD programming language, such as Verilog.
  • the CPU Under the control of the CPU, the CPU can form different scan chains by configuring the registers in the JTAG EPLD.
  • the Bank can be a pair of pins in the JTAG EPLD.
  • the device to be tested can be an electronic device that needs to be detected in a single board, such as a CPU or an FPGA.
  • the board may further include a second JTAG Jacket, where the second JTAG Jacket is connected to a JTAG pin of the JTAG EPLD, and the second JTAG Jacket is a JTAG EPLD.
  • Load the software online The above method for loading software on the JTAG EPLD is actually that the software loading device is connected to the JTAG EPLD through the second JTAG Jacket, and the online loading software for the JTAG EPLD is completed.
  • the above software loading device can be a CPU or JTAG debugging instrument, and the like.
  • the JTAG pin of the device to be tested is connected to the JTAG EPLD. Since the bank working level of the JTAG EPLD can be adjusted to the operating level of the device connected to the bank, no additional level is needed.
  • the conversion circuit can simplify the connection relationship of the JTAG pins of the device to be tested, thereby simplifying the BOM list; and the detection signals are all transmitted through the JTAG EPLD, the detection signal transmission distance is short, and the signal quality is good; further, the device to be detected
  • the connection method can be realized by software, so there is no need to change the solder joint of the device, and the chaining method is more flexible.
  • the method provided by another embodiment of the present invention may be applied to a single board as shown in FIG. 2, and the device in the single board may specifically include: JTAG EPLD 21 (the JTAG EPLD here has passed the second JTAG Jacket (in the figure) Not shown) the loading of the software is completed), the first JTAG Jacket 22, the DSP 23, the Application Specific Integrated Circuit (ASIC) 24, the first integrated circuit (IC) device 25, the CPU 26, the PLD 27 , the FPGA 28 and the second IC device 29; wherein, the DSP 23, the ASIC 24, the first IC device 25, the CPU 26, the PLD 27, the FPGA 28, and the second IC device 29 may be devices to be detected; the above JTAG EPLD 21 and the first JTAG Jacket 22.
  • JTAG EPLD 21 the JTAG EPLD here has passed the second JTAG Jacket (in the figure) Not shown
  • the loading of the software is completed
  • the first JTAG Jacket 22 the DSP 23, the Application Specific Integrated Circuit (ASIC) 24, the first integrated circuit (IC)
  • the working level of the bank connected to the first IC device, CPU26, PLD27, and FPGA28 is 3.3V.
  • the working level of the bank connected to the second IC device in JTAG EPLD21 is 2.5V.
  • the JTAG EPLD21 is connected to DSP23 and ASIC24.
  • the working level of the Bank is 1.8V; it should be noted that the first JTAG Jacket 22, DSP23, ASIC 24, first IC device 25, CPU 26, PLD 27, FPGA 28 and second IC are mentioned above.
  • the pin connected to JTAG EPLD21 is the JTAG pin.
  • the specific method for implementing S31 may be that the DSP 23, the ASIC 24, the first IC device, the CPU 26, the EPLD 27, the FPGA 28, the second IC device 29, and the first JTAG Jacket 22 are sequentially connected in series through the JTAG EPLD 21;
  • the series may also be connected in series without the above sequence, and the series only needs to include all the devices to be detected.
  • the method of implementing the above series connection can be referred to the related description in S11.
  • the device to be detected may also be a single device, such as separately detecting the CPU.
  • the first JTAG Jacket and the CPU need only be connected in series.
  • the JTAG EPLD21 receives the detection signal from the first JTAG Jacket22, and the device to be detected transmits the detection signal in series, and completes the detection of the device to be detected.
  • the specific step of completing S32 may include: the first JTAG Jacket22 sends a detection signal to the CPU 26 through the JTAG EPLD 21, and if the CPU 26 detects normal, the detection signal is transmitted to the PLD 27 through the JTAG EPLD 21, and if the PLD 27 detects normal, the detection signal passes the JTAG.
  • the EPLD 21 is passed to the first IC device. If the first IC device detects normal, the detection signal is passed through the JTAG EPLD 21 to the next device until all devices have been detected.
  • the FPGA 28 is taken as an example for description, and after the device to be detected is changed to the FPGA 28, the internal device of the single board is The structure is shown in FIG. 4.
  • the method may further include:
  • the first JTAG Jacket22 sends a detection signal to the FPGA 28 through JTAG EPLD21 to complete the detection.
  • the foregoing method may further include: controlling the PLD 27 to complete the loading of the booting program, and the device structure diagram of the board loaded in the booting is as shown in FIG. 5, and the loading process is as follows:
  • the STAG and the JTAG EPLD 21 select a control PLD 27 from the CPU 26 and the first JTAG Jacket 22 according to the selection command to complete the loading of the board boot.
  • the method of completing the S36 may include: the first JTAG Jacket22 sends a load command to the JTAG EPLD21, and the JTAG EPLD21 sends the load command to the PLD27 to control the PLD27 to complete the loading of the board boot.
  • the method of selecting the CPU 26 is as follows.
  • the method for completing the S36 may include: the CPU 26 sends a control command to the JTAG EPLD 21, and the JTAG EPLD 21 sends the load command to the PLD 27 to control the loading of the board by the PLD 27.
  • the specific implementation manner of the loading command of the JTAG EPLD receiving CPU and the loading command of the first JTAG Jacket may be: the loading command sent by the JTAG EPLD receiving CPU and the first JTAG Jacket, or the first being forwarded by the CPU by the JTAG EPLD.
  • the method provided in this embodiment may further include loading the JTAG EPLD online by using a JTAG pin of the JTAG EPLD.
  • the JTAG pin of the JTAG EPLD is connected to the JTAG Jacket. After the JTAG EPLD is powered on or reset, the JTAG EPet is used to control the JTAG EPLD online loading software.
  • the JTAG pin of the device to be tested is connected to the JTAG EPLD. Since the bank working level of the JTAG EPLD can be adjusted to the operating level of the device connected to the bank, no additional level is needed.
  • the conversion circuit can simplify the connection relationship of the JTAG pins of the device to be tested, thereby simplifying the BOM list; and the detection signals are all transmitted through the JTAG EPLD, the detection signal transmission distance is short, and the signal quality is good; further, the device to be detected
  • the connection method can be realized by software, so there is no need to change the solder joint of the device, and the chaining method is more flexible.
  • the invention also provides a detecting device for a device in a single board, comprising: a first PLD, to be detected a device and a first JTAG Jacket; wherein the first JTAG Jacket and the JTAG pin of the device to be detected are respectively connected to the input and output pin Bank of the first PLD; and the working level of the bank is the device connected thereto The working level.
  • the foregoing apparatus further includes:
  • the first JTAG Jacket completes the boundary scan of the device to be detected through the first PLD.
  • the device to be detected is at least two.
  • the device to be detected includes: a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD, and the second PLD is connected to the first JTAG Jacket through the first PLD;
  • the loading unit is configured to: after the first PLD receives the loading command of the CPU and the loading command of the first JTAG Jacket, select a control from the CPU and the first JTAG Jacket according to the selection command to complete loading of the board boot.
  • the board further includes: a second JTAG Jacket, where the second JTAG Jacket is connected to the JTAG pin of the first PLD, and is used to load the first PLD online software by using the second JTAG Jacket.
  • the device provided in this embodiment all the JTAG pins of the device to be detected are connected to the first PLD, because the bank working level of the first PLD can be adjusted to the operating level of the device connected to the bank. Therefore, no additional level conversion circuit is needed, which can simplify the connection relationship of the JTAG pins of the device to be detected, thereby simplifying the BOM list; and the detection signals are transmitted through the first PLD, and the detection signal transmission distance is short, the signal quality Further, further, the connection mode of the device to be tested can be implemented by software, so there is no need to change the solder joint of the device. The chaining method is more flexible.
  • Embodiments of the present invention also provide a single board, which may include the boundary scan device provided by the above embodiment, and various devices to be detected connected to the boundary scan device.
  • the boundary scan device can be implemented by using an EPLD, and the connection manner of the device to be tested and the JTAG EPLD can be referred to the solution disclosed in the foregoing embodiment, and details are not described herein.
  • the technical solution provided by the specific embodiment of the present invention has the advantages of simple connection relationship between the detection devices in the single board, short detection signal transmission distance, good signal quality, less BOM list, and flexible chaining mode.

Abstract

L'invention concerne un procédé destiné à effectuer le balayage d'une carte unique par balayage à l'intérieur d'une frontière, un dispositif et une carte unique. La carte unique comprend un premier dispositif logique programmable (PLD pour Programmable Logic Device), un dispositif destiné à être détecté et une première chemise JTAG, la première chemise JTAG et la broche JTAG du dispositif à détecter étant respectivement connectées au banc de broches d'entrée et au banc de broches de sortie du premier dispositif logique programmable ; et le niveau de fonctionnement des bancs de broches d'entrée et de sortie étant égal à celui des dispositifs connectés aux bancs de broches. Le procédé comprend les étapes consistant à : connecter en série le dispositif à détecter à la première chemise JTAG par l'intermédiaire du premier PLD ; recevoir un signal de détection JTAG de la première chemise JTAG ; et effectuer un balayage de frontière sur le dispositif connecté en série à détecter.
PCT/CN2011/070643 2010-01-27 2011-01-26 Procédé pour analyser une carte unique à l'intérieur d'une frontière, son dispositif et sa carte unique WO2011091750A1 (fr)

Applications Claiming Priority (2)

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CN201010104402.8 2010-01-27
CN2010101044028A CN101776728B (zh) 2010-01-27 2010-01-27 单板内器件的边界扫描方法及装置

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CN101776728B (zh) * 2010-01-27 2012-07-04 华为技术有限公司 单板内器件的边界扫描方法及装置
CN106918726A (zh) * 2015-12-24 2017-07-04 英业达科技有限公司 适用于串行ata连接器的测试电路板
CN106918750A (zh) * 2015-12-24 2017-07-04 英业达科技有限公司 适用于内存插槽的测试电路板
CN106918725A (zh) * 2015-12-25 2017-07-04 英业达科技有限公司 具联合测试工作群组信号串接电路设计的测试电路板

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