WO2011091750A1

WO2011091750A1 - Method for scanning boundary inside single board，device and single board thereof

Info

Publication number: WO2011091750A1
Application number: PCT/CN2011/070643
Authority: WO
Inventors: 曾文虹
Original assignee: 华为技术有限公司
Priority date: 2010-01-27
Filing date: 2011-01-26
Publication date: 2011-08-04
Also published as: CN101776728B; CN101776728A

Abstract

Provided is a method for scanning boundary scanning inside single board, device and single board. The single board comprises a first programmable logic device (PLD), a device to be detected and a first JTAG Jacket, wherein the first JTAG Jacket and the JTAG pin of the device to be detected are receptively connected with the input pin Bank and the output pin Bank of the first programmable logic device; and an operation level of the input and output pin Banks equals to that of the devices connecting with the pin Banks. The method comprises the following steps of: serially connecting the device to be detected with the first JTAG Jacket through the first PLD; receiving a JTAG detection signal from the first JTAG Jacket; and carrying out the boundary scan on the device to be detected serially connected.

Description

Boundary scanning method, device and single board of the device in the board The application is submitted to the Chinese Patent Office on January 27, 2010, and the application number is 201 01 01 04402. 8. The invention name is "Boundary scanning of the device in the board" The priority of the Chinese Patent Application, the entire disclosure of which is incorporated herein by reference. The present invention relates to the field of communications, and in particular, to a boundary scan method, device, and board for a device in a single board.

BACKGROUND OF THE INVENTION Digital hardware boards currently designed have high density, more powerful functions, and a wide variety of devices in the board. This brings a lot of difficulties and inconvenience to the production and maintenance of the veneer. In order to test the devices in the board, the prior art provides a universal detection method for the devices in the single board. The method uses the Joint Test Action Group (JTAG) to detect the devices in the board, and the JTAG is initially used. It is used to test the chip. The basic principle of JTAG is to define a Test Access Port (TAP) inside the device to test the internal nodes through a dedicated JTAG test tool. JTAG test allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, which can be tested separately for each device. Therefore, in JTAG technology, the JTAG pins of each device on the board need to be connected in series to form a scan chain. Perform a boundary scan on the devices on the scan chain.

In the process of implementing the present invention, the inventors have found that the prior art has the following problems: In the prior art solution, if there are many devices in the single board, the connection relationship between the JTAG pins of the device will be complicated.

Summary of the invention

In order to simplify the connection between JTAG pins, an aspect of the present invention provides a boundary scan method for devices in a single board, the board including a first programmable logic device PLD, to be Detecting device and first JTAG Jacket; wherein the first JTAG Jacket and the JTAG pin of the device to be detected are respectively connected to an input/output pin Bank of the first programmable logic device; Flattening the operating level of the device to which it is connected, the method includes:

And connecting, by the first PLD, the device to be detected in series with the first JTAG Jacket; receiving a JTAG detection signal from the first JTAG Jacket, performing boundary scan on the serially detected device to be detected.

In another aspect of the present invention, a boundary scan device for a device in a single board is provided, including: a first programmable logic device PLD, a device to be detected, and a first JTAG Jacket; wherein the first JTAG Jacket and the The JTAG pins of the detecting device are respectively connected to the input and output pin banks of the first programmable logic device; the working level of the bank is the working level of the connected device.

In still another aspect of the present invention, a single board is provided, including the above-described boundary scanning device. It can be seen from the technical solution provided by the foregoing that, in the technical solution of the embodiment of the present invention, the JTAG pin of the device to be detected and the JTAG PLD are connected, and the bank working level of the JTAG PLD can be adjusted to be connected to the device on the bank. The working level, thus eliminating the need for an additional level shifting circuit, simplifies the JTAG pin connection of the device to be tested, thereby simplifying the BOM list; and the detection signal is transmitted through the JTAG PLD, and the detection signal is transmitted at a short distance. , the signal quality is good.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic flow chart of a boundary scan method for a device in a single board according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a device in a single board according to another embodiment of the present invention; FIG. 3 is a schematic flowchart of a boundary scan method of a device in a single board according to an embodiment of the present invention;

4 is a schematic structural diagram of a device in a board after a device to be detected is changed in a boundary scan method of a device in a single board according to an embodiment of the present disclosure; FIG. 5 is a schematic structural diagram of a device in a single board in which a boot load is implemented in a boundary scan method of a device in a single board according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention provide a boundary scan method for a device in a single board. The single board includes a first programmable logic device (PLD), such as an erasable editable logic device (Erasable Programmable Logic Device). , EPLD), CPLD, Field Programmable Gate Array (FPGA), etc. For convenience of description, the first PLD in the following description takes JTAG EPLD as an example for description.

Those skilled in the art will appreciate that in order to facilitate management and adaptation to a variety of electrical standards, resources in a logical device can be divided into groups or blocks, which are referred to as banks.

In this implementation, the board includes a JTAG EPLD, the device to be detected and the first JTAG Jacket; wherein the JTAG pin of the device to be detected, and the first JTAG Jacket are respectively connected to the input and output pin Bank of the JTAG EPLD; The working level of the bank is the working level of the device connected to the bank. The JTAG Jacket is a JTAG socket and can be connected to the JTAG test device. In the flow diagram shown in Figure 1, the following steps are included:

511. Connect the device to be tested in series with the first JTAG Jacket through JTAG EPLD.

One or more (two or more) devices can be selected from the device to be tested, with JTAG

The Jacket is connected in series to form a JTAG scan chain. The chained solution can be implemented in the EPLD programming language, such as Verilog. Under the control of the CPU, the CPU can form different scan chains by configuring the registers in the JTAG EPLD.

512. Receive a JTAG detection signal from the first JTAG Jacket, and perform boundary scan on the serially detected device.

The Bank can be a pair of pins in the JTAG EPLD. The device to be tested can be an electronic device that needs to be detected in a single board, such as a CPU or an FPGA.

Optionally, the board may further include a second JTAG Jacket, where the second JTAG Jacket is connected to a JTAG pin of the JTAG EPLD, and the second JTAG Jacket is a JTAG EPLD. Load the software online. The above method for loading software on the JTAG EPLD is actually that the software loading device is connected to the JTAG EPLD through the second JTAG Jacket, and the online loading software for the JTAG EPLD is completed.

The above software loading device can be a CPU or JTAG debugging instrument, and the like.

In the method provided in this embodiment, the JTAG pin of the device to be tested is connected to the JTAG EPLD. Since the bank working level of the JTAG EPLD can be adjusted to the operating level of the device connected to the bank, no additional level is needed. The conversion circuit can simplify the connection relationship of the JTAG pins of the device to be tested, thereby simplifying the BOM list; and the detection signals are all transmitted through the JTAG EPLD, the detection signal transmission distance is short, and the signal quality is good; further, the device to be detected The connection method can be realized by software, so there is no need to change the solder joint of the device, and the chaining method is more flexible.

The method provided by another embodiment of the present invention may be applied to a single board as shown in FIG. 2, and the device in the single board may specifically include: JTAG EPLD 21 (the JTAG EPLD here has passed the second JTAG Jacket (in the figure) Not shown) the loading of the software is completed), the first JTAG Jacket 22, the DSP 23, the Application Specific Integrated Circuit (ASIC) 24, the first integrated circuit (IC) device 25, the CPU 26, the PLD 27 , the FPGA 28 and the second IC device 29; wherein, the DSP 23, the ASIC 24, the first IC device 25, the CPU 26, the PLD 27, the FPGA 28, and the second IC device 29 may be devices to be detected; the above JTAG EPLD 21 and the first JTAG Jacket 22. The working level of the bank connected to the first IC device, CPU26, PLD27, and FPGA28 is 3.3V. The working level of the bank connected to the second IC device in JTAG EPLD21 is 2.5V. The JTAG EPLD21 is connected to DSP23 and ASIC24. The working level of the Bank is 1.8V; it should be noted that the first JTAG Jacket 22, DSP23, ASIC 24, first IC device 25, CPU 26, PLD 27, FPGA 28 and second IC are mentioned above. The pin connected to JTAG EPLD21 is the JTAG pin.

In the flow diagram shown in Figure 3, the following steps are included:

S31. The device to be detected in the board and the first JTAG Jacket 22 through the JTAG EPLD 21 In series.

The specific method for implementing S31 may be that the DSP 23, the ASIC 24, the first IC device, the CPU 26, the EPLD 27, the FPGA 28, the second IC device 29, and the first JTAG Jacket 22 are sequentially connected in series through the JTAG EPLD 21; The series may also be connected in series without the above sequence, and the series only needs to include all the devices to be detected. The method of implementing the above series connection can be referred to the related description in S11.

Optionally, in actual situations, the device to be detected may also be a single device, such as separately detecting the CPU. In this case, the first JTAG Jacket and the CPU need only be connected in series.

532. The JTAG EPLD21 receives the detection signal from the first JTAG Jacket22, and the device to be detected transmits the detection signal in series, and completes the detection of the device to be detected.

The specific step of completing S32 may include: the first JTAG Jacket22 sends a detection signal to the CPU 26 through the JTAG EPLD 21, and if the CPU 26 detects normal, the detection signal is transmitted to the PLD 27 through the JTAG EPLD 21, and if the PLD 27 detects normal, the detection signal passes the JTAG. The EPLD 21 is passed to the first IC device. If the first IC device detects normal, the detection signal is passed through the JTAG EPLD 21 to the next device until all devices have been detected.

Optionally, when the detection of the device to be detected is completed, and the changed device to be detected needs to be detected, the FPGA 28 is taken as an example for description, and after the device to be detected is changed to the FPGA 28, the internal device of the single board is The structure is shown in FIG. 4. In the schematic diagram of the process shown in FIG. 3, the method may further include:

533. Connect the first JTAG Jacket22 in series with FPGA28 via JTAG EPLD21.

534. The first JTAG Jacket22 sends a detection signal to the FPGA 28 through JTAG EPLD21 to complete the detection.

In addition, optionally, after the S32, the foregoing method may further include: controlling the PLD 27 to complete the loading of the booting program, and the device structure diagram of the board loaded in the booting is as shown in FIG. 5, and the loading process is as follows:

535. Connect the PLD27 to the CPU 26 via JTAG EPLD21 and also pass JTAG. The EPLD 21 connects the PLD 27 to the first JTAG Jacket 22.

After receiving the loading command of the CPU 26 and the loading command of the first JTAG Jacket22, the STAG and the JTAG EPLD 21 select a control PLD 27 from the CPU 26 and the first JTAG Jacket 22 according to the selection command to complete the loading of the board boot.

If the selection command is used to select the first JTAG Jacket22, the method of completing the S36 may include: the first JTAG Jacket22 sends a load command to the JTAG EPLD21, and the JTAG EPLD21 sends the load command to the PLD27 to control the PLD27 to complete the loading of the board boot.

The method of selecting the CPU 26 is as follows. The method for completing the S36 may include: the CPU 26 sends a control command to the JTAG EPLD 21, and the JTAG EPLD 21 sends the load command to the PLD 27 to control the loading of the board by the PLD 27.

The specific implementation manner of the loading command of the JTAG EPLD receiving CPU and the loading command of the first JTAG Jacket may be: the loading command sent by the JTAG EPLD receiving CPU and the first JTAG Jacket, or the first being forwarded by the CPU by the JTAG EPLD. The JTAG Jacket's load command and its own load command sent by the CPU.

Further, before the step S31, the method provided in this embodiment may further include loading the JTAG EPLD online by using a JTAG pin of the JTAG EPLD.

For example, the JTAG pin of the JTAG EPLD is connected to the JTAG Jacket. After the JTAG EPLD is powered on or reset, the JTAG EPet is used to control the JTAG EPLD online loading software.

The invention also provides a detecting device for a device in a single board, comprising: a first PLD, to be detected a device and a first JTAG Jacket; wherein the first JTAG Jacket and the JTAG pin of the device to be detected are respectively connected to the input and output pin Bank of the first PLD; and the working level of the bank is the device connected thereto The working level.

Optionally, the foregoing apparatus further includes:

a series unit for connecting the device to be detected in series with the first JTAG Jacket by the first PLD.

For the specific implementation of the above series, refer to the related description in S11.

When the series is completed, the first JTAG Jacket completes the boundary scan of the device to be detected through the first PLD.

Optionally, the device to be detected is at least two.

Optionally, the device to be detected includes: a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD, and the second PLD is connected to the first JTAG Jacket through the first PLD; Includes:

The loading unit is configured to: after the first PLD receives the loading command of the CPU and the loading command of the first JTAG Jacket, select a control from the CPU and the first JTAG Jacket according to the selection command to complete loading of the board boot.

Optionally, the board further includes: a second JTAG Jacket, where the second JTAG Jacket is connected to the JTAG pin of the first PLD, and is used to load the first PLD online software by using the second JTAG Jacket.

For a specific implementation of the online software loading, refer to the related description in the foregoing method embodiments. In the device provided in this embodiment, all the JTAG pins of the device to be detected are connected to the first PLD, because the bank working level of the first PLD can be adjusted to the operating level of the device connected to the bank. Therefore, no additional level conversion circuit is needed, which can simplify the connection relationship of the JTAG pins of the device to be detected, thereby simplifying the BOM list; and the detection signals are transmitted through the first PLD, and the detection signal transmission distance is short, the signal quality Further, further, the connection mode of the device to be tested can be implemented by software, so there is no need to change the solder joint of the device. The chaining method is more flexible.

Embodiments of the present invention also provide a single board, which may include the boundary scan device provided by the above embodiment, and various devices to be detected connected to the boundary scan device. Optionally, the boundary scan device can be implemented by using an EPLD, and the connection manner of the device to be tested and the JTAG EPLD can be referred to the solution disclosed in the foregoing embodiment, and details are not described herein.

A person skilled in the art can understand that the drawings are only a schematic diagram of a preferred embodiment, and the modules or processes in the drawings are not necessarily required to implement the invention.

A person skilled in the art can understand that all or part of the steps of implementing the foregoing embodiments may be performed by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, when executed, Include one of the steps of the method embodiments or a combination thereof.

In summary, the technical solution provided by the specific embodiment of the present invention has the advantages of simple connection relationship between the detection devices in the single board, short detection signal transmission distance, good signal quality, less BOM list, and flexible chaining mode.

The embodiments of the present invention have been described in detail above, and the principles and implementations of the present invention have been described with reference to specific examples. The description of the above embodiments is only for helping to understand the method of the present invention and its core ideas; The present invention is not limited by the scope of the present invention, and the details of the present invention are not limited by the scope of the present invention.

Claims

Rights request

A boundary scan method for a device in a single board, wherein the single board includes a first programmable logic device PLD, a device to be detected, and a first joint test action group socket JTAG Jacket; wherein the first JTAG a Jacket and a JTAG pin of the device to be detected are respectively connected to an input/output pin bank of the first programmable logic device; an operating level of the bank is an operating level of the connected device, and the method includes :

2. The method according to claim 1, wherein the device to be detected is at least two.

The method according to any one of claims 1 to 2, wherein the device to be detected further includes a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD. The second PLD is further connected to the first JTAG Jacket by using the first PLD, and the method further includes:

After receiving the loading command of the CPU and the loading command of the first JTAG Jacket, the first PLD selects one of the CPU and the first JTAG Jacket to control the second PLD completion list according to the selection command. The board launcher Boot loads.

The method according to claim 3, wherein the selecting, by the selecting one of the CPU and the first JTAG Jacket, the loading of the second PLD to complete the loading of the board includes:

The CPU sends a load command to the second PLD through the first PLD, and controls loading of the board by the second PLD by using the load command.

Or the first JTAG Jacket sends a load command to the second PLD by using the first PLD, and controls the loading of the board by the second PLD by using the load command.

5. The method according to any one of claims 1 - 2, wherein the board is further included The second JTAG Jacket is connected to the JTAG pin of the first PLD, and the method further includes:

Loading software for the first PLD online through the second JTAG Jacket.

6. A boundary scan device for a device in a single board, comprising: a first programmable logic device PLD, a device to be detected, and a first joint test action group socket JTAG Jacket; wherein the first JTAG Jacket and the The JTAG pins of the detection device are respectively connected to the input and output pins of the first programmable logic device; the working level of the bank is the operating level of the connected device.

The device according to claim 6, wherein the device further comprises: a serial unit, configured to connect the device to be detected in series with the first JTAG Jacket by using the first PLD.

The device according to any one of claims 6 or 7, characterized in that the device to be detected is at least two.

The device according to claim 6 or 7, wherein the device to be detected further comprises: a CPU and a second PLD, and the second PLD is connected to the CPU through the first PLD, the second The PLD is further connected to the first JTAG Jacket by using the first PLD, and the device further includes:

a loading unit, configured to select a control station from the CPU and the first JTAG Jacket according to a selection command after the first PLD receives the loading command of the CPU and the loading command of the first JTAG Jacket The second PLD completes the loading of the board boot program Boot.

The device according to claim 6, wherein the device further comprises: a second JTAG Jacket, the second JTAG Jacket is connected to a JTAG pin of the first PLD, and the second JTAG is connected Jacket loads the software for the first PLD online.

A veneer comprising the apparatus of any of claims 6-10.