CN101776728A - Boundary scanning method and device of device inside single plate - Google Patents
Boundary scanning method and device of device inside single plate Download PDFInfo
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- CN101776728A CN101776728A CN201010104402A CN201010104402A CN101776728A CN 101776728 A CN101776728 A CN 101776728A CN 201010104402 A CN201010104402 A CN 201010104402A CN 201010104402 A CN201010104402 A CN 201010104402A CN 101776728 A CN101776728 A CN 101776728A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
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Abstract
The invention provides boundary scanning method and device of a device inside a single plate, belonging to the field of network communication. The single plate comprises a first programmable logic device (PLD), a device to be detected and a first JTAG Jacket, wherein the first JTAG Jacket and a JTAG pin of the device to be detected are receptively connected with an input and output pin Bank of the first programmable logic device (PLD); and an operation level of the input and output pin Bank is an operation level of a connecting device of the input and output pin Bank. The boundary scanning method comprises the following steps of: serially connecting the device to be detected with the first JTAG Jacket; receiving a JTAG detection signal from the first JTAG Jacket; and carrying out boundary scan on the series-connected device to be detected. The invention has the advantages of simple connection relation of the device to be detected inside the single plate, short transmission distance of the detecting signal, good signal quality, few bill of material (BOM) lists and flexible chaining way.
Description
Technical field
The present invention relates to the communications field, relate in particular to the boundary scanning method and the device of device in a kind of veneer.
Background technology
The digital hardware veneer density of design is very high at present, and function is more powerful, and part category is various in the plate.This safeguards just for the production of veneer and brings a lot of difficulties and inconvenience.For the device in the veneer is tested, prior art provides device general detection method in a kind of veneer, this method adopts boundary scan technique (Joint Test Action Group, JTAG) device in the veneer is detected, JTAG is used for chip is tested at first, the ultimate principle of JTAG is that (Test Access Port TAP) tests carrying out internal node by the jtag test instrument of special use at test access mouth of device inside definition.Jtag test allows a plurality of devices to be cascaded by jtag interface, forms a JTAG chain, can realize each device is tested respectively, so in the JTAG technology, the JTAG pin series connection of each device on the veneer need be formed scan chain, and then the device on the scan chain is finished boundary scan.
In realizing process of the present invention, the inventor finds prior art, and there are the following problems:
The scheme of prior art, if the device in the veneer is more, the annexation between the JTAG pin of device will be complicated.
Summary of the invention
In order to simplify the annexation between the JTAG pin, an aspect of of the present present invention provides the boundary scanning method of device in a kind of veneer, and described veneer comprises the first programmable logic device (PLD) PLD, device to be detected and a JTAG Jacket; The JTAG pin of a wherein said JTAG Jacket and described device to be detected is connected on the input and output pin Bank of described first programmable logic device (PLD); The operation level of described Bank is the operation level of its interface unit, and described method comprises:
By a described PLD described device to be detected is connected with a described JTAG Jacket;
Receive the JTAG detection signal from a described JTAG Jacket, the device to be detected of described series connection is carried out boundary scan.
Another aspect of the present invention provides the boundary scan device of device in a kind of veneer, comprising: the first programmable logic device (PLD) PLD, device to be detected and a JTAG Jacket; The JTAG pin of a wherein said JTAGJacket and described device to be detected is connected on the input and output pin Bank of described first programmable logic device (PLD); The operation level of described Bank is the operation level of its interface unit.
By the above-mentioned technical scheme that provides as can be seen, the JTAG pin of the technical scheme device to be detected of the embodiment of the invention is connected with JTAG EPLD, because the Bank operation level of JTAG EPLD can be adjusted to the operation level that is connected the device on this Bank, thereby do not need extra level shifting circuit, the annexation of the JTAG pin of device to be detected can be simplified, and then the BOM inventory can be simplified; And this detection signal all sends by JTAG EPLD, and the distance that detection signal transmits is short, and signal quality is good.
Description of drawings
The schematic flow sheet of the boundary scanning method of device in a kind of veneer that Fig. 1 provides for one embodiment of the invention;
The structural representation of device in a kind of veneer that Fig. 2 provides for another embodiment of the present invention;
The schematic flow sheet of the boundary scanning method of device in a kind of veneer that Fig. 3 provides for one embodiment of the invention;
Change the structural representation of device in the veneer behind the device to be detected in a kind of veneer that Fig. 4 provides for one embodiment of the invention in the boundary scanning method of device;
Realize the structural representation of device in the veneer when Boot loads in a kind of veneer that Fig. 5 provides for one embodiment of the invention in the boundary scanning method of device;
Embodiment
Embodiment of the present invention provides the boundary scanning method of device in a kind of veneer, veneer comprises first programmable logic device (PLD) (Programmable Logic Device, PLD), but as wiping editorial logic device (Erasable Programmable Logic Device, EPLD), CPLD, field programmable gate array (FieldProgrammable Gate Array, FPGA) etc., for the convenience of describing, a PLD is that example describes with JTAG EPLD in the following narration.
In this enforcement, veneer comprises JTAG EPLD, device to be detected and a JTAG Jacket; The wherein JTAG pin of this device to be detected, an and JTAG Jacket is connected on the input and output pin Bank of this JTAGEPLD; And the operation level of this Bank is the operation level that is connected the device on this Bank, and above-mentioned JTAG Jacket is being the JTAG socket, can be connected with jtag test equipment.In schematic flow sheet as shown in Figure 1, comprise the steps:
S11, device to be detected is connected with a JTAG Jacket by JTAG EPLD;
Can select one or more (more than two or two) device from device to be detected, connecting with JTAG Jacket forms the JTAG scan chain.Wherein the scheme of chaining can adopt the EPLD programming language to realize, as Verilog; Under the control of CPU, by the register in the configuration JTAG EPLD, just can form different scan chains as CPU.
S12, receive the JTAG detection signal, the device to be detected of this series connection is carried out boundary scan from a JTAG Jacket.
Above-mentioned Bank can be a pair of pin among the JTAG EPLD, and above-mentioned device to be detected can be the electron device that needs in the veneer to detect, as CPU, FPGA etc.
Optionally, above-mentioned veneer can also comprise the 2nd JTAG Jacket, and the 2nd JTAG Jacket links to each other with the JTAG pin of JTAG EPLD, is JTAG EPLD on-line loaded software by described the 2nd JTAG Jacket.Above-mentioned method to JTAG EPLD on-line loaded software is actual to be, the software loading device links to each other with JTAG EPLD by the 2nd JTAG Jacket, and finishes the on-line loaded software to JTAG EPLD.
Above-mentioned software loading device can be CPU or JTAG adjusting instrument etc.
In the method that present embodiment provides, the JTAG pin of device to be detected is connected with JTAG EPLD, because the Bank operation level of JTAG EPLD can be adjusted to the operation level that is connected the device on this Bank, thereby do not need extra level shifting circuit, the annexation of the JTAG pin of device to be detected can be simplified, and then the BOM inventory can be simplified; And this detection signal all sends by JTAG EPLD, and the distance that detection signal transmits is short, and signal quality is good; Further, the connected mode of device to be detected can realize that so do not need to change the pad of device, the chaining mode is more flexible by software.
The method that another embodiment of the present invention provides, can be applied in the veneer as shown in Figure 2, device specifically can comprise in this veneer: JTAG EPLD 21 (the JTAG EPLD has here finished the loading of software by the 2nd JTAG Jacket (not drawing among the figure)), a JTAG Jacket 22, DSP23, special IC 24 (Application Specific Integrated Circuit, ASIC), first integrated circuit (Integrated Circuit, IC) device 25, CPU 26, PLD 27, FPGA 28 and the 2nd IC device 29; Wherein, DSP23, ASIC24, an IC device 25, CPU26, PLD27, FPGA 28 and the 2nd IC device 29 can be device to be detected; The operation level of the Bank that links to each other with a JTAG Jacket22, an IC device, CPU26, PLD27, FPGA28 among the above-mentioned JTAG EPLD21 is 3.3V; The operation level of the Bank that links to each other with the 2nd IC device among the JTAGEPLD21 is 2.5V; The operation level of the Bank that links to each other with DSP23, ASIC24 among the JTAG EPLD21 is 1.8V; Need to prove that an above-mentioned JTAGJacket 22, DSP23, ASIC24, an IC device 25, CPU 26, PLD 27, FPGA 28 and the pin that the 2nd IC device 29 links to each other with JTAG EPLD21 are the JTAG pin.
In schematic flow sheet as shown in Figure 3, comprise the steps:
S31, device to be detected in the veneer is connected with a JTAG Jacket 22 by JTAG EPLD 21;
Realize S31 concrete grammar can for, by JTAG EPLD 21 DSP23, ASIC24, an IC device, CPU 26, EPLD27, FPGA28, the 2nd IC device 29 and a JTAG Jacket 22 are connected in order; Certainly in actual conditions, this series connection also can be connected not according to said sequence, and this series connection only need comprise that all devices to be detected get final product.The method that realizes above-mentioned series connection can be referring to the associated description among the S11.
Optionally, in actual conditions, this device to be detected can also be individual devices, as separately CPU being detected, at this moment, only needs a JTAG Jacket and CPU series connection are got final product.
S32, JTAG EPLD21 receive detection signal from a JTAG Jacket22, and device to be detected is sent detection signal by series sequence, finish device to be detected is detected.
The concrete steps of the above-mentioned S32 of finishing can comprise: a JTAG Jacket22 sends to CPU26 by JTAG EPLD21 with detection signal, detect normal as CPU26, then this detection signal is delivered to PLD27 by JTAGEPLD21, detect normal as PLD27, then this detection signal is delivered to an IC device by JTAG EPLD21, detect as an IC device normal, then this detection signal by JTAG EPLD21 be delivered to next device until all devices all detect finish till.
Optionally, after the detection of finishing device to be detected, when also needing the device to be detected after changing detected, here be that example describes with FPGA28, after device to be detected changed over FPGA28, the structural representation of the interior device of veneer as shown in Figure 4, in schematic flow sheet as shown in Figure 3, this method can also comprise:
S33, the one JTAG Jacket22 is connected with FPGA28 by JTAG EPLD21;
S34, a JTAG Jacket22 send to FPGA28 by JTAG EPLD21 with detection signal and finish detection.
In addition, optionally, after S32, said method can also comprise that control PLD27 finishes the loading of start-up routine Boot, realizes in the veneer of loading of Boot device architecture figure as shown in Figure 5, the following operation of loading procedure:
S35, PLD27 is connected with CPU26 by JTAG EPLD21, and also passes through JTAG EPLD21 PLD27 is connected with a JTAG Jacket22;
After S36, JTAG EPLD21 receive the loading command of the loading command of CPU26 and a JTAG Jacket22, from a CPU26 and a JTAG Jacket22, select a control PLD27 to finish loading to board B oot according to select command.
Select a JTAG Jacket22 as above-mentioned select command, the method of then finishing S36 can comprise: a JTAG Jacket22 sends to JTAG EPLD21 with loading command, and JTAG EPLD21 sends to PLD27 with this loading command and finishes loading to board B oot with control PLD27.
Select CPU26 as above-mentioned select command, the method for then finishing S36 specifically can comprise: CPU26 sends to JTAG EPLD21 with control command, and JTAG EPLD21 sends to PLD27 with this loading command and finishes loading to board B oot with control PLD27.
The specific implementation of the loading command of above-mentioned JTAG EPLD reception CPU and the loading command of a JTAG Jacket can be, JTAG EPLD receives the loading command that CPU and a JTAG Jacket send respectively, the loading command of himself that also can be that JTAG EPLD receives the loading command of a JTAG Jacket who is transmitted by CPU and CPU sends.
Further, before step S31, the method that present embodiment provides can also comprise, the JTAG pin by JTAGEPLD is this JTAG EPLD on-line loaded software.
JTAG pin as JTAG EPLD links to each other with JTAG Jacket, after JTAG EPLD powers on or resets, by this JTAG Jacket control JTAG EPLD on-line loaded software.
In the method that present embodiment provides, the JTAG pin of device to be detected is connected with JTAG EPLD, because the Bank operation level of JTAG EPLD can be adjusted to the operation level that is connected the device on this Bank, thereby do not need extra level shifting circuit, the annexation of the JTAG pin of device to be detected can be simplified, and then the BOM inventory can be simplified; And this detection signal all sends by JTAG EPLD, and the distance that detection signal transmits is short, and signal quality is good; Further, the connected mode of device to be detected can realize that so do not need to change the pad of device, the chaining mode is more flexible by software.
The present invention also provides the pick-up unit of device in a kind of veneer, comprising: a PLD, device to be detected and a JTAG Jacket; Wherein the JTAG pin of a JTAG Jacket and this device to be detected is connected on the input and output pin Bank of a PLD; And the operation level of Bank is for connecting the operation level of device thereon.
Optionally, said apparatus also comprises:
Series unit is used for by a described PLD described device to be detected being connected with a described JTAGJacket.
The specific implementation of above-mentioned series connection can be referring to the associated description among the S11.
After finishing series connection, a JTAG Jacket finishes the boundary scan for the treatment of detection means by a PLD.
Optionally, above-mentioned device to be detected is at least two.
Optionally, device to be detected as described comprises: CPU and the 2nd PLD, and the 2nd PLD is connected with CPU by a PLD, also passes through a PLD the 2nd PLD is connected with a JTAG Jacket; Said apparatus also comprises:
Loading unit is used for after a PLD receives the loading command of the loading command of CPU and a JTAG Jacket, selects control the 2nd PLD to finish loading to board B oot from a CPU and a JTAG Jacket according to select command.
Optionally, above-mentioned veneer also comprises: the 2nd JTAG Jacket, the 2nd JTAG Jacket is connected with the JTAG pin of a PLD, and to be used for by the 2nd JTAG Jacket be the online software loading of a PLD.
The specific implementation of online software loading can be referring to the associated description among the said method embodiment.
In the device that present embodiment provides, the JTAG pin of all devices to be detected all is connected with a PLD, because the Bank operation level of a PLD can be adjusted to the operation level that is connected the device on this Bank, thereby do not need extra level shifting circuit, the annexation of the JTAG pin of device to be detected can be simplified, and then the BOM inventory can be simplified; And this detection signal all sends by a PLD, and the distance that detection signal transmits is short, and signal quality is good; Further, the connected mode of device to be detected can realize that so do not need to change the pad of device, the chaining mode is more flexible by software.
It will be appreciated by those skilled in the art that accompanying drawing is the synoptic diagram of a preferred embodiment, module in the accompanying drawing or flow process might not be that enforcement the present invention is necessary.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method can instruct relevant hardware to finish by program, described program can be stored in a kind of computer-readable recording medium, this program comprises one of step or its combination of method embodiment when carrying out.
In sum, the technical scheme that the specific embodiment of the invention provides, it is simple to have veneer internal detector spare annexation, and the detection signal transmitting range is short, and signal quality is good, and the BOM inventory is few, and the chaining mode is advantage flexibly.
More than the embodiment of the invention is described in detail, used specific case herein principle of the present invention and embodiment set forth, the explanation of above embodiment just is used for help understanding method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. the boundary scanning method of the interior device of veneer is characterized in that described veneer comprises the first programmable logic device (PLD) PLD, device to be detected and a JTAG Jacket; The JTAG pin of a wherein said JTAG Jacket and described device to be detected is connected on the input and output pin Bank of described first programmable logic device (PLD); The operation level of described Bank is the operation level of its interface unit, and described method comprises:
By a described PLD described device to be detected is connected with a described JTAG Jacket;
Receive the JTAG detection signal from a described JTAG Jacket, the device to be detected of described series connection is carried out boundary scan.
2. method according to claim 1 is characterized in that, described device to be detected is at least two.
3. according to the described arbitrary method of claim 1-2, it is characterized in that, device to be detected as described comprises CPU and the 2nd PLD, and described the 2nd PLD is connected with described CPU by a described PLD, the 2nd PLD also is connected with a described JTAG Jacket by a described PLD, and described method also comprises:
After a described PLD receives the loading command of the loading command of described CPU and a described JTAG Jacket, from a described CPU and a described JTAG Jacket, select described the 2nd PLD of control to finish the loading of single board starting program Boot according to select command.
4. method according to claim 3 is characterized in that, the described loading of selecting described the 2nd PLD of control to finish board B oot from a described CPU and a described JTAG Jacket according to select command comprises:
Described CPU sends loading command by a described PLD to described the 2nd PLD, and controls the loading that described the 2nd PLD finishes board B oot by described loading command;
Or a described JTAG Jacket sends loading command by a described PLD to described the 2nd PLD, and controls the loading that described the 2nd PLD finishes board B oot by described loading command.
5. according to the described arbitrary method of claim 1-2, it is characterized in that described veneer also comprises: the 2nd JTAG Jacket, described the 2nd JTAG Jacket is connected with the JTAG pin of a described PLD, and described method also comprises:
By described the 2nd JTAG Jacket is a described PLD on-line loaded software.
6. the boundary scan device of the interior device of veneer is characterized in that, comprising: the first programmable logic device (PLD) PLD, device to be detected and a JTAG Jacket; The JTAG pin of a wherein said JTAG Jacket and described device to be detected is connected on the input and output pin Bank of described first programmable logic device (PLD); The operation level of described Bank is the operation level of its interface unit.
7. device according to claim 6 is characterized in that, described device also comprises:
Series unit is used for by a described PLD described device to be detected being connected with a described JTAGJacket.
8. according to the described device in one of claim 6 or 7, it is characterized in that described device to be detected is at least two.
9. according to claim 6 or 7 described devices, it is characterized in that, device to be detected as described comprises: CPU and the 2nd PLD, and described the 2nd PLD is connected with CPU by a described PLD, the 2nd PLD also is connected with a JTAG Jacket by a described PLD, and then described device also comprises:
Loading unit, be used for after a described PLD receives the loading command of the loading command of described CPU and a described JTAG Jacket, from a described CPU and a described JTAG Jacket, select described the 2nd PLD of control to finish the loading of single board starting program Boot according to select command.
10. device according to claim 6, it is characterized in that, described device also comprises: the 2nd JTAGJacket, described the 2nd JTAG Jacket is connected with the JTAG pin of a described PLD, is a described PLD on-line loaded software by described the 2nd JTAG Jacket.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101044028A CN101776728B (en) | 2010-01-27 | 2010-01-27 | Boundary scanning method and device of device inside single plate |
| PCT/CN2011/070643 WO2011091750A1 (en) | 2010-01-27 | 2011-01-26 | Method for scanning boundary inside single board，device and single board thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101044028A CN101776728B (en) | 2010-01-27 | 2010-01-27 | Boundary scanning method and device of device inside single plate |
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| Publication Number | Publication Date |
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| CN101776728A true CN101776728A (en) | 2010-07-14 |
| CN101776728B CN101776728B (en) | 2012-07-04 |
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| CN2010101044028A Active CN101776728B (en) | 2010-01-27 | 2010-01-27 | Boundary scanning method and device of device inside single plate |
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| CN (1) | CN101776728B (en) |
| WO (1) | WO2011091750A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011091750A1 (en) * | 2010-01-27 | 2011-08-04 | 华为技术有限公司 | Method for scanning boundary inside single board，device and single board thereof |
| CN106918750A (en) * | 2015-12-24 | 2017-07-04 | 英业达科技有限公司 | Suitable for the test circuit plate of memory bank |
| CN106918725A (en) * | 2015-12-25 | 2017-07-04 | 英业达科技有限公司 | Tool joint test work group signal concatenates the test circuit plate of circuit design |
| CN106918726A (en) * | 2015-12-24 | 2017-07-04 | 英业达科技有限公司 | Suitable for the test circuit plate of serial ATA connector |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4401039B2 (en) * | 2001-06-13 | 2010-01-20 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
| US7191265B1 (en) * | 2003-04-29 | 2007-03-13 | Cisco Technology, Inc. | JTAG and boundary scan automatic chain selection |
| JP4450787B2 (en) * | 2005-11-28 | 2010-04-14 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| CN101071155A (en) * | 2006-05-08 | 2007-11-14 | 中兴通讯股份有限公司 | Device and method for realizing border-scanning multi-link test |
| CN100573175C (en) * | 2006-07-31 | 2009-12-23 | 大唐移动通信设备有限公司 | Multifunctional combined testing moving group chain device |
| CN101529388B (en) * | 2007-03-08 | 2012-05-09 | 中兴通讯股份有限公司 | Test method for non-boundary scan digital device |
| CN101105782B (en) * | 2007-08-22 | 2011-08-24 | 中兴通讯股份有限公司 | Border scanning system based on high-performance computer communication framework and method therefor |
| CN101183139B (en) * | 2007-11-02 | 2010-12-08 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101776728B (en) * | 2010-01-27 | 2012-07-04 | 华为技术有限公司 | Boundary scanning method and device of device inside single plate |
-
2010
- 2010-01-27 CN CN2010101044028A patent/CN101776728B/en active Active
-
2011
- 2011-01-26 WO PCT/CN2011/070643 patent/WO2011091750A1/en active Application Filing
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011091750A1 (en) * | 2010-01-27 | 2011-08-04 | 华为技术有限公司 | Method for scanning boundary inside single board，device and single board thereof |
| CN106918750A (en) * | 2015-12-24 | 2017-07-04 | 英业达科技有限公司 | Suitable for the test circuit plate of memory bank |
| CN106918726A (en) * | 2015-12-24 | 2017-07-04 | 英业达科技有限公司 | Suitable for the test circuit plate of serial ATA connector |
| CN106918725A (en) * | 2015-12-25 | 2017-07-04 | 英业达科技有限公司 | Tool joint test work group signal concatenates the test circuit plate of circuit design |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101776728B (en) | 2012-07-04 |
| WO2011091750A1 (en) | 2011-08-04 |
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