CN110133486A - The pin of FPGA bridges short circuit test method - Google Patents
The pin of FPGA bridges short circuit test method Download PDFInfo
- Publication number
- CN110133486A CN110133486A CN201910509147.6A CN201910509147A CN110133486A CN 110133486 A CN110133486 A CN 110133486A CN 201910509147 A CN201910509147 A CN 201910509147A CN 110133486 A CN110133486 A CN 110133486A
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- signal
- pin
- short circuit
- test method
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The present invention provides the pins of FPGA a kind of to bridge short circuit test method, including constructing signal excitation module and signal receiving module by the logic unit of FPGA, the signal excitation module includes m signal exciting unit, the signal receiving module includes m signal receiving unit, the m is the natural number greater than 0, the signal exciting unit and signal receiving unit are arranged in a one-to-one correspondence with pin respectively, it is input pattern that the m pins, which are arranged, moving pulse signal is inputted to first signal exciting unit, the access module for receiving the pin of the second signal is arranged to output mode, when a new pin is arranged to the output mode, the then output signal of the m pins of the signal receiving module acquisition, then it is exported using the m output signals as test result.It in the test method, without additional detection instrument, reduces costs, detection successively is completed to the m pins, is not limited by number of pin.
Description
Technical field
The present invention relates to the pins of technical field of integrated circuits more particularly to a kind of FPGA to bridge short circuit test method.
Background technique
Field programmable gate array (Field-Programmable GateArray, FPGA) is used as specific integrated circuit
One of field semi-custom circuit, had not only solved the deficiency of full custom circuit, but also overcame original programmable logic device door
The limited disadvantage of circuit quantity.
The signal of FPGA pin both can be transferred to chip interior through processing by the pin of FPGA, can also be by chip interior
The signal of output is transferred to chip pin through processing, is often used automated test device (Automatic Test in the prior art
Equipment, ATE) bridging fault between the pin of FPGA is detected.
But automated test device has the following problems: on the one hand, automated test device is expensive, makes testing cost
Increase；On the other hand, the limited amount of input/output (Input/Output, IO) pipeline of automated test device meets not
Demand when FPGA number of pin is more.
Therefore, it is necessary to provide the pin bridge joint short circuit test method of novel FPGA a kind of to solve to deposit in the prior art
The above problem.
Summary of the invention
The purpose of the present invention is to provide the pins of FPGA a kind of to bridge short circuit test method, without additional detection work
Tool, reduces costs, while can be avoided the quantity that test method is limited to pin.
To achieve the above object, the pin of the FPGA of the invention bridges short circuit test method, comprising the following steps:
S1: signal excitation module and signal receiving module, the signal excitation module are constructed by the logic unit of FPGA
The signal exciting unit successively to sort including m, the signal receiving module include the m signal receiving units successively to sort,
The m is the natural number greater than 0, and the signal exciting unit and signal receiving unit are arranged in a one-to-one correspondence with pin respectively；
S2: continuously inputting the first signal to m exciting units, makes each exciting unit to corresponding described
Pin transmits first signal, the access module of the m pins is arranged as input pattern；
S3: Xiang Suoshu signal excitation module inputs moving pulse signal, and the moving pulse signal includes one second letter
Number and be more than or equal to m first signals, the moving pulse signal is continuously transmitted from first signal exciting unit
To the described m-th signal exciting unit, wherein the moving pulse signal is in two adjacent signal exciting units
Between transmitted in a manner of once only transmitting first signal or the second signal, and the m signals excitations are single
Member, which also synchronizes first signal or the second signal, passes to the corresponding pin, receives the second signal
The access module of pin be arranged to output mode；
S4: when the access module of a new pin is arranged to the output mode, then the signal connects
The output signal that module acquires the m pins by the m signal receiving units is received, then by the m output signals
It is exported as test result, until completing the detection of the m pins.
The beneficial effects of the present invention are: signal excitation module is constructed by the logic unit of FPGA and signal receives mould
Block detects the bridge joint short circuit of pin by the signal excitation module and the signal receiving module, without additional
Detection instrument reduces costs；Signal excitation module and signal receiving module, the signal are constructed by the logic unit of FPGA
Excitation module includes the m signal exciting units successively to sort, and the signal receiving module includes that the m signals successively to sort connect
Unit is received, the quantity of the signal exciting unit and the signal receiving unit can be determined according to the quantity of the pin, if
The access module for setting the m pins is input pattern, inputs moving pulse signal to first signal exciting unit,
Described in moving pulse signal include being more than or equal to m first signals and a second signal, receive the second signal
The access module of pin be arranged to output mode, whenever the access module of a new pin is arranged to described defeated
Out when mode, then the signal receiving module acquires the output signal of the m pins, until completing the inspection of the m pins
It surveys, is sequentially completed the detection to m pin, is not limited by number of pin.
Preferably, the signal excitation module is Output Shift Register, the beneficial effect is that: the output displacement is posted
Signal in storage shifts transmitting, and it is primary that all pins can be disposed as to output mode, may be implemented to all pins
Detection.
It is further preferred that the signal exciting unit is the position of the Output Shift Register.
Preferably, the signal receiving module is input shift register, the beneficial effect is that: the input displacement is posted
Storage can shift output, so as to export the signal of all pin input terminals, so that it is determined that whether the pin occurs bridge
Connect short circuit.
It is further preferred that the signal receiving unit is the position of the input shift register.
Preferably, it is short to judge whether the pin bridges for the quantity of the second signal according to the test result
Road, the beneficial effect is that: whether the pin can be judged by the quantity of second signal described in the test result
Bridge joint short circuit occurs, accuracy is high.
It is further preferred that the quantity of second signal described in the test result is equal to 1, judge that the pin is not sent out
Raw bridge joint short circuit.
It is further preferred that the quantity of second signal described in the test result is greater than 1, judge that bridge occurs for the pin
Connect short circuit.
Detailed description of the invention
Fig. 1 is that the pin of FPGA of the invention bridges the flow chart of short circuit test method.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing of the invention, to this hair
Technical solution in bright embodiment is clearly and completely described, it is clear that described embodiment is that a part of the invention is real
Example is applied, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creation
Property labour under the premise of every other embodiment obtained, shall fall within the protection scope of the present invention.Unless otherwise defined, make herein
Technical term or scientific term should be persons with general skills in the field understood it is usual
Meaning.The similar word such as " comprising " used herein, which means to occur element or object before the word, to be covered and appears in this
The element of word presented hereinafter perhaps object and its equivalent and be not excluded for other elements or object.
In view of the problems of the existing technology, the embodiment provides the pins of FPGA a kind of to bridge short-circuit test
Method, referring to Fig.1, comprising the following steps:
S1: signal excitation module and signal receiving module, the signal excitation module are constructed by the logic unit of FPGA
The signal exciting unit successively to sort including m, the signal receiving module include the m signal receiving units successively to sort,
The m is the natural number greater than 0, and the signal exciting unit and signal receiving unit are arranged in a one-to-one correspondence with pin respectively；
S2: continuously inputting the first signal to m exciting units, makes each exciting unit to corresponding described
Pin transmits first signal, the access module of the m pins is arranged as input pattern；
S3: Xiang Suoshu signal excitation module inputs moving pulse signal, and the moving pulse signal includes one second letter
Number and be more than or equal to m first signals, the moving pulse signal is continuously transmitted from first signal exciting unit
To the described m-th signal exciting unit, wherein the moving pulse signal is in two adjacent signal exciting units
Between transmitted in a manner of once only transmitting first signal or the second signal, and the m signals excitations are single
Member, which also synchronizes first signal or the second signal, passes to the corresponding pin, receives the second signal
The access module of pin be arranged to output mode；
S4: when the access module of a new pin is arranged to the output mode, then the signal connects
The output signal that module acquires the m pins by the m signal receiving units is received, then by the m output signals
It is exported as test result, until completing the detection of the m pins.
In some specific embodiments of the present invention, the binary numeral of first signal is 1, the two of the second signal
Binary value is 0.
In some embodiments of the present invention, when the pin is output mode, the value of the pin output end is the pipe
Value on foot press point position, i.e., the described second signal.
In some embodiments of the present invention, pin pressure point position is the position that the pin is connected with other devices.
In some embodiments of the present invention, when the pin is input pattern, the input value of the pin is default weak
Pull-up values, the default weak pull-up value are equal to 1.
In some specific embodiments of the present invention, the signal excitation module is Output Shift Register.
In some specific embodiments of the present invention, the signal exciting unit is the position of the Output Shift Register.
In some specific embodiments of the present invention, the signal receiving module is input shift register.
In some specific embodiments of the present invention, the signal receiving unit is the position of the input shift register.
In some embodiments of the present invention, the input terminal of first signal exciting unit connects first output selection
The output end of unit, the input terminal of first output select unit connect the first signal output end and signal pulse output end, the
The input terminal of two output select units connects the output of first signal output end and first signal exciting unit
End, the output end of second output select unit connect the input terminal of second signal exciting unit, third output choosing
The input terminal for selecting unit connects the output end of first signal output end and second signal exciting unit, and third is defeated
The input terminal connection of the output end connection third signal exciting unit of selecting unit out, until m-th of output selection is single
The input terminal of member connects the output end of first signal output end and the m-1 signal exciting units, m-th of output choosing
The output end for selecting unit connects the input terminal of m-th of signal exciting unit.
In some embodiments of the present invention, first signal output end persistently exports the first signal, the signal pulse
Output end exports the moving pulse signal and does not receive when each signal exciting unit receives the moving pulse signal
First signal of the first signal output end output.
In some embodiments of the present invention, the output end of first signal exciting unit connects first pin
Output end and ternary signal select end, the output end of second signal exciting unit connects the defeated of second pin
Outlet and ternary signal select end, until the output end of m-th of signal exciting unit connects the output of m-th of pin
End and ternary signal select end.
In some embodiments of the present invention, the input terminal of first signal receiving unit connects first input selection
The output end of unit, the input terminal of first input selecting unit connect the input terminal of first pin, second input
The input terminal of selecting unit connects the output end of first signal receiving unit and the input terminal of second pin, the
The input terminal of two signal receiving units connects the output end of second input selecting unit, and third inputs selecting unit
Input terminal connect the output end of second signal receiving unit and the input terminal of the third pin, third is described
The output end of the input terminal connection third input selecting unit of pin, until the input terminal connection of m-th of input selecting unit
The m-1 output ends of the signal receiving unit and the input terminal of m-th of pin.
In some embodiments of the present invention, the input selecting unit and the output select unit are selector.
In some embodiments of the present invention, the pin is judged according to the quantity of second signal described in the test result
Whether generation bridge joint is short-circuit.
In some embodiments of the present invention, the quantity of second signal described in the test result is equal to 1, judges the pipe
There is no bridge joint short circuits for foot.
When there is 10 value in some specific embodiments of the present invention, in the test result, judge that the pin does not have
Bridge joint short circuit occurs.
In some embodiments of the present invention, the quantity of second signal described in the test result is greater than 1, judges the pipe
The raw bridge joint short circuit of human hair combing waste.
In some specific embodiments of the present invention, when having in the test result greater than 10 value, the pin is judged
Bridge joint short circuit occurs.
In some embodiments of the present invention, the pin for being arranged to output mode and the pipe for being arranged to input pattern
When the raw bridge joint of human hair combing waste is short-circuit, the bit shift connecting in the input shift register with the pin for being arranged to input pattern is exported
0。
Although embodiments of the present invention are hereinbefore described in detail, show for those skilled in the art
And be clear to, these embodiments can be carry out various modifications and be changed.However, it is understood that this modifications and variations are all
Belong within scope and spirit of the present invention described in the claims.Moreover, the present invention described herein can have others
Embodiment, and can be practiced or carried out in several ways.
Claims (8)
1. the pin of FPGA a kind of bridges short circuit test method, which comprises the following steps:
S1: signal excitation module and signal receiving module are constructed by the logic unit of FPGA, the signal excitation module includes m
A signal exciting unit successively to sort, the signal receiving module include the m signal receiving units successively to sort, the m
For the natural number greater than 0, the signal exciting unit and signal receiving unit are arranged in a one-to-one correspondence with pin respectively；
S2: the first signal is continuously inputted to the m exciting units, makes each exciting unit to the corresponding pin
First signal is transmitted, the access module of the m pins is arranged as input pattern；
S3: Xiang Suoshu signal excitation module inputs moving pulse signal, the moving pulse signal include second signal and
More than or equal to m first signals, the moving pulse signal are continuously transmitted to institute from first signal exciting unit
M-th of signal exciting unit is stated, wherein the moving pulse signal is between two adjacent signal exciting units
It is transmitted in a manner of once only transmitting first signal or the second signal, and the m signal exciting units are also
One first signal or the second signal are synchronized and pass to the corresponding pin, receives the pipe of the second signal
The access module of foot is arranged to output mode；
S4: when the access module of a new pin is arranged to the output mode, then the signal receives mould
Block acquires the output signal of the m pins by the described signal receiving units of m, then using the m output signals as
Test result output, until completing the detection of the m pins.
2. the pin of FPGA according to claim 1 bridges short circuit test method, which is characterized in that the signal excited modes
Block is Output Shift Register.
3. the pin of FPGA according to claim 2 bridges short circuit test method, which is characterized in that the signal excitation is single
Member is the position of the Output Shift Register.
4. the pin of FPGA according to claim 1 bridges short circuit test method, which is characterized in that the signal receives mould
Block is input shift register.
5. the pin of FPGA according to claim 4 bridges short circuit test method, which is characterized in that the signal receives single
Member is the position of the input shift register.
6. the pin of FPGA according to claim 1 bridges short circuit test method, which is characterized in that tied according to the test
The quantity of second signal described in fruit judges whether the pin occurs bridge joint short circuit.
7. the pin of FPGA according to claim 6 bridges short circuit test method, which is characterized in that in the test result
The quantity of the second signal is equal to 1, and judging the pin, there is no bridge joint short circuits.
8. the pin of FPGA according to claim 6 bridges short circuit test method, which is characterized in that in the test result
The quantity of the second signal is greater than 1, judges that bridge joint short circuit occurs for the pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910509147.6A CN110133486B (en) | 2019-06-13 | 2019-06-13 | Pin bridging short circuit test method of FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910509147.6A CN110133486B (en) | 2019-06-13 | 2019-06-13 | Pin bridging short circuit test method of FPGA |
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| Publication Number | Publication Date |
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| CN110133486A true CN110133486A (en) | 2019-08-16 |
| CN110133486B CN110133486B (en) | 2021-06-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910509147.6A Active CN110133486B (en) | 2019-06-13 | 2019-06-13 | Pin bridging short circuit test method of FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117054858A (en) * | 2023-10-11 | 2023-11-14 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
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| WO2006064551A1 (en) * | 2004-12-14 | 2006-06-22 | Atsunori Shibuya | Test apparatus |
| CN103076530A (en) * | 2012-12-28 | 2013-05-01 | 昆山丘钛微电子科技有限公司 | Automatic open short circuit test system for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip and test method |
| CN103869209A (en) * | 2014-03-19 | 2014-06-18 | 成都市中州半导体科技有限公司 | Method for testing pins of integrated circuit |
| CN106952839A (en) * | 2017-03-01 | 2017-07-14 | 华为技术有限公司 | A kind of test circuit and chip |
| CN108510923A (en) * | 2018-03-30 | 2018-09-07 | 武汉精立电子技术有限公司 | A kind of detection liquid crystal module ID pins open the device of short circuit |
-
2019
- 2019-06-13 CN CN201910509147.6A patent/CN110133486B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006064551A1 (en) * | 2004-12-14 | 2006-06-22 | Atsunori Shibuya | Test apparatus |
| CN103076530A (en) * | 2012-12-28 | 2013-05-01 | 昆山丘钛微电子科技有限公司 | Automatic open short circuit test system for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip and test method |
| CN103869209A (en) * | 2014-03-19 | 2014-06-18 | 成都市中州半导体科技有限公司 | Method for testing pins of integrated circuit |
| CN106952839A (en) * | 2017-03-01 | 2017-07-14 | 华为技术有限公司 | A kind of test circuit and chip |
| CN108510923A (en) * | 2018-03-30 | 2018-09-07 | 武汉精立电子技术有限公司 | A kind of detection liquid crystal module ID pins open the device of short circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117054858A (en) * | 2023-10-11 | 2023-11-14 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
| CN117054858B (en) * | 2023-10-11 | 2024-01-16 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
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| CN110133486B (en) | 2021-06-18 |
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