CN110133486B - Pin bridging short circuit test method of FPGA - Google Patents
Pin bridging short circuit test method of FPGA Download PDFInfo
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- CN110133486B CN110133486B CN201910509147.6A CN201910509147A CN110133486B CN 110133486 B CN110133486 B CN 110133486B CN 201910509147 A CN201910509147 A CN 201910509147A CN 110133486 B CN110133486 B CN 110133486B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a pin bridge short circuit test method of an FPGA, which comprises the steps of constructing a signal excitation module and a signal receiving module through a logic unit of the FPGA, wherein the signal excitation module comprises m signal excitation units, the signal receiving module comprises m signal receiving units, m is a natural number larger than 0, the signal excitation units and the signal receiving units are respectively arranged corresponding to pins one by one, the m pins are set to be in an input mode, a moving pulse signal is input to the first signal excitation unit, the access mode of the pin for receiving a second signal is set to be in an output mode, and when a new pin is set to be in the output mode, the signal receiving module collects output signals of the m pins and then outputs the m output signals as test results. In the test method, no additional detection tool is needed, the cost is reduced, and the m pins are detected in sequence without being limited by the number of the pins.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a pin bridging short circuit testing method of an FPGA.
Background
As a semi-custom circuit in the Field of application-specific integrated circuits, a Field-Programmable gate array (FPGA) not only solves the defects of a full-custom circuit, but also overcomes the defect of limited gate circuit quantity of the original Programmable logic device.
The pin of the FPGA can transmit the signal of the pin of the FPGA to the chip through processing, and can also transmit the signal output from the chip to the pin of the chip through processing.
However, the automated test equipment has the following problems: on one hand, the automatic test equipment is expensive, so that the test cost is increased; on the other hand, the number of Input/Output (IO) pipelines of the automatic test equipment is limited, and the requirement when the number of pins of the FPGA is large cannot be met.
Therefore, there is a need to provide a novel pin bridging short circuit testing method for FPGA to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a pin bridging short circuit testing method of an FPGA, which does not need an additional detection tool, reduces the cost and can avoid the limitation of the testing method to the number of pins.
In order to achieve the above object, the pin bridging short circuit testing method of the FPGA of the present invention includes the following steps:
s1: constructing a signal excitation module and a signal receiving module through a logic unit of an FPGA (field programmable gate array), wherein the signal excitation module comprises m signal excitation units which are sequentially sequenced, the signal receiving module comprises m signal receiving units which are sequentially sequenced, m is a natural number which is greater than 0, and the signal excitation units and the signal receiving units are respectively arranged in one-to-one correspondence with pins;
s2: continuously inputting first signals to m excitation units, enabling each excitation unit to transmit the first signals to the corresponding pin, and setting an access mode of the m pins as an input mode;
s3: inputting a shift pulse signal to the signal excitation module, wherein the shift pulse signal comprises a second signal and m or more first signals, the shift pulse signal is continuously transmitted from a first signal excitation unit to an m-th signal excitation unit, the shift pulse signal is transmitted between two adjacent signal excitation units in a manner of transmitting only one first signal or one second signal at a time, the m signal excitation units also synchronously transmit one first signal or one second signal to the corresponding pins, and the access mode of the pins receiving the second signals is set to be an output mode;
s4: and each time when the access mode of a new pin is set to be the output mode, the signal receiving module collects the output signals of m pins through m signal receiving units, and then outputs the m output signals as test results until the detection of the m pins is completed.
The invention has the beneficial effects that: a signal excitation module and a signal receiving module are constructed through a logic unit of the FPGA, and the bridging short circuit of the pin is detected through the signal excitation module and the signal receiving module, so that an additional detection tool is not needed, and the cost is reduced; constructing a signal excitation module and a signal receiving module through a logic unit of an FPGA, wherein the signal excitation module comprises m signal excitation units which are sequentially sequenced, the signal receiving module comprises m signal receiving units which are sequentially sequenced, the number of the signal excitation units and the number of the signal receiving units can be determined according to the number of the pins, the access mode of the m pins is set as an input mode, a moving pulse signal is input to a first signal excitation unit, the moving pulse signal comprises more than or equal to m first signals and a second signal, the access mode of the pins which receive the second signal is set as an output mode, and the signal receiving module collects the output signals of the m pins when the access mode of a new pin is set as the output mode until the detection of the m pins is completed, and the detection on the m pins is completed in sequence without the limitation of the number of the pins.
Preferably, the signal excitation module is an output shift register, which has the following beneficial effects: the signal shift transmission in the output shift register can set all the pins to be in an output mode once, and the detection of all the pins can be realized.
Further preferably, the signal excitation unit is a bit of the output shift register.
Preferably, the signal receiving module is an input shift register, which has the advantages that: the input shift register can shift output, so that signals of all the pin input ends can be output, and whether the pin is in bridge short circuit or not can be determined.
Further preferably, the signal receiving unit is a bit of the input shift register.
Preferably, whether the pin is in a bridge short circuit or not is judged according to the number of the second signals in the test result, and the method has the advantages that: whether the pin is in the bridging short circuit or not can be judged according to the number of the second signals in the test result, and the accuracy is high.
Further preferably, the number of the second signals in the test result is equal to 1, and it is determined that the pin is not in a bridge short circuit.
Further preferably, the number of the second signals in the test result is greater than 1, and it is determined that the pin is in a bridge short circuit.
Drawings
Fig. 1 is a flowchart of a pin bridge short circuit test method of an FPGA according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a pin bridging short circuit testing method for an FPGA, and with reference to fig. 1, the method includes the following steps:
s1: constructing a signal excitation module and a signal receiving module through a logic unit of an FPGA (field programmable gate array), wherein the signal excitation module comprises m signal excitation units which are sequentially sequenced, the signal receiving module comprises m signal receiving units which are sequentially sequenced, m is a natural number which is greater than 0, and the signal excitation units and the signal receiving units are respectively arranged in one-to-one correspondence with pins;
s2: continuously inputting first signals to m excitation units, enabling each excitation unit to transmit the first signals to the corresponding pin, and setting an access mode of the m pins as an input mode;
s3: inputting a shift pulse signal to the signal excitation module, wherein the shift pulse signal comprises a second signal and m or more first signals, the shift pulse signal is continuously transmitted from a first signal excitation unit to an m-th signal excitation unit, the shift pulse signal is transmitted between two adjacent signal excitation units in a manner of transmitting only one first signal or one second signal at a time, the m signal excitation units also synchronously transmit one first signal or one second signal to the corresponding pins, and the access mode of the pins receiving the second signals is set to be an output mode;
s4: and each time when the access mode of a new pin is set to be the output mode, the signal receiving module collects the output signals of m pins through m signal receiving units, and then outputs the m output signals as test results until the detection of the m pins is completed.
In some embodiments of the present invention, the binary value of the first signal is 1, and the binary value of the second signal is 0.
In some embodiments of the present invention, when the pin is in the output mode, the value of the output end of the pin is the value at the pin pressure point position, i.e. the second signal.
In some embodiments of the present invention, the pin pressure location is a location where the pin is connected to other devices.
In some embodiments of the present invention, when the pin is in the input mode, the input value of the pin is a default weak pull-up value, and the default weak pull-up value is equal to 1.
In some embodiments of the invention, the signal excitation module is an output shift register.
In some embodiments of the present invention, the signal excitation unit is a bit of the output shift register.
In some embodiments of the invention, the signal receiving module is an input shift register.
In some embodiments of the invention, the signal receiving unit is a bit of the input shift register.
In some embodiments of the present invention, an input terminal of a first one of the signal pumping units is connected to an output terminal of a first one of the signal pumping units, an input terminal of the first one of the output selecting units is connected to a first signal output terminal and a signal pulse output terminal, an input terminal of a second one of the output selecting units is connected to the first signal output terminal and an output terminal of the first one of the signal pumping units, an output terminal of the second one of the output selecting units is connected to an input terminal of the second one of the signal pumping units, an input terminal of a third one of the output selecting units is connected to the first signal output terminal and an output terminal of the second one of the signal pumping units, an output terminal of the third one of the output selecting units is connected to an input terminal of the third one of the signal pumping units until an input terminal of the m-th one of the output selecting, the output end of the mth output selection unit is connected with the input end of the mth signal excitation unit.
In some embodiments of the present invention, the first signal output terminal continuously outputs a first signal, the signal pulse output terminal outputs the moving pulse signal, and each of the signal excitation units does not receive the first signal output by the first signal output terminal when receiving the moving pulse signal.
In some embodiments of the present invention, an output terminal of a first one of said signal excitation units is connected to an output terminal of a first one of said pins and to a tri-state signal selection terminal, and an output terminal of a second one of said signal excitation units is connected to an output terminal of a second one of said pins and to a tri-state signal selection terminal, until an output terminal of an m-th one of said signal excitation units is connected to an output terminal of an m-th one of said pins and to a tri-state signal selection terminal.
In some embodiments of the present invention, an input terminal of a first one of the signal receiving units is connected to an output terminal of a first one of the input selecting units, an input terminal of the first one of the input selecting units is connected to an input terminal of a first one of the pins, an input terminal of a second one of the input selecting units is connected to an output terminal of the first one of the signal receiving units and an input terminal of a second one of the pins, an input terminal of the second one of the signal receiving units is connected to an output terminal of the second one of the signal receiving units and an input terminal of a third one of the pins, and an input terminal of the third one of the pins is connected to an output terminal of the third one of the input selecting units until an input terminal of an m-th one of the input selecting units is connected to an output terminal of an m-1 th one of the signal receiving units.
In some embodiments of the present invention, the input selection unit and the output selection unit are both selectors.
In some embodiments of the present invention, whether the pin has a bridge short circuit is determined according to the number of the second signals in the test result.
In some embodiments of the present invention, the number of the second signals in the test result is equal to 1, and it is determined that the pin is not in a short circuit.
In some embodiments of the present invention, when the test result has 1 value of 0, it is determined that the pin is not in a bridge short circuit.
In some embodiments of the present invention, the number of the second signals in the test result is greater than 1, and it is determined that the pin is in a short circuit.
In some embodiments of the present invention, when the test result has more than 1 0 value, it is determined that the pin is in a bridge short circuit.
In some embodiments of the present invention, when the pin set to the output mode and the pin set to the input mode are in a bridge short circuit, the bit shift output 0 connected to the pin set to the input mode in the input shift register is output.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (5)
1. A pin bridging short circuit test method of an FPGA is characterized by comprising the following steps:
s1: constructing a signal excitation module and a signal receiving module through a logic unit of an FPGA (field programmable gate array), wherein the signal excitation module comprises m signal excitation units which are sequentially sequenced, the signal receiving module comprises m signal receiving units which are sequentially sequenced, m is a natural number which is greater than 0, and the signal excitation units and the signal receiving units are respectively arranged in one-to-one correspondence with pins;
s2: continuously inputting first signals to m excitation units, enabling each excitation unit to transmit the first signals to the corresponding pin, and setting an access mode of the m pins as an input mode;
s3: inputting a shift pulse signal to the signal excitation module, wherein the shift pulse signal comprises a second signal and m or more first signals, the shift pulse signal is continuously transmitted from a first signal excitation unit to an m-th signal excitation unit, the shift pulse signal is transmitted between two adjacent signal excitation units in a manner of transmitting only one first signal or one second signal at a time, the m signal excitation units also synchronously transmit one first signal or one second signal to the corresponding pins, and the access mode of the pins receiving the second signals is set to be an output mode;
s4: when the access mode of a new pin is set to the output mode, the signal receiving module acquires output signals of m pins through m signal receiving units, outputs the m output signals as test results until the detection of the m pins is completed, and judges whether the pins are in a bridge short circuit or not according to the number of the second signals in the test results;
the signal excitation module is an output shift register, and the signal receiving module is an input shift register.
2. The method according to claim 1, wherein the signal excitation unit is a bit of the output shift register.
3. The method according to claim 1, wherein the signal receiving unit is a bit of the input shift register.
4. The method according to claim 1, wherein the number of the second signals in the test result is equal to 1, and it is determined that the pin is not in a bridge short circuit.
5. The method for testing the pin bridge short circuit of the FPGA according to claim 1, wherein the number of the second signals in the test result is greater than 1, and it is determined that the pin is in the bridge short circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910509147.6A CN110133486B (en) | 2019-06-13 | 2019-06-13 | Pin bridging short circuit test method of FPGA |
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| CN201910509147.6A CN110133486B (en) | 2019-06-13 | 2019-06-13 | Pin bridging short circuit test method of FPGA |
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| CN110133486A CN110133486A (en) | 2019-08-16 |
| CN110133486B true CN110133486B (en) | 2021-06-18 |
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| CN117054858B (en) * | 2023-10-11 | 2024-01-16 | 井芯微电子技术(天津)有限公司 | Three-state configuration pin implementation method and IO device in chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006064551A1 (en) * | 2004-12-14 | 2006-06-22 | Atsunori Shibuya | Test apparatus |
| CN103076530A (en) * | 2012-12-28 | 2013-05-01 | 昆山丘钛微电子科技有限公司 | Automatic open short circuit test system for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip and test method |
| CN103869209A (en) * | 2014-03-19 | 2014-06-18 | 成都市中州半导体科技有限公司 | Method for testing pins of integrated circuit |
| CN106952839A (en) * | 2017-03-01 | 2017-07-14 | 华为技术有限公司 | A kind of test circuit and chip |
| CN108510923A (en) * | 2018-03-30 | 2018-09-07 | 武汉精立电子技术有限公司 | A kind of detection liquid crystal module ID pins open the device of short circuit |
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- 2019-06-13 CN CN201910509147.6A patent/CN110133486B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006064551A1 (en) * | 2004-12-14 | 2006-06-22 | Atsunori Shibuya | Test apparatus |
| CN103076530A (en) * | 2012-12-28 | 2013-05-01 | 昆山丘钛微电子科技有限公司 | Automatic open short circuit test system for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip and test method |
| CN103869209A (en) * | 2014-03-19 | 2014-06-18 | 成都市中州半导体科技有限公司 | Method for testing pins of integrated circuit |
| CN106952839A (en) * | 2017-03-01 | 2017-07-14 | 华为技术有限公司 | A kind of test circuit and chip |
| CN108510923A (en) * | 2018-03-30 | 2018-09-07 | 武汉精立电子技术有限公司 | A kind of detection liquid crystal module ID pins open the device of short circuit |
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