KR100435259B1 - Scan chain type integrated circuit and test method thereof, through which a stable vector value is supplied to an output cell - Google Patents

Abstract

PURPOSE: A scan chain type integrated circuit and a test method thereof are provided to reduce vector size and test time by supplying a serial scan vector to a register connected to an output cell directly, without going through logic gates of the integrated circuit. CONSTITUTION: A plurality of input cells(10) input external parallel data in a normal mode. A plurality of output cells(70) output internal parallel data in the normal mode, and output a scan vector in a test mode. A scan vector input cell(20) inputs the scan vector in the test mode. A scan vector output cell(60) outputs the scan vector in the test mode. The first and the second logic unit(40,50) are connected in parallel between the plurality of input cells and output cells to process the internal parallel data. And a plurality of registers(30) are connected between the input cells and the output cells to transmit the external parallel data to the first logic unit and to supply the internal parallel data to the output cell in the normal mode, and are shifted in sequence in response to a clock signal in the test mode, and are connected serially to supply the shifted scan vector to the output cell.

Description

Scan Chain Integrated Circuits and Test Methods

The present invention relates to an integrated circuit and a test method including a plurality of registers connected in a scan chain method, a scan vector input cell and a scan vector output cell, and particularly, in a test mode for testing an output cell driving capability of the integrated circuit. The present invention relates to a scan chain integrated circuit and a test method capable of testing an output cell driving capability at high speed using a serial scan vector input through the scan chain.

Conventional integrated circuits have measured VOH / L primarily using function vectors to test whether the output cell is rated "high level" or "low level" according to design rules. However, the integrated circuit needs to de-estimate the output vector and input the appropriate input vector value into the input cell in order to obtain the desired "high level" or "low level" of the desired VOH / L from the output cell during the VOH / L test. There was a disadvantage in that the test time was longer and longer.

In addition, since the input vector value must pass through the logic gates between the input cell and the output cell before being output to the output cell, when there is a defective device among the logic gates, the output cell itself during the output cell VOH / L test. Even if there is no defect, there is a problem of undetermining that an error occurs in an output cell of the integrated circuit.

An object of the present invention is to connect a plurality of registers and a scan vector input cell and a scan vector output cell in a scan chain method in order to solve the problems of the prior art as described above in series scan during the output cell VOH / L test The present invention provides a scan chain integrated circuit and a test method which can reduce a vector size and shorten a test time by allowing a vector to be directly supplied to a resistor connected to an output cell without passing through the logic gates of the integrated circuit.

In order to achieve the above object, the apparatus of the present invention comprises: a plurality of input cells for inputting external parallel data in a normal mode; A plurality of output cells for outputting internal parallel data in the normal mode; A scan vector input cell for inputting a serial scan vector in the test mode; A scan vector output cell for outputting the scan vector in the test mode; First and second logic units connected in parallel between the plurality of input cells and output cells to logic the internal parallel data; In order to transmit the external parallel data input from the input cells to the first logic unit in the normal mode and to supply internal parallel data processed by the first logic unit and the second logic unit to the output cell. And output cells are alternately connected in parallel with the first and second logic units, and the scan vectors input through the scan vector input cells in the test mode are sequentially responsive to a clock signal supplied from the outside. And a plurality of registers connected in series so that the shifted scan vector is supplied to an output cell.

On the other hand, the test method of the present invention for achieving the above object comprises the steps of determining whether the test mode for testing the output cell drive capability is performed; Inputting a serial scan vector to a scan vector input cell when the test mode is performed; Shifting the input serial scan vector with a plurality of registers connected in series with the scan vector input cell in synchronization with a clock signal; Determining whether the shifted serial scan vector is set up to a register connected to a plurality of output cells; Testing the output cell driving capability by transmitting the set vector as parallel data to the output cell when all the serial scan vectors are set; Determining whether the output cell driving capability test has ended; Ending the test mode when the test of the output cell drive capability is finished.

1 is a circuit diagram showing a scan chain type integrated circuit according to the present invention.

2 is a flowchart illustrating a control method for testing an output cell driving capability of a scan chain integrated circuit according to the present invention;

* Description of the symbols for the main parts of the drawings *

10: a plurality of input cells 20; Scan vector input cell

30: a plurality of registers 40: the first logic portion

50: second logic unit 60: scan vector output cell

70: multiple output cells

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a circuit diagram illustrating a scan chain type integrated circuit according to an exemplary embodiment of the present invention, and includes a plurality of input cells 10 for inputting parallel data from the outside in a normal mode and internal parallel data in the normal mode. A plurality of output cells 70 for outputting, a scan vector input cell 20 for inputting a serial scan vector in a test mode, and a scan vector output cell 60 for outputting a serial scan vector in the test mode And a first logic unit 40 and a second logic unit for processing data input from the plurality of input cells 10 between the plurality of input cells 10 and the plurality of output cells 70. The logic unit 50 and the data input from the plurality of input cells 10 are transmitted to the first logic unit 40, and through the first logic unit 40 and the second logic unit 50. Outputting the plurality of logically processed internal parallel data Supplied to the cells 70, it is composed of a plurality of resistors 30 connected in series with the input vector scan cell 20 and output scan cell vector 60.

2 is a flowchart illustrating a control method for testing an output cell driving capability of a scan chain type integrated circuit according to the present invention. Referring to FIGS. 1 to 2, the operation of the present invention will be described below.

When the control signal for selecting the mode is input to the integrated circuit of the present invention at a high level, the control signal is changed into a test mode for testing the VOH / L of the output cell to input a serial scan vector to the scan input cell 20. The serial scan vector input from the scan input cell 20 is shifted into the plurality of registers 30 by one digit per clock in synchronization with a clock signal supplied from the outside. That is, when the serial scan vector input to the scan input cell 20 is 000000001, the first serial scan vector 0 is input to the input terminal SI of the first register S_R1 in synchronization with a clock signal and the second clock is synchronized with the clock signal. In synchronization with the signal, the first serial scan vector 0 output from the output terminal SO of the first register S_R1 is input to the input terminal SI of the second register S_R2 and simultaneously from the scan input cell 20. The input second serial scan vector 0 is input to the input terminal SI of the first register S_R1. As a result, the serial scan vector 000000001 is set in the first register S_R1 to the ninth register S_R9 in the ninth clock signal.

When the serial scan vectors are set in the plurality of registers 30 as described above, the control signal inputted to the integrated circuit is transferred from the high level to the low level and is connected to the plurality of output cells 70. The serial scan vectors of S_R7 to S_R9 are simultaneously output to the plurality of output cells 70. Accordingly, the data values output through the plurality of output cells 70 are measured to test whether the plurality of output cells are driven at their respective ratings.

Subsequently, when the VOH / L test of the output cell is not completed, a new serial scan vector is inputted to the scan input cell 20 to repeat the same test procedure as above. Quit.

In the test mode, the serial scan vector value is set to 000 in registers S_R7 to S_R9 connected to the plurality of output cells 70 when the VOL of the output cell is to be tested, and the registers are to be tested when VOH is to be tested. Since the vector value can be easily adjusted to set 111 to (S_R7 to S_R9), the vector required for the test is reduced than before.

Meanwhile, when the integrated circuit is in the normal mode, parallel data input to the plurality of input cells 10 corresponds to the first logic unit 40 via the first register S_R1 through the third register S_R3. After the data is transmitted to the respective logic gates, the data is transmitted to the respective logic gates corresponding to the second logic unit 50 through the fourth register S_R4 through the sixth register S_R6. The internal parallel data output through the second logic unit 50 is output to the plurality of output cells 70 through the seventh register S_R7 through the ninth register S_R9.

Accordingly, the present invention provides a stable level vector value to a register located in front of the output cell by providing a register connected in series with the integrated circuit, a scan vector input cell and a scan vector output cell, thereby providing a more accurate VOHL of the output cell. You get

The present invention includes a plurality of registers connected in a scan chain, a scan vector input cell, and a scan vector output cell to test the output cell driving ability of the integrated circuit, so that a stable vector value is directly supplied to the output cell during the test. Since the time and the vector size can be shortened as much as possible, and the VOH / OL of the correct output cell can be obtained by the stable vector value, the test error rate is reduced.

Claims (8)

A plurality of input cells for inputting external parallel data in a normal mode; A plurality of output cells for outputting internal parallel data in the normal mode and outputting a scan vector in a test mode; A scan vector input cell for inputting the scan vector in the test mode; A scan vector output cell for outputting the scan vector in the test mode; First and second logic units connected in parallel between the plurality of input cells and output cells to logic the internal parallel data; The external parallel data input from the input cells in the normal mode is transmitted to the first logic unit and the internal parallel data processed through the first logic unit and the second logic unit is supplied to the output cell. Cells and output cells are alternately connected in parallel with the first and second logic units, and the scan vectors input through the scan vector input cells in the test mode are responsive to a clock signal supplied from the outside. And a plurality of registers sequentially shifted and connected in series so that the shifted scan vectors are supplied to an output cell. Determining whether a test mode for testing output cell driving capability is performed; Inputting a serial scan vector to a scan vector input cell when the test mode is performed; Shifting the input serial scan vector with a plurality of registers connected in series with the scan vector input cell in synchronization with a clock signal; Determining whether the shifted serial scan vector has been set up to a register connected to a plurality of output cells; Testing the output cell driving capability by transmitting the set vector as parallel data to the output cell when all the serial scan vectors are set; Determining whether the output cell driving capability test has ended; And ending a test mode when the test of the output cell driving ability is terminated. The scan method of claim 2, further comprising: determining whether a normal mode is performed when the test mode is not performed in determining whether a test mode for testing the output cell driving capability is performed. Test method for chain integrated circuits. The method of claim 2, wherein when the serial scan vector is not set in the step of determining whether all the serial scan vectors are set up to the registers connected to the output cells, the plurality of serially connected in series with the scan vector input cells in synchronization with a clock signal. And repeating the step of shifting the input serial scan vector into two registers. The scan chain type according to claim 2, further comprising a step of inputting a new serial scan vector into a scan vector input cell when the test is not terminated in the step of determining whether the output cell driving capability test is finished. Test method for integrated circuits. The normal mode of claim 3, wherein when the normal mode is performed in the determining of whether the normal mode is performed, the normal mode outputs parallel data input through the input cells to the output cells through a plurality of registers and logic gates. The method of claim 1, further comprising the step of performing a scan chain integrated circuit. 4. The test method of claim 3, wherein in the determining of whether the normal mode is performed, determining whether the test mode is performed when the normal mode is not performed. . 6. The method of claim 5, wherein the inputting of the new serial scan vector into the scan vector input cell comprises inputting a new serial scan vector into the scan vector input cell and then serially connecting the scan vector input cell in synchronization with a clock signal. And repeating the shifting of the input serial scan vector with a plurality of registers.

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