WO2011089762A1 - 表示パネルおよびその検査方法 - Google Patents
表示パネルおよびその検査方法 Download PDFInfo
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- WO2011089762A1 WO2011089762A1 PCT/JP2010/067649 JP2010067649W WO2011089762A1 WO 2011089762 A1 WO2011089762 A1 WO 2011089762A1 JP 2010067649 W JP2010067649 W JP 2010067649W WO 2011089762 A1 WO2011089762 A1 WO 2011089762A1
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- video signal
- switches
- switch
- source bus
- demultiplexer
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
Definitions
- the present invention relates to a display panel, and more particularly, to a display panel including a demultiplexer for distributing a video signal to a plurality of video signal lines and an inspection method thereof.
- a liquid crystal module is manufactured by mounting a driver IC (driving integrated circuit) on a liquid crystal panel in a module manufacturing process after an array manufacturing process, a panel manufacturing process, and the like.
- a driver IC driving integrated circuit
- panel inspection an inspection for checking whether or not the liquid crystal panel is defective is performed.
- an inspection circuit may be formed in advance on a substrate constituting the liquid crystal panel.
- FIG. 31 is a block diagram showing a configuration of a main part of a liquid crystal module in which a driver IC is mounted on a liquid crystal panel provided with such an inspection circuit.
- the liquid crystal module includes a pixel circuit unit 90 serving as an area for displaying an image by providing a source bus line SL and a gate bus line (not shown), a source driver 94 that is a driver IC for driving the source bus line SL, A first distribution circuit 91 that outputs a video signal sent from the source driver 94 while switching to a plurality of source bus lines SL, and a second distribution circuit that outputs a test video signal sent from the outside while switching to a plurality of source bus lines SL.
- Distribution circuit 92 and a switching circuit 93 that switches the output source of the video signal to the source bus line SL between the first distribution circuit 91 and the second distribution circuit 92.
- the second distribution circuit 92 functions as an inspection circuit.
- the source driver 94 is not yet mounted on the glass substrate.
- FIG. 32 is a circuit diagram showing the configuration of the first distribution circuit 91, the second distribution circuit 92, and the switching circuit 93.
- FIG. 32 shows only six source bus lines SL1 to SL6 among the plurality of source bus lines.
- the first distribution circuit 91 is provided with a 1-input 3-output demultiplexer for each of three source bus lines for red, green, and blue. Since one input has three outputs, each demultiplexer includes three switches (for example, thin film transistors).
- the second distribution circuit 92 is also provided with a 1-input 3-output demultiplexer for each of three source bus lines for red, green, and blue, and each demultiplexer includes three demultiplexers. Switches (for example, thin film transistors) are included.
- the first distribution circuit 91 is configured such that different video signals are respectively supplied to a plurality of demultiplexers. However, since the source driver 94 is not mounted at the time when the panel inspection is performed, a video signal is not externally applied to the first distribution circuit 91.
- the second distribution circuit 92 is configured such that a common (one) test video signal T_VIDEO is provided as an input signal to a plurality of demultiplexers.
- the switch constituting the demultiplexer in the first distribution circuit 91 is referred to as “sampling switch”, and the switch constituting the demultiplexer in the second distribution circuit 92 is referred to as “inspection switch”. It is called a switch.
- the switching circuit 93 includes a first switch group 931 composed of three switches, a second switch group 932 composed of three switches, and an inverter 933.
- the on / off states of the switches included in the first switch group 931 are controlled by a control signal T_SMP given from the outside, and the on / off states of the switches included in the second switch group 932 are logical inversion signals of the control signal T_SMP. Controlled by.
- T_SMP logical inversion signals of the control signal
- control signal T_SMP is also referred to as a “switching control signal”.
- control signals ASW1 to ASW3 are given to the circuit shown in FIG.
- the control signal ASW1 is supplied to the second distribution circuit 92 as the control signal T_ASW1
- the control signal ASW2 is supplied to the second distribution circuit 92 as the control signal T_ASW2.
- the control signal ASW3 is supplied to the second distribution circuit 92 as the control signal T_ASW3.
- the control signal ASW1 is given to the first distribution circuit 91 as the control signal U_ASW1
- the control signal ASW2 is given to the first distribution circuit 91 as the control signal U_ASW2.
- the control signal ASW3 is supplied to the first distribution circuit 91 as the control signal U_ASW3.
- the control signals ASW1 to 3 are also referred to as “distribution control signals”
- the control signals U_ASW1 to 3 are also referred to as “normal distribution control signals”
- the control signals T_ASW1 to 3 are “ Also referred to as “distribution control signal for inspection”.
- the switches included in the first switch group 931 are turned on and the switches included in the second switch group 932 are turned off based on the switching control signal T_SMP.
- the inspection switch in the second distribution circuit 92 is turned on or off according to the respective logic levels of the distribution control signals ASW1 to ASW3. In this manner, the liquid crystal panel is inspected by changing the potential of the test video signal T_VIDEO while changing the on / off state of the inspection switch in the second distribution circuit 92.
- the switches included in the first switch group 931 are turned off, and the switches included in the second switch group 932 are turned on.
- the sampling switch in the first distribution circuit 91 is turned on or off according to the respective logic levels of the distribution control signals ASW1 to ASW3.
- a video signal is supplied from the source driver 94 to the first distribution circuit 91 while changing the on / off state of the sampling switch in the first distribution circuit 91, whereby a desired image display is performed on the liquid crystal panel. Done.
- FIG. 33 shows the correspondence with the source bus line in which is performed.
- Japanese Unexamined Patent Application Publication No. 2007-206440 has a configuration in which a demultiplexer for distributing a data signal is provided on one end side of a data line, and an inspection circuit including a shift register is provided on the other end side of the data line.
- An invention relating to a substrate for an electro-optical device is disclosed.
- the circuit area is relatively large because the shift circuit is included in the inspection circuit. For this reason, it is difficult to narrow the frame of the panel. Further, since the inspection control circuit operates on the basis of the voltage on the readout line, a device for measuring the voltage on the readout line is required.
- the switches included in the second switch group 932 are maintained in the OFF state throughout the period during which the panel inspection is performed. For this reason, the sampling switch in the first distribution circuit 91 is maintained in the off state during the panel inspection. Therefore, a defective sampling switch cannot be detected during panel inspection.
- an object of the present invention is to realize a display panel that can detect a failure of a sampling switch that normally operates during panel inspection without increasing the circuit scale.
- the first aspect of the present invention is: A display panel, a display unit in which a plurality of video signal lines constituting a set of video signal line groups are arranged every n (n is a natural number of 2 or more); Each of the n video signal lines included in the video signal line group is provided with one set of video signal line groups on one end side of the plurality of video signal lines and sent from the outside.
- a first demultiplexer comprising n first switches for switching whether to apply to A second video signal that is provided for each set of video signal line groups on the other end side of the plurality of video signal lines and is sent from the outside is connected to n video signal lines included in the video signal line group.
- a second demultiplexer composed of n second switches for switching whether or not to apply to each;
- An operation control unit that switches whether to enable application of the second video signal to the plurality of video signal lines,
- the states of the n first switches included in the first demultiplexer are controlled by n different control signals,
- the states of the n second switches included in the second demultiplexer are controlled by the n control signals different from each other,
- an arbitrary control signal among the n control signals is a target control signal
- the video signal line connected to the first switch turned on by the target control signal and the video signal line It is different from the video signal line connected to the second switch which is turned on by the target control signal.
- the operation control unit includes n control switches provided corresponding to each of the n second switches included in the second demultiplexer, Each control switch controls whether or not to apply the control signal to the second switch based on a switching control signal given from the outside.
- the operation control unit includes a plurality of control switches provided corresponding to each of the plurality of video signal lines between the output unit of the second demultiplexer and the display unit. Whether each control switch enables application of the second video signal from the output unit of the second demultiplexer to the plurality of video signal lines based on a switching control signal given from the outside. It is characterized by switching.
- the operation control unit includes a plurality of control switches provided corresponding to each of the plurality of video signal lines in the vicinity of the input unit of the second demultiplexer, Each control switch switches whether to apply the second video signal to the input unit of the second demultiplexer based on a switching control signal given from the outside.
- the second video signal is commonly supplied to input portions of all second demultiplexers provided on the other end side of the plurality of video signal lines.
- the n first switches included in the first demultiplexer and the n second switches included in the second demultiplexer are thin film transistors.
- a seventh aspect of the present invention is a display module including the display panel according to the first aspect of the present invention, A video signal line driving circuit for supplying the first video signal to the first demultiplexer is mounted on the display panel.
- a display unit in which a plurality of video signal lines constituting a set of video signal line groups are arranged every n (n is a natural number of 2 or more); Whether one of the video signal line groups is provided on one end side of the video signal lines and the first video signal sent from the outside is applied to each of the n video signal lines included in the video signal line group
- a first demultiplexer composed of n first switches for switching between “no” and “no”, and provided on the other end side of the plurality of video signal lines for each set of video signal line groups and sent from the outside.
- a second demultiplexer comprising n second switches for switching whether to apply a second video signal to each of the n video signal lines included in the video signal line group; Whether or not the second video signal can be applied to the video signal line.
- An operation control unit for changing Ri there is provided an inspection method of a display panel and a control signal input for receiving the n control signals sent from the outside, An inspection preparation step in which the operation control unit enables application of the second video signal to the plurality of video signal lines; When the signal level of the second video signal is a predetermined first level, the n first signals included in the first demultiplexer provided corresponding to each video signal line group.
- One of the switches and one of the n second switches included in the second demultiplexer provided corresponding to each video signal line group are maintained in an ON state for a predetermined period.
- One of the n first switches and one of the n second switches included in the second demultiplexer provided corresponding to each video signal line group are on for a predetermined period.
- the first level applying step is performed such that the second video signal of the first level is applied to the video signal line corresponding to the display color to be inspected
- the second level applying step is performed such that the second video signal of the second level is applied to a video signal line corresponding to a display color other than the inspection target.
- a display unit in which a plurality of video signal lines constituting one set of video signal line groups are arranged every n (n is a natural number of 2 or more); Whether one of the video signal line groups is provided on one end side of the video signal lines and the first video signal sent from the outside is applied to each of the n video signal lines included in the video signal line group
- a first demultiplexer composed of n first switches for switching between “no” and “no”, and provided on the other end side of the plurality of video signal lines for each set of video signal line groups and sent from the outside.
- a second demultiplexer comprising n second switches for switching whether to apply a second video signal to each of the n video signal lines included in the video signal line group; Whether or not the second video signal can be applied to the video signal line.
- An operation control unit for changing Ri there is provided an inspection method of a display panel and a control signal input for receiving the n control signals sent from the outside, An inspection preparation step in which the operation control unit enables application of the second video signal to the plurality of video signal lines; When the signal level of the second video signal is a predetermined first level, the n first signals included in the first demultiplexer provided corresponding to each video signal line group.
- M of the switches (m is a natural number less than n) and m of the n second switches included in the second demultiplexer provided corresponding to each video signal line group.
- an arbitrary control signal among the n control signals is a target control signal
- the video signal line connected to the first switch turned on by the target control signal and the video signal line It is different from the video signal line connected to the second switch which is turned on by the target control signal.
- the first demultiplexer including the first switch is provided on one end side of the video signal line
- the second demultiplexer including the second switch is provided on the other end side of the video signal line.
- the first control signal is turned on by the target control signal.
- the video signal line connected to one switch is different from the video signal line connected to the second switch which is turned on by the target control signal.
- the first switch having an open failure in the first demultiplexer.
- the first switch having an open failure in the first demultiplexer.
- the first switch with the opening failure but also the first switch controlled by the target control signal is turned on.
- the voltage of the second video signal that should be originally applied to only one of the n video signal lines constituting the set of video signal line groups is applied to the plurality of video signal lines.
- the electric charge accumulated in one video signal line is distributed to a plurality of video signal lines. Accordingly, it is possible to detect an open failure of the first switch during panel inspection in which the first video signal is not given from the outside.
- a display panel having a configuration in which the operation control unit for switching whether or not the second video signal can be applied to the video signal line is realized by a relatively small number of switches.
- the same effect as that of the first aspect of the present invention is achieved without increasing the frame area in the direction perpendicular to the direction in which the video signal line extends (the direction in which the scanning signal line extends). Is realized.
- the same effect as that of the first aspect of the present invention is achieved without increasing the frame area in the direction perpendicular to the direction in which the video signal line extends (the direction in which the scanning signal line extends). Is realized.
- the same effect as that of the first aspect of the present invention can be obtained in the display panel in which the thin film transistor is adopted as the switch constituting the demultiplexer.
- a display module including a display panel that can obtain the same effect as that of the first aspect of the present invention is realized.
- the first demultiplexer including the first switch is provided on one end side of the video signal line
- the second demultiplexer including the second switch is provided on the other end side of the video signal line.
- a voltage other than the first level is applied to the video signal line corresponding to the display color to be inspected, and the display color other than the inspection target is displayed.
- a voltage other than the second level may be applied to the video signal line corresponding to.
- the first demultiplexer including the first switch is provided on one end side of the video signal line
- the second demultiplexer including the second switch is provided on the other end side of the video signal line.
- FIG. 3 is a circuit diagram illustrating configurations of a first distribution circuit and a second distribution circuit included in the liquid crystal panel according to the first embodiment of the present invention. It is a block diagram which shows the structure of the principal part of the liquid crystal panel which concerns on the said 1st Embodiment.
- FIG. 3 is a block diagram showing a state where a source driver is mounted on a liquid crystal panel in the first embodiment.
- FIG. 3 is a circuit diagram showing a detailed configuration of a first distribution circuit in the first embodiment.
- FIG. 3 is a circuit diagram showing a detailed configuration of a second distribution circuit in the first embodiment.
- FIG. 3 is a circuit diagram illustrating configurations of a first distribution circuit and a second distribution circuit included in the liquid crystal panel according to the first embodiment of the present invention. It is a block diagram which shows the structure of the principal part of the liquid crystal panel which concerns on the said 1st Embodiment.
- FIG. 3 is a block diagram showing a state where a source driver is mounted on a
- FIG. 5 is a signal waveform diagram showing waveforms at the time of inspection and normal time of a distribution control signal, a switching control signal, a normal distribution control signal, and an inspection distribution control signal in the first embodiment.
- FIG. 6 is a diagram illustrating a correspondence relationship between a distribution control signal that is set to a high level, a source bus line that is normally written, and a source bus line that is written during a check in the first embodiment.
- it is a signal waveform diagram for demonstrating the panel test
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when the test
- FIG. 6 is a diagram for explaining an operation when there is an open defect in the sampling switch in the first embodiment.
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when the test
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when the test
- it is a signal waveform diagram for demonstrating the panel test
- FIG. 6 is a signal waveform diagram showing a change in potential of a source bus line when an R / B write check is performed in the first embodiment.
- FIG. 6 is a signal waveform diagram showing a change in potential of a source bus line when an R / G write test is performed in the first embodiment.
- FIG. 6 is a signal waveform diagram showing a change in potential of a source bus line when a G / B write test is performed in the first embodiment.
- It is a circuit diagram which shows the structure in the modification of the said 1st Embodiment.
- It is a circuit diagram which shows the structure in another modification of the said 1st Embodiment.
- FIG. 10 is a diagram illustrating a correspondence relationship between a distribution control signal that is set to a high level, a source bus line that is normally written, and a source bus line that is written during a check in the second embodiment.
- it is a signal waveform diagram for demonstrating the panel test
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when the test
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when the test
- the said 2nd Embodiment it is a signal waveform diagram which shows the change of the electric potential of a source bus line when the test
- it is a signal waveform diagram for demonstrating the panel test
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when R / B writing test
- it is a signal waveform diagram which shows the change of the electric potential of a source bus line when R / G writing test
- the said 2nd Embodiment it is a signal waveform diagram which shows the change of the electric potential of a source bus line when G / B write test
- FIG. 2 is a block diagram showing a configuration of a main part of the liquid crystal panel according to the first embodiment of the present invention.
- the liquid crystal panel includes a pixel circuit unit 10 serving as a region for displaying an image, a first distribution circuit 20 having a function of outputting a signal sent from the outside while switching to a plurality of signal lines, and And a second distribution circuit 30.
- the pixel circuit unit 10, the first distribution circuit 20, and the second distribution circuit 30 are one glass substrate (generally called an “array substrate”) of two glass substrates constituting the liquid crystal panel. ) Is formed on.
- the pixel circuit unit 10 includes a plurality of source bus lines (video signal lines) SL, a plurality of gate bus lines (scanning signal lines), and intersections of the source bus lines SL and the gate bus lines. And a plurality of pixel forming portions provided.
- FIG. 2 shows only the source bus line SL among the components of the pixel circuit unit 10.
- Each pixel forming portion includes a thin film transistor (TFT) which is a switching element having a gate terminal connected to a gate bus line passing through a corresponding intersection and a source terminal connected to a source bus line SL passing through the intersection.
- TFT thin film transistor
- the liquid crystal layer is sandwiched between the common electrode.
- a driver IC driving integrated circuit
- a liquid crystal module is manufactured by mounting a driver IC on the liquid crystal panel.
- the source driver 40 for driving the source bus line SL is mounted on the glass substrate in the form of an IC chip as shown in FIG. That is, in this embodiment, a COG (Chip On Glass) method is adopted as a mounting method of the IC chip.
- the present invention can also be applied to a liquid crystal panel that employs a mounting method other than the COG method such as a COF (Chip On Film) method in which an IC chip is mounted on an FPC (Flexible Printed Circuit).
- a mounting method other than the COG method such as a COF (Chip On Film) method in which an IC chip is mounted on an FPC (Flexible Printed Circuit).
- the gate driver for driving the gate bus line include those formed monolithically on the glass substrate in advance and those mounted on the glass substrate in the form of an IC chip in the same manner as the source driver. Since it is not directly related to the above, its description and illustration are omitted.
- the source driver 40 drives the source bus line SL based on a data signal and a timing signal sent from a control circuit outside the liquid crystal panel (for example, a PCB attached to the liquid crystal panel). However, when the panel inspection described later is performed, the liquid crystal module is not completed, that is, the source driver 40 is not yet mounted on the glass substrate. It is never driven.
- FIG. 1 is a circuit diagram showing the configuration of the first distribution circuit 20 and the second distribution circuit 30.
- FIG. 1 shows only six source bus lines SL1 to SL6 among the plurality of source bus lines.
- the first distribution circuit 20 includes a plurality of demultiplexers that output one input signal while switching to a plurality of signal lines. Specifically, as shown in FIG. 4, a 1-input 3-output demultiplexer is provided for each of the three source bus lines for red, green, and blue. Since one input has three outputs, each demultiplexer includes three switches (for example, thin film transistors). These switches are hereinafter referred to as “sampling switches”.
- different input signals are given to the plurality of demultiplexers DMU1, DMU2,..., DMUn in the first distribution circuit 20, respectively.
- the video signal V1 is given to the demultiplexer DMU1 provided corresponding to the source bus lines SL1 to SL3
- the video signal V2 is supplied to the demultiplexer DMU2 provided corresponding to the source bus lines SL4 to SL6.
- the video signal Vn is supplied to the demultiplexer DMUn provided corresponding to the source bus lines SL (3n-2) to SL (3n).
- the on / off states of the sampling switches TRU1, TRU2,..., TRUn provided corresponding to the red source bus lines SL1, SL4,..., SL (3n-2) are controlled by the control signal U_ASW1.
- the on / off states of the sampling switches TGU1, TGU2,..., TGUn provided corresponding to the green source bus lines SL2, SL5,..., SL (3n-1) are controlled.
- the on / off states of the sampling switches TBU1, TBU2,..., TBUn controlled by the signal U_ASW2 and provided corresponding to the blue source bus lines SL3, SL6,. Controlled by signal U_ASW3.
- the video signals V1 to Vn are sent from the source driver 40 described above. Therefore, in the panel inspection performed in a state where the source driver 40 is not yet mounted on the glass substrate, the video signals V1 to Vn are not given to the demultiplexers DMU1 to DMUn.
- reference numerals 56 and 57 are assigned to input terminals for receiving the video signals V1 and V2 sent from the source driver 40, respectively.
- the second distribution circuit 30 includes a distribution unit 31 including a plurality of demultiplexers and an operation control unit 32 that controls transmission of signals to the distribution unit 31.
- the distribution unit 31 is provided with a 1-input 3-output demultiplexer for each of three source bus lines for red, green, and blue, as in the first distribution circuit 20. ing.
- Each demultiplexer includes three switches (eg, thin film transistors). These switches are hereinafter referred to as “inspection switches”.
- a plurality of demultiplexers DMT1, DMT2,..., DMTn receive a common (one) test video signal T_VIDEO as an input signal.
- the test video signal T_VIDEO is given from the outside to an input terminal denoted by reference numeral 55 in FIG.
- the on / off states of the inspection switches TRT1, TRT2,..., TRTn provided corresponding to the red source bus lines SL1, SL4,.
- the state is controlled by the control signal T_ASW3.
- the operation control unit 32 includes three switches SW1 to SW3 for controlling transmission of signals to the distribution unit 31, as shown in FIG.
- the on / off states of the three switches SW1 to SW3 are controlled by a control signal (switching control signal) T_SMP given to the input terminal indicated by reference numeral 54 from the outside.
- the switches SW1 to SW3 are turned on if the control signal T_SMP is high level, and the switches SW1 to SW3 are turned off if the control signal T_SMP is low level.
- control signals ASW1 to ASW3 are applied.
- the control signal ASW1 is given to the first distribution circuit 20 as the control signal U_ASW1, and is given to the distribution unit 31 in the second distribution circuit 30 as the control signal T_ASW3 when the switch SW1 is in the ON state.
- the control signal ASW2 is supplied to the first distribution circuit 20 as the control signal U_ASW2, and is also supplied to the distribution unit 31 in the second distribution circuit 30 as the control signal T_ASW1 when the switch SW2 is in the ON state.
- the control signal ASW3 is given to the first distribution circuit 20 as the control signal U_ASW3, and is given to the distribution unit 31 in the second distribution circuit 30 as the control signal T_ASW1 when the switch SW3 is in the ON state.
- FIG. 6 is a signal waveform diagram showing waveforms at the time of inspection and normal time of the distribution control signal, the switching control signal, the normal distribution control signal, and the inspection distribution control signal.
- the control signal T_SMP is maintained at a high level at the time of inspection, and is maintained at a low level at the normal time. Therefore, the switches SW1 to SW3 in the operation control unit 32 are maintained in the on state at the time of inspection, and are maintained in the off state at the normal time.
- control signals U_ASW1 and T_ASW3 are at the high level during the period in which the control signal ASW1 is at the high level, and the control signals U_ASW2 and T_ASW1 are at the period in which the control signal ASW2 is at the high level.
- the control signals U_ASW3 and T_ASW2 are at the high level during the period when the control signal ASW3 is at the high level.
- the control signal U_ASW1 is at the high level during the period when the control signal ASW1 is at the high level
- only the control signal U_ASW2 is at the high level during the period when the control signal ASW2 is at the high level.
- the control signal U_ASW3 is at the high level.
- the source bus line to which writing is performed at the time of inspection is as shown in FIG.
- the distribution control signal to be set to the high level and the source bus line to which writing is normally performed
- the source bus line to which writing is performed at the time of inspection is as shown in FIG.
- FIG. 32 In the conventional configuration, paying attention to the case where a certain distribution control signal becomes high level, as shown in FIG. 32, writing is performed on the same source bus line at the normal time and at the time of inspection.
- writing is performed on different source bus lines at the normal time and at the time of inspection.
- one set of video signal line groups is constituted by three source bus lines for red, green, and blue.
- the first demultiplexer is realized by the demultiplexer in the first distribution circuit 20
- the second demultiplexer is realized by the demultiplexer in the second distribution circuit 30, and the sampling switch
- the first switch is realized and the second switch is realized by the inspection switch.
- the distribution control signal is set to a high level for each predetermined period in the order of ASW2, ASW3, and ASW1.
- the periods indicated by reference numerals T1, T2, and T3 in FIG. 8 are hereinafter referred to as a first period, a second period, and a third period, respectively.
- the switching control signal T_SMP is maintained at a high level throughout the period during which the panel inspection is performed.
- this inspection includes a red display inspection, a green display inspection, and a blue display inspection. As shown in FIG.
- the test video signal T_VIDEO is set to the high level only during the first period T1 when the red display is inspected, and the test video signal is performed only during the second period T2 when the green display is inspected.
- T_VIDEO is set to the high level
- the test video signal T_VIDEO is set to the high level only during the third period T3 when the blue display is inspected. For example, if the voltage of the common electrode is 0V, the voltage of the test video signal T_VIDEO is 5V when the level is high and 0V when the level is low.
- FIG. 9 is a signal waveform diagram showing changes in potentials of source bus lines SL1 to SL3 when red display inspection is performed.
- the test video signal T_VIDEO is set to the high level only in the first period T1.
- the sampling switch If there is no open failure in the sampling switch, it operates as follows. In the first period T1, since the control signals T_ASW1, U_ASW2 are at a high level, the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. In the second period T2, since the control signals T_ASW2 and U_ASW3 are at a high level, the inspection switch TGT1 and the sampling switch TBU1 are turned on. Thereby, the low-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the inspection switch TBT1 and the sampling switch TRU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- a high level voltage is applied to the source bus line SL1
- a low level voltage is applied to the source bus lines SL2 and SL3.
- red display is performed in a line area including only normal sampling switches.
- the sampling switch has an open failure, it operates as follows.
- the sampling switch TRU1 is defective in opening.
- the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1.
- the sampling switch TRU1 is also turned on in the first period T1. As a result, as shown by an arrow 19 in FIG.
- a high-level test video signal T_VIDEO is supplied from the source bus line SL1 to the source bus line SL2 via the sampling switches TRU1 and TGU1.
- the inspection switch TGT1 and the sampling switch TBU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL3 via the sampling switches TRU1 and TBU1.
- the potential of the source bus line SL1 decreases and the potential of the source bus line SL3 increases.
- the inspection switch TBT1 and the sampling switch TRU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- an intermediate level voltage is applied to the source bus line SL1
- a low level voltage is applied to the source bus lines SL2 and SL3.
- red display is not performed and gray display is performed in the area of the line where the open defective sampling switch exists.
- FIG. 11 is a signal waveform diagram showing changes in the potentials of the source bus lines SL1 to SL3 when the green display inspection is performed.
- the test video signal T_VIDEO is set to the high level only in the second period T2.
- the sampling switch If there is no open failure in the sampling switch, it operates as follows. In the first period T1, since the control signals T_ASW1, U_ASW2 are at a high level, the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the low-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. In the second period T2, since the control signals T_ASW2 and U_ASW3 are at a high level, the inspection switch TGT1 and the sampling switch TBU1 are turned on. Thereby, the high-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the inspection switch TBT1 and the sampling switch TRU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- a low level voltage is applied to the source bus lines SL1 and SL3, and a high level voltage is applied to the source bus line SL2.
- green display is performed in the area of the line including only normal sampling switches.
- the sampling switch TRU1 If the sampling switch has an open failure, it operates as follows. Here, it is assumed that the sampling switch TRU1 is defective in opening. In the first period T1, since the control signals T_ASW1, U_ASW2 are at a high level, the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the low-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. Further, since it is assumed that the sampling switch TRU1 is in an open failure, the sampling switch TRU1 is also turned on in the first period T1. As a result, the low-level test video signal T_VIDEO is supplied from the source bus line SL1 to the source bus line SL2 via the sampling switches TRU1 and TGU1.
- the inspection switch TGT1 and the sampling switch TBU1 are turned on.
- the high-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL3 via the sampling switches TRU1 and TBU1. As a result, the potential of the source bus line SL1 increases and the potential of the source bus line SL3 decreases.
- the inspection switch TBT1 and the sampling switch TRU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- an intermediate level voltage is applied to the source bus line SL1
- a high level voltage is applied to the source bus line SL2
- the source bus line SL3 is applied to the source bus line SL3.
- a low level voltage is applied.
- the green display is not performed in the area of the line where the sampling switch with poor opening exists.
- FIG. 12 is a signal waveform diagram showing changes in the potentials of the source bus lines SL1 to SL3 when the blue display inspection is performed.
- the test video signal T_VIDEO is set to the high level only in the third period T3.
- the sampling switch If there is no open failure in the sampling switch, it operates as follows. In the first period T1, since the control signals T_ASW1, U_ASW2 are at a high level, the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the low-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. In the second period T2, since the control signals T_ASW2 and U_ASW3 are at a high level, the inspection switch TGT1 and the sampling switch TBU1 are turned on. Thereby, the low-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the inspection switch TBT1 and the sampling switch TRU1 are turned on.
- the high-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- a low level voltage is applied to the source bus lines SL1 and SL2, and a high level voltage is applied to the source bus line SL3.
- blue display is performed in a line area including only normal sampling switches.
- the sampling switch TRU1 If the sampling switch has an open failure, it operates as follows. Here, it is assumed that the sampling switch TRU1 is defective in opening. In the first period T1, since the control signals T_ASW1, U_ASW2 are at a high level, the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the low-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. Further, since it is assumed that the sampling switch TRU1 is in an open failure, the sampling switch TRU1 is also turned on in the first period T1. As a result, the low-level test video signal T_VIDEO is supplied from the source bus line SL1 to the source bus line SL2 via the sampling switches TRU1 and TGU1.
- the inspection switch TGT1 and the sampling switch TBU1 are turned on.
- the high-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL3 via the sampling switches TRU1 and TBU1. As a result, the potential of the source bus line SL1 increases and the potential of the source bus line SL3 decreases.
- the inspection switch TBT1 and the sampling switch TRU1 are turned on.
- the high-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- an intermediate level voltage is applied to the source bus line SL1
- a low level voltage is applied to the source bus line SL2
- the source bus line SL3 is applied to the source bus line SL3.
- a high level voltage is applied.
- blue display is not performed in the area of the line where the sampling switch with poor opening exists.
- red display, green display, and blue display are all normally performed in a line area including only normal sampling switches.
- all or part of red display, green display, and blue display is not normally performed. Thereby, it is possible to detect an open failure of the sampling switch.
- any two of the distribution control signals ASW1 to ASW3 are set to a high level for a predetermined period (first period T1).
- FIG. 13 shows a signal waveform diagram when ASW1 and ASW2 of the distribution control signals are set to the high level in the first period T1.
- the switching control signal T_SMP is maintained at a high level throughout the period during which the panel inspection is performed.
- the two normal distribution control signals and the two inspection distribution control signals corresponding to the distribution control signal set to the high level are set to the high level.
- the test video signal T_VIDEO is set to the high level in the first period T1.
- R / B writing inspection writing inspection to the source bus lines for red and blue
- G / B write check writing inspection to the green and blue source bus lines
- FIG. 14 is a signal waveform diagram showing changes in the potentials of source bus lines SL1 to SL3 when the R / B write test is performed. At this time, during the first period T1, among the distribution control signals, ASW1 and ASW2 are set to the high level.
- the sampling switch If the sampling switch has no interruption, it operates as follows. In the first period T1, since the T_ASW1 and T_ASW3 for the inspection distribution control signal are at a high level, the inspection switches TRT1 and TBT1 are turned on. Thereby, the high-level test video signal T_VIDEO is applied to the source bus lines SL1 and SL3 via the test switches TRT1 and TBT1. Further, in the first period T1, since the U_ASW1 and U_ASW2 for the normal distribution control signal are at a high level, the sampling switches TRU1 and TGU1 are turned on.
- the high-level test video signal T_VIDEO is also applied to the source bus line SL2 from the source bus line SL1 via the sampling switches TRU1 and TGU1.
- a high-level voltage is applied to the source bus lines SL1 to SL3.
- white display is performed in a line area including only normal sampling switches.
- the sampling switch has an interruption failure, it operates as follows. In this case, it is assumed that the sampling switch TRU1 has a cutoff failure. In the first period T1, the inspection switches TRT1 and TBT1 are turned on and the high-level test video signal T_VIDEO is applied to the source bus lines SL1 and SL3, as in the case where the sampling switch has no blocking failure. In the first period T1, U_ASW1 and U_ASW2 are at a high level for the normal distribution control signal. However, since it is assumed that the sampling switch TRU1 is defective in blocking, only the sampling switch TGU1 is in the ON state. Become.
- the test video signal T_VIDEO is not applied to the source bus line SL2.
- a high level voltage is applied to the source bus lines SL1 and SL3, and an intermediate level voltage is applied to the source bus line SL2.
- white display is not performed in the area of the line where the sampling switch with poor interruption exists.
- FIG. 15 is a signal waveform diagram showing changes in the potentials of source bus lines SL1 to SL3 when the R / G write test is performed. At this time, during the first period T1, among the distribution control signals, ASW2 and ASW3 are set to the high level.
- the sampling switch If the sampling switch has no interruption, it operates as follows. In the first period T1, since the T_ASW1 and T_ASW2 are at a high level for the inspection distribution control signal, the inspection switches TRT1 and TGT1 are turned on. Thereby, the high-level test video signal T_VIDEO is applied to the source bus lines SL1 and SL2 via the test switches TRT1 and TGT1. Further, in the first period T1, since the U_ASW2 and U_ASW3 are at a high level for the normal distribution control signal, the sampling switches TGU1 and TBU1 are turned on.
- the high-level test video signal T_VIDEO is also applied to the source bus line SL3 from the source bus line SL2 via the sampling switches TGU1 and TBU1.
- a high-level voltage is applied to the source bus lines SL1 to SL3.
- white display is performed in a line area including only normal sampling switches.
- the sampling switch has an interruption failure, it operates as follows. In this case, it is assumed that the sampling switch TRU1 has a cutoff failure.
- the inspection switches TRT1 and TGT1 are turned on and the high-level test video signal T_VIDEO is applied to the source bus lines SL1 and SL2, as in the case where the sampling switch has no blocking failure.
- the sampling switches TGU1 and TBU1 are switched from the source bus line SL2 as in the case where the sampling switch has no blocking failure.
- the high-level test video signal T_VIDEO is also applied to the source bus line SL3.
- a high-level voltage is applied to the source bus lines SL1 to SL3.
- a white display is performed even though there is a sampling switch having a poor cutoff.
- FIG. 16 is a signal waveform diagram showing changes in the potentials of source bus lines SL1 to SL3 when the G / B write test is performed. At this time, during the first period T1, among the distribution control signals, ASW1 and ASW3 are set to the high level.
- the sampling switch If the sampling switch has no interruption, it operates as follows. In the first period T1, the inspection switches TGT1 and TBT1 are turned on because T_ASW2 and T_ASW3 are at a high level for the inspection distribution control signal. As a result, the high-level test video signal T_VIDEO is applied to the source bus lines SL2 and SL3 via the test switches TGT1 and TBT1. Further, in the first period T1, since the U_ASW1 and U_ASW3 are at a high level for the normal distribution control signal, the sampling switches TRU1 and TBU1 are turned on.
- the high-level test video signal T_VIDEO is also applied to the source bus line SL1 from the source bus line SL3 via the sampling switches TBU1 and TRU1.
- a high-level voltage is applied to the source bus lines SL1 to SL3.
- white display is performed in a line area including only normal sampling switches.
- the sampling switch has an interruption failure, it operates as follows. In this case, it is assumed that the sampling switch TRU1 has a cutoff failure. In the first period T1, the inspection switches TGT1 and TBT1 are turned on and the high-level test video signal T_VIDEO is applied to the source bus lines SL2 and SL3, as in the case where there is no shutoff failure in the sampling switch. In the first period T1, U_ASW1 and U_ASW3 are at a high level for the normal distribution control signal. However, since it is assumed that the sampling switch TRU1 is defective in blocking, only the sampling switch TBU1 is in the ON state. Become.
- the test video signal T_VIDEO is not applied to the source bus line SL1.
- a high level voltage is applied to the source bus lines SL2 and SL3, and an intermediate level voltage is applied to the source bus line SL1.
- white display is not performed in the area of the line where the sampling switch with poor interruption exists.
- the sampling switch and the inspection switch are turned on based on a certain distribution control signal when the test video signal T_VIDEO is at the high level, if there is no sampling switch having an open defect, 1 A high level voltage is applied to only one source bus line among the three source bus lines constituting the set of video signal line groups.
- a high level voltage is applied to two or more source bus lines of the three source bus lines constituting a set of video signal line groups.
- the charge accumulated in one source bus line is distributed to two or more source bus lines.
- the sampling switch and the inspection switch are turned on based on the two distribution control signals when the test video signal T_VIDEO is at the high level, one set is obtained if there is no shut-off failure sampling switch.
- a high level voltage is applied to all of the three source bus lines constituting the video signal line group.
- a high-level voltage is applied only to two source bus lines of the three source bus lines that constitute a set of video signal line groups. Can occur. Specifically, if there is a sampling switch with poor shutoff, sampling is performed based on all combinations of two distribution control signals among the three distribution control signals when the test video signal T_VIDEO is at a high level. When the switch and the inspection switch are turned on, a high level voltage is necessarily applied to only two source bus lines of the three source bus lines that constitute a set of video signal line groups. As a result, it is possible to detect a sampling switch failure when performing panel inspection.
- the circuit scale does not increase as compared with the conventional example. . For this reason, a narrow frame of the panel can be achieved. Furthermore, since the sampling switch is arranged on one end side of the source bus line and the inspection switch is arranged on the other end side of the source bus line, the sampling switch side (source driver side) with reference to the display unit (pixel circuit unit) ) Can be easily narrowed.
- the transmission of the inspection distribution control signal given to the distribution unit 31 in the second distribution circuit 30 is controlled by the three switches SW1 to SW3, so that the test distribution control signal is supplied to the source bus line.
- the output of the video signal T_VIDEO is controlled, the present invention is not limited to this.
- a switch for example, a thin film transistor for controlling the output of the test video signal T_VIDEO to each source bus line is provided between the distribution unit 31 and the pixel circuit unit 10. May be.
- a switch for example, a thin film transistor
- the test video signal T_VIDEO is connected between the signal line for transmitting the test video signal T_VIDEO and the sampling switch in the distribution unit 31. You may make it the structure provided with the switch (for example, thin-film transistor) which controls transmission.
- the operation control unit is realized by a plurality of switches in the region indicated by reference numeral 33, and in the configuration shown in FIG. 18, the operation is performed by a plurality of switches in the region indicated by reference numeral 34.
- a control unit is realized.
- the panel inspection can be performed without increasing the frame area in the direction perpendicular to the direction in which the source bus line extends (direction in which the gate bus line extends) as compared with the first embodiment.
- a liquid crystal panel that can detect a failure of a sampling switch that operates normally is realized.
- FIG. 19 is a circuit diagram showing a detailed configuration of the first distribution circuit 20 and the second distribution circuit 30 in the second embodiment of the present invention.
- FIG. 1 shows only six source bus lines SL1 to SL6 among the plurality of source bus lines. Since the entire configuration of the liquid crystal panel is the same as that of the first embodiment, description thereof is omitted (see FIGS. 2 and 3).
- the first distribution circuit 20 is provided with a 1-input 6-output demultiplexer for every 6 source bus lines.
- the distribution unit 35 in the second distribution circuit 30 is also provided with a 1-input 6-output demultiplexer for every 6 source bus lines.
- the first distribution circuit 20 is provided with six sampling switches TRU1, TGU1, TBU1, TRU2, TGU2, and TBU2.
- the distribution unit 35 in the second distribution circuit 30 is provided with six inspection switches TRT1, TGT1, TBT1, TRT2, TGT2, and TBT2.
- the operation control unit 36 is provided with six switches SW1 to SW6. The on / off states of the six switches SW1 to SW6 are controlled by a control signal T_SMP sent from the outside, as in the first embodiment.
- the on / off states of the sampling switches TRU1, TGU1, TBU1, TRU2, TGU2, and TBU2 are controlled by control signals U_ASW1, U_ASW2, U_ASW3, U_ASW4, U_ASW5 and U_ASW6, respectively.
- the on / off states of the inspection switches TRT1, TGT1, TBT1, TRT2, TGT2, and TBT2 are controlled by control signals T_ASW1, T_ASW2, T_ASW3, T_ASW4, T_ASW5, and T_ASW6, respectively.
- distribution control signals ASW1 to ASW6 are given from the outside.
- Distribution control signals ASW1, ASW2, ASW3, ASW4, ASW5, and ASW6 are applied to first distribution circuit 20 as normal distribution control signals U_ASW1, U_ASW2, U_ASW3, U_ASW4, U_ASW5, and U_ASW6, respectively.
- the distribution control signals ASW1, ASW2, ASW3, ASW4, ASW5, and ASW6 are respectively the inspection distribution control signals T_ASW6, T_ASW1, T_ASW2, T_ASW3, and T_ASW4 when the switches SW1 to SW6 in the operation control unit 36 are on.
- And T_ASW5 are provided to the distribution unit 35 in the second distribution circuit 30.
- the on / off states of the six switches SW1 to SW6 described above are switched between the inspection time and the normal time. Specifically, at the time of inspection, the control signal T_SMP is maintained at a high level and the switches SW1 to SW6 are turned on, and at a normal time, the control signal T_SMP is maintained at a low level and the switches SW1 to SW6 are turned off. Thus, at the time of inspection, the control signals U_ASW1 and T_ASW6 are at a high level during a period in which the control signal ASW1 is at a high level, and the control signals U_ASW2 and T_ASW1 are at a period in which the control signal ASW2 is at a high level.
- the control signals U_ASW3 and T_ASW2 are at a high level during a period when the control signal ASW3 is at a high level, and the control signals U_ASW4 and T_ASW3 are at a high level during a period when the control signal ASW4 is at a high level.
- the control signals U_ASW5 and T_ASW4 are at high level during the period when the control signal ASW5 is at high level, and the control signals U_ASW6 and T_ASW5 are at high level during the period when the control signal ASW6 is at high level.
- the distribution control signal to be set to the high level and the source bus line to which writing is normally performed And the source bus line to which writing is performed at the time of inspection is as shown in FIG.
- the source bus line to which writing is performed at the time of inspection is as shown in FIG.
- the present embodiment when attention is paid to a case where a certain distribution control signal is at a high level, writing is performed on different source bus lines in the normal time and the inspection time.
- the distribution control signal is set to a high level for a predetermined period in the order of ASW2, ASW3, ASW4, ASW5, ASW6, and ASW1.
- the periods indicated by reference numerals T1, T2, T3, T4, T5, and T6 in FIG. 21 are the first period, the second period, the third period, the fourth period, the fifth period, and the It is called 6 periods.
- the switching control signal T_SMP is maintained at a high level throughout the period during which the panel inspection is performed.
- the test video signal T_VIDEO is set to the high level during the first period T1 and the fourth period T4 during the red display inspection, and during the green display inspection.
- the test video signal T_VIDEO is set to the high level during the second period T2 and the fifth period T5, and the test video signal T_VIDEO is set to the high level during the third period T3 and the sixth period T6 during the blue display inspection. Is done.
- FIG. 22 is a signal waveform diagram showing changes in the potentials of the source bus lines SL1 to SL6 when the red display inspection is performed.
- the test video signal T_VIDEO becomes a high level in the first period T1 and the fourth period T4.
- the sampling switch If there is no open failure in the sampling switch, it operates as follows. In the first period T1, since the control signals T_ASW1, U_ASW2 are at a high level, the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. In the second period T2, since the control signals T_ASW2 and U_ASW3 are at a high level, the inspection switch TGT1 and the sampling switch TBU1 are turned on. Thereby, the low-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the inspection switch TBT1 and the sampling switch TRU2 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- the inspection switch TRT2 and the sampling switch TGU2 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus line SL4 via the test switch TRT2.
- the inspection switch TGT2 and the sampling switch TBU2 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL5 via the test switch TGT2.
- the inspection switch TBT2 and the sampling switch TRU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL6 via the test switch TBT2.
- a high level voltage is applied to the source bus lines SL1 and SL4, and a low level voltage is applied to the source bus lines SL2, SL3, SL5, and SL6. Is applied. As a result, red display is performed in a line area including only normal sampling switches.
- the sampling switch has an open failure, it operates as follows.
- the sampling switch TRU1 is defective in opening.
- the inspection switch TRT1 and the sampling switch TGU1 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus line SL1 via the test switch TRT1. Further, since it is assumed that the sampling switch TRU1 is in an open failure, the sampling switch TRU1 is also turned on in the first period T1.
- a high-level test video signal T_VIDEO is supplied from the source bus line SL1 to the source bus line SL2 via the sampling switches TRU1 and TGU1.
- the inspection switch TGT1 and the sampling switch TBU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL2 via the test switch TGT1.
- the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL3 via the sampling switches TRU1 and TBU1.
- the potential of the source bus line SL1 decreases and the potential of the source bus line SL3 increases.
- the inspection switch TBT1 and the sampling switch TRU2 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL3 via the test switch TBT1.
- the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL4 via the sampling switches TRU1 and TRU2.
- the potential of the source bus line SL1 decreases and the potential of the source bus line SL4 increases.
- the inspection switch TRT2 and the sampling switch TGU2 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus line SL4 via the test switch TRT2. Further, since the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL5 via the sampling switches TRU1 and TGU2. As a result, the potential of the source bus line SL1 slightly decreases, and the potential of the source bus line SL5 slightly increases.
- the inspection switch TGT2 and the sampling switch TBU2 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL5 via the test switch TGT2.
- the sampling switch TRU1 is also in the on state, charge is distributed between the source bus line SL1 and the source bus line SL6 via the sampling switches TRU1 and TBU2. As a result, the potential of the source bus line SL1 slightly decreases, and the potential of the source bus line SL6 slightly increases.
- the inspection switch TBT2 and the sampling switch TRU1 are turned on.
- the low-level test video signal T_VIDEO is applied to the source bus line SL6 via the test switch TBT2.
- an intermediate level voltage is applied to the source bus line SL1
- a low level voltage is applied to the source bus lines SL2, SL3, SL5, and SL6.
- a high level voltage is applied to the source bus line SL4.
- red display is not performed in the area of the line where the sampling switch with poor opening exists.
- FIG. 23 is a signal waveform diagram showing changes in the potentials of the source bus lines SL1 to SL6 when the green display inspection is performed
- FIG. 24 is the source bus line SL1 when the blue display inspection is performed
- FIG. 6 is a signal waveform diagram showing changes in potential of .about.SL6.
- the green display is not performed as a result of the green display inspection
- the blue display is not performed as a result of the blue display inspection.
- FIG. 25 shows a signal waveform diagram when ASW1, ASW2, ASW4, and ASW5 among the distribution control signals are set to the high level in the first period T1.
- the switching control signal T_SMP is maintained at a high level throughout the period during which the panel inspection is performed.
- the four normal distribution control signals and the four inspection distribution control signals corresponding to the distribution control signal set to the high level are at the high level.
- the test video signal T_VIDEO is set to the high level in the first period T1.
- FIG. 26 is a signal waveform diagram showing a change in potential of source bus lines SL1 to SL6 when the R / B write test is performed.
- ASW1, ASW2, ASW4, and ASW5 are set to the high level.
- the sampling switch If the sampling switch has no interruption, it operates as follows. In the first period T1, since the T_ASW1, T_ASW3, T_ASW4, and T_ASW6 are at a high level for the inspection distribution control signal, the inspection switches TRT1, TBT1, TRT2, and TBT2 are turned on. As a result, a high-level test video signal T_VIDEO is applied to the source bus lines SL1, SL3, SL4, and SL6 via the test switches TRT1, TBT1, TRT2, and TBT2.
- the sampling switches TRU1, TGU1, TRU2, and TGU2 are turned on.
- the high-level test video signal T_VIDEO applied to the source bus lines SL1 and SL4 is also applied to the source bus lines SL2 and SL5 via the sampling switch that is in the on state.
- a high-level voltage is applied to the source bus lines SL1 to SL6.
- white display is performed in a line area including only normal sampling switches.
- the sampling switch has an interruption failure, it operates as follows. In this case, it is assumed that the sampling switch TRU1 has a cutoff failure. In the first period T1, the inspection switches TRT1, TBT1, TRT2, and TBT2 are turned on and the high-level test video signal T_VIDEO is supplied to the source bus lines SL1, SL3, as in the case where the sampling switch has no blocking failure. Applied to SL4 and SL6. In the first period T1, U_ASW1, U_ASW2, U_ASW4, and U_ASW5 are set to a high level for the normal distribution control signal, but it is assumed that the sampling switch TRU1 is in a cutoff failure, so the sampling switch TGU1, TRU2 and TGU2 are turned on.
- the high-level test video signal T_VIDEO is also applied to the source bus line SL5 from the source bus line SL4 via the sampling switches TRU2 and TGU2. Further, a high-level test video signal T_VIDEO is also applied from the source bus line SL4 to the source bus line SL2 via the sampling switches TRU2 and TGU1. As described above, when the first period T1 ends, a high-level voltage is applied to the source bus lines SL1 to SL6. As a result, for this inspection, a white display is performed even though there is a sampling switch with poor shutoff.
- FIG. 27 is a signal waveform diagram showing a change in potential of source bus lines SL1 to SL6 when the R / G write test is performed.
- ASW2, ASW3, ASW5, and ASW6 are set to the high level.
- the sampling switch does not have an interruption failure, the same operation as the R / B writing inspection described above is performed, and white display is performed.
- the sampling switch has an interruption failure, it operates as follows. In this case, it is assumed that the sampling switch TRU1 has a cutoff failure. In the first period T1, since the T_ASW1, T_ASW2, T_ASW4, and T_ASW5 are at a high level for the inspection distribution control signal, the inspection switches TRT1, TGT1, TRT2, and TGT2 are turned on. Accordingly, the high-level test video signal T_VIDEO is applied to the source bus lines SL1, SL2, SL4, and SL5 via the test switches TRT1, TGT1, TRT2, and TGT2.
- the sampling switches TGU1, TBU1, TGU2, and TBU2 are turned on.
- the high-level test video signal T_VIDEO applied to the source bus lines SL2 and SL5 is also applied to the source bus lines SL3 and SL6 via the sampling switch that is turned on.
- a high-level voltage is applied to the source bus lines SL1 to SL6.
- a white display is performed even though there is a sampling switch having a poor cutoff.
- FIG. 28 is a signal waveform diagram showing a change in potential of source bus lines SL1 to SL6 when the G / B write test is performed.
- ASW1, ASW3, ASW4, and ASW6 are set to the high level.
- the sampling switch does not have an interruption failure, the same operation as the R / B writing inspection described above is performed, and white display is performed.
- the sampling switch has an interruption failure, it operates as follows. In this case, it is assumed that the sampling switch TRU1 has a cutoff failure. In the first period T1, the inspection switches TGT1, TBT1, TGT2, and TBT2 are turned on because T_ASW2, T_ASW3, T_ASW5, and T_ASW6 are at a high level for the inspection distribution control signal. As a result, the high-level test video signal T_VIDEO is applied to the source bus lines SL2, SL3, SL5, and SL6 via the test switches TGT1, TBT1, TGT2, and TBT2.
- the sampling switch TBU1 is assumed to be defective in shutoff.
- TRU2 and TBU2 are turned on.
- the high-level test video signal T_VIDEO applied to the source bus lines SL3 and SL6 is also applied to the source bus line SL4 via the sampling switch that is turned on.
- the sampling switch TRU1 is in the off state, the test video signal T_VIDEO is not applied to the source bus line SL1.
- a liquid crystal panel having a configuration in which a demultiplexer having 1 input and 6 outputs is provided in the first distribution circuit 20 and the second distribution circuit 30 can be used for panel inspection without increasing the circuit scale.
- the configuration of the liquid crystal panel according to the third embodiment of the present invention is the same as the configuration in the first embodiment (see FIGS. 1 to 5).
- the second distribution circuit 30 is used as a circuit for circuit inspection (typically before mounting the driver IC), but in this embodiment, the source bus line is used. Is used as a precharge circuit. Therefore, the second distribution circuit 30 can be used as a panel inspection circuit or a precharge circuit.
- the “test video signal” in the first embodiment is referred to as a “precharge video signal”
- the “inspection switch” in the first embodiment is referred to as a “precharge switch”.
- a so-called line inversion driving method is employed in which the positive / negative polarity of the voltage applied to the liquid crystal layer is inverted for each gate bus line. Accordingly, video signals having different polarities are applied to each source bus line every horizontal scanning period. In FIG. 29, a certain horizontal scanning period is started at time t10, and the next horizontal scanning period is started at time t20.
- the precharge video signal T_VIDEO is fixed at an intermediate gradation potential. In FIG. 29, the video signal VIDEO applied to the source bus line is shown as one waveform, but in reality, video signals having different potentials are applied to each source bus line depending on the image to be displayed. .
- the control signals ASW1 to ASW3 are set to the high level.
- the switches SW1 to SW3 are in the on state. Therefore, at time t10, the control signals U_ASW1 to U_ASW3 and T_ASW1 to T_ASW3 become high level. As a result, all sampling switches and all precharge switches are turned on.
- the first distribution circuit 20 and the source driver 40 are electrically disconnected, and the potential of the video signal VIDEO is indefinite.
- the precharge potential (the potential of the precharge video signal T_VIDEO) is written to all the source bus lines at time t10.
- the control signals ASW1 to ASW3 are set to low level. As a result, all sampling switches and all precharge switches are turned off.
- the control signal T_SMP is set to a low level. As a result, the switches SW1 to SW3 are turned off.
- the first distribution circuit 20 and the source driver 40 are electrically connected, and the video signal VIDEO corresponding to the image to be displayed is supplied from the source driver 40 to the first distribution circuit 20.
- the control signal ASW1 is set to the high level. As a result, the control signal U_ASW1 becomes high level. At this time, since the control signal T_SMP is set to the low level, the switch SW1 is in the off state. Therefore, the control signal T_ASW3 is maintained at a low level. As described above, the sampling switches TRU1, TRU2, ..., TRUn are turned on. As a result, the video signal VIDEO corresponding to the image to be displayed on the red source bus lines SL1, SL4,..., SL (3n-2) is applied. At time t14, the control signal ASW1 is set to low level. Thereby, the control signal U_ASW1 becomes a low level, and the sampling switches TRU1, TRU2,..., TRUn are turned off.
- the period from the time point t15 to the time point t16 depends on the image to be displayed on the green source bus lines SL2, SL5,..., SL (3n-1).
- the video signal VIDEO corresponding to the image to be displayed on the blue source bus lines SL3, SL6,..., SL (3n) is applied during the period from time t17 to time t18.
- control signal T_SMP is set to the high level.
- the switches SW1 to SW3 are turned on.
- the first distribution circuit 20 and the source driver 40 are electrically disconnected, and the potential of the video signal VIDEO becomes indefinite.
- the red, green, and blue colors are used in this order.
- the video signal VIDEO corresponding to the image to be displayed is applied to the source bus line.
- the polarity of the video signal VIDEO applied to the source bus line is opposite between the period from time t13 to time t18 and the period from time t23 to time t28.
- the first distribution circuit 20 including the demultiplexer for outputting the video signal VIDEO to the plurality of source bus lines is provided on one end side of the source bus line, and the other end of the source bus line is provided.
- a second distribution circuit 30 including a demultiplexer for outputting a predetermined input signal to a plurality of source bus lines is provided on the side.
- the precharge video signal T_VIDEO fixed to the potential of the intermediate gradation is supplied to the second distribution circuit 30 as the predetermined input signal. Then, in the first predetermined period of each horizontal scanning period, all the switches constituting the demultiplexer in the second distribution circuit 30 are turned on.
- the precharge potential is written to all the source bus lines. Thereafter, all the switches constituting the demultiplexer in the second distribution circuit 30 are turned off, and the video signal VIDEO corresponding to the image to be displayed is applied to each source bus line from the first distribution circuit 20 side.
- the source bus line is precharged in each horizontal scanning period, the time to reach the target applied voltage is shortened in each pixel forming portion, and the display quality is improved.
- the circuit configuration (the configuration of the first distribution circuit 20 and the second distribution circuit 30) is the same as that of the first embodiment. Therefore, by providing a circuit with a relatively simple configuration, it is possible to detect the failure of the sampling switch that normally operates during panel inspection, and it is possible to precharge the source bus line. As a result, the display quality can be improved.
- the video signal VIDEO corresponding to the image to be displayed in the order of red, green, and blue is supplied to the source bus line.
- the present invention is not limited to this.
- the precharge potential and the video signal potential can be written to the source bus lines in the order of blue, green, and red.
- a method for driving the source bus line in the present modification will be described with reference to FIG. In this modification as well, the precharge video signal T_VIDEO is fixed at a potential of intermediate gradation.
- the control signal ASW1 is set to the high level.
- the switch SW1 since the control signal T_SMP is at a high level, the switch SW1 is in an ON state. Therefore, at time t10, the control signals U_ASW1 and T_ASW3 become high level. Thereby, sampling switches TRU1, TRU2,..., TRUn and precharge switches TBT1, TBT2,..., TBTn are turned on.
- the potential of the video signal VIDEO is written to the red source bus lines SL1, SL4,..., SL (3n-2), and the blue source bus lines SL3, SL6 are written. ,..., SL (3n) is written with a precharge potential.
- the potential of the video signal VIDEO at the time point t10 is a temporary potential, and the original writing to the red source bus lines SL1, SL4,..., SL (3n-2) is performed at a time point as described later. Performed at t17.
- the control signal ASW1 is set to low level.
- the control signals U_ASW1 and T_ASW3 become low level, and the sampling switches TRU1, TRU2,..., TRUn and the precharge switches TBT1, TBT2,.
- the control signal ASW3 is set to the high level. For this reason, the control signals U_ASW3 and T_ASW2 become high level. Thereby, the sampling switches TBU1, TBU2,..., TBUn and the precharge switches TGT1, TGT2,..., TGTn are turned on. As described above, at time t12, the potential of the video signal VIDEO is written to the blue source bus lines SL3, SL6,..., SL (3n), and the green source bus lines SL2, SL5,. ... A precharge potential is written to SL (3n-1). At time t13, the control signal ASW3 is set to low level. As a result, the control signals U_ASW3 and T_ASW2 become low level, and the sampling switches TBU1, TBU2,..., TUn and the precharge switches TGT1, TGT2,.
- the potential of the video signal VIDEO is written to the green source bus lines SL2, SL5,..., SL (3n-1), and the red source bus is processed in the same manner as at time t12.
- a precharge potential is written to the lines SL1, SL4,..., SL (3n-2).
- the control signal ASW2 becomes low level at time t15, at time t16, the control signal T_SMP is changed to low level. As a result, the switches SW1 to SW3 are turned off, and all the precharge switches are turned off. At time t17, the control signal ASW1 is set to high level. As a result, the control signal U_ASW1 becomes high level. At this time, since the switch SW1 is in an off state, the control signal T_ASW3 is maintained at a low level. As described above, the sampling switches TRU1, TRU2, ..., TRUn are turned on. As a result, the potential of the video signal VIDEO is written to the red source bus lines SL1, SL4,..., SL (3n-2).
- the control signal ASW1 is set to low level. Thereby, the control signal U_ASW1 becomes a low level, and the sampling switches TRU1, TRU2,..., TRUn are turned off.
- the control signal T_SMP is set to high level. As a result, the switches SW1 to SW3 are turned on.
- the liquid crystal panel has been described as an example, but the present invention is not limited to this.
- the present invention can also be applied to a display panel other than a liquid crystal panel such as an organic EL (Electro Luminescence) panel.
- DESCRIPTION OF SYMBOLS 10 ... Pixel circuit part 20 ... 1st distribution circuit 30 ... 2nd distribution circuit 31, 35 ... Distribution part 32, 33, 34, 36 ... Operation control part 40 ...
- Source driver (video signal line drive circuit) DMU1 to DMUn, DMT1 to DMTn ... Demultiplexer SL1 to SL (3n) ... Source bus line TRT1 to TRTn, TGT1 to TGTn, TBT1 to TBTn, ... Inspection switch TRU1 to TRUn, TGU1 to TGUn, TBU1 to TBUn, ... Switches ASW1 to ASW6 ... Distribution control signal U_ASW1 to U_ASW6 ... Normal distribution control signal T_ASW1 to T_ASW6 ... Inspection distribution control signal T_SMP ... Switching control signal T_VIDEO ... Test video signal
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Abstract
Description
表示パネルであって、
n本毎(nは2以上の自然数)に1組の映像信号線群を構成する複数本の映像信号線が配設された表示部と、
前記複数本の映像信号線の一端側に前記1組の映像信号線群毎に設けられ、外部から送られる第1の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第1スイッチからなる第1のデマルチプレクサと、
前記複数本の映像信号線の他端側に前記1組の映像信号線群毎に設けられ、外部から送られる第2の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第2スイッチからなる第2のデマルチプレクサと、
前記複数本の映像信号線への前記第2の映像信号の印加を可能とするか否かを切り替える動作制御部と
を備え、
前記第1のデマルチプレクサに含まれる前記n個の第1スイッチの状態は、互いに異なるn個の制御信号によって制御され、
前記第2のデマルチプレクサに含まれる前記n個の第2スイッチの状態は、互いに異なる前記n個の制御信号によって制御され、
前記n個の制御信号のうちの任意の制御信号を着目制御信号としたとき、各映像信号線群について、前記着目制御信号によってオン状態にされる第1スイッチに接続された映像信号線と前記着目制御信号によってオン状態にされる第2スイッチに接続された映像信号線とは異なることを特徴とする。
前記動作制御部は、前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのそれぞれに対応して設けられるn個の制御スイッチからなり、
各制御スイッチは、外部から与えられる切替制御信号に基づいて、前記第2スイッチに前記制御信号を与えるか否かを制御することを特徴とする。
前記動作制御部は、前記第2のデマルチプレクサの出力部と前記表示部との間に前記複数本の映像信号線のそれぞれに対応して設けられる複数個の制御スイッチからなり、
各制御スイッチは、外部から与えられる切替制御信号に基づいて、前記第2のデマルチプレクサの出力部から前記複数本の映像信号線への前記第2の映像信号の印加を可能とするか否かを切り替えることを特徴とする。
前記動作制御部は、前記第2のデマルチプレクサの入力部近傍に前記複数本の映像信号線のそれぞれに対応して設けられる複数個の制御スイッチからなり、
各制御スイッチは、外部から与えられる切替制御信号に基づいて、前記第2の映像信号を前記第2のデマルチプレクサの入力部に与えるか否かを切り替えることを特徴とする。
前記第2の映像信号は、前記複数本の映像信号線の他端側に設けられている全ての第2のデマルチプレクサの入力部に共通的に与えられていることを特徴とする。
前記第1のデマルチプレクサに含まれる前記n個の第1スイッチおよび前記第2のデマルチプレクサに含まれる前記n個の第2スイッチは、薄膜トランジスタであることを特徴とする。
前記第1のデマルチプレクサに前記第1の映像信号を与える映像信号線駆動回路が前記表示パネルに実装されていることを特徴とする。
前記動作制御部が前記複数本の映像信号線への前記第2の映像信号の印加を可能とする検査準備ステップと、
前記第2の映像信号の信号レベルが所定の第1レベルになっているときに、各映像信号線群に対応して設けられている前記第1のデマルチプレクサに含まれる前記n個の第1スイッチのうちの1つおよび各映像信号線群に対応して設けられている前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのうちの1つが所定期間オン状態で維持されるように前記n個の制御信号のうちの1つの信号レベルを変化させる第1レベル印加ステップと、
前記第2の映像信号の信号レベルが前記第1レベルとは異なる第2レベルになっているときに、各映像信号線群に対応して設けられている前記第1のデマルチプレクサに含まれる前記n個の第1スイッチのうちの1つおよび各映像信号線群に対応して設けられている前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのうちの1つが所定期間オン状態で維持されるように前記n個の制御信号のうちの1つの信号レベルを変化させる第2レベル印加ステップと
を含み、
前記n個の制御信号のうちの任意の制御信号を着目制御信号としたとき、各映像信号線群について、前記着目制御信号によってオン状態にされる第1スイッチに接続された映像信号線と前記着目制御信号によってオン状態にされる第2スイッチに接続された映像信号線とは異なり、
検査対象の表示色に対応する映像信号線には前記第1レベルの前記第2の映像信号が印加されるよう前記第1レベル印加ステップが行われ、
検査対象以外の表示色に対応する映像信号線には前記第2レベルの前記第2の映像信号が印加されるよう前記第2レベル印加ステップが行われることを特徴とする。
前記動作制御部が前記複数本の映像信号線への前記第2の映像信号の印加を可能とする検査準備ステップと、
前記第2の映像信号の信号レベルが所定の第1レベルになっているときに、各映像信号線群に対応して設けられている前記第1のデマルチプレクサに含まれる前記n個の第1スイッチのうちのm個(mはn未満の自然数)および各映像信号線群に対応して設けられている前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのうちのm個が所定期間オン状態で維持されるように前記n個の制御信号のうちのm個の信号レベルを変化させるmライン書き込みステップと
を含み、
前記n個の制御信号のうちの任意の制御信号を着目制御信号としたとき、各映像信号線群について、前記着目制御信号によってオン状態にされる第1スイッチに接続された映像信号線と前記着目制御信号によってオン状態にされる第2スイッチに接続された映像信号線とは異なることを特徴とする。
<1.1 全体構成>
図2は、本発明の第1の実施形態に係る液晶パネルの要部の構成を示すブロック図である。この液晶パネルは、図2に示すように、画像を表示する領域となる画素回路部10と、外部から送られる信号を複数の信号線に切り替えつつ出力する機能を有する第1の分配回路20および第2の分配回路30とによって構成されている。これら画素回路部10,第1の分配回路20,および第2の分配回路30は、液晶パネルを構成する2枚のガラス基板のうちの一方のガラス基板(一般に「アレイ基板」と呼ばれている)上に形成されている。
図1は、第1の分配回路20および第2の分配回路30の構成を示す回路図である。なお、図1には、複数本のソースバスラインのうちの6本のソースバスラインSL1~SL6のみを示している。第1の分配回路20には、1つの入力信号を複数の信号線に切り替えつつ出力する複数個のデマルチプレクサが含まれている。詳しくは、図4に示すように、赤色用,緑色用,および青色用の3本のソースバスライン毎に1入力3出力のデマルチプレクサが設けられている。1入力3出力であるので、各デマルチプレクサには3個のスイッチ(例えば薄膜トランジスタ)が含まれている。これらのスイッチのことを以下「サンプリングスイッチ」という。
次に、図8~図16を参照しつつ、本実施形態に係る液晶パネルの検査方法について説明する。以下において、まず、サンプリングスイッチの開放不良を検出するためのパネル検査の方法について説明し、次に、サンプリングスイッチの遮断不良を検出するためのパネル検査の方法について説明する。開放不良とは、サンプリングスイッチをオフ状態にすることができなくなっている(常にオン状態になっている)ことをいい、遮断不良とは、サンプリングスイッチをオン状態にすることができなくなっている(常にオフ状態になっている)ことをいう。なお、以下のパネル検査に関し、「テスト用映像信号T_VIDEOの書き込みが行われる前には、ソースバスラインの電位は中間階調のレベルになっている」と仮定する。以下、ソースバスラインSL1~SL3と、サンプリングスイッチTRU1,TGU1,およびTBU1と、検査用スイッチTRT1,TGT1,およびTBT1とに着目して説明する。
開放不良を検出するためのパネル検査の際には、図8に示すように、例えばASW2、ASW3、ASW1の順序で分配制御信号が所定期間ずつハイレベルとされる。なお、図8で符号T1,T2,およびT3で示す期間のことを、以下、それぞれ第1期間,第2期間,および第3期間という。切替制御信号T_SMPについては、上述したように、パネル検査が行われている期間を通じてハイレベルで維持される。これにより、通常用分配制御信号については、第1期間T1にはU_ASW2がハイレベルとなり、第2期間T2にはU_ASW3がハイレベルとなり、第3期間T3にはU_ASW1がハイレベルとなる。検査用分配制御信号については、第1期間T1にはT_ASW1がハイレベルとなり、第2期間T2にはT_ASW2がハイレベルとなり、第3期間T3にはT_ASW3がハイレベルとなる。ところで、この検査には、赤色表示の検査,緑色表示の検査,および青色表示の検査が含まれている。図8に示すように、赤色表示の検査の際には第1期間T1にのみテスト用映像信号T_VIDEOがハイレベルにされ、緑色表示の検査の際には第2期間T2にのみテスト用映像信号T_VIDEOがハイレベルにされ、青色表示の検査の際には第3期間T3にのみテスト用映像信号T_VIDEOがハイレベルにされる。例えば、共通電極の電圧を0Vとすると、テスト用映像信号T_VIDEOの電圧は、ハイレベルのときには5Vにされ、ローレベルのときには0Vにされる。
図9は、赤色表示の検査が行われるときのソースバスラインSL1~SL3の電位の変化を示す信号波形図である。このとき、上述したように、テスト用映像信号T_VIDEOについては第1期間T1にのみハイレベルとなる。
図11は、緑色表示の検査が行われるときのソースバスラインSL1~SL3の電位の変化を示す信号波形図である。このとき、上述したように、テスト用映像信号T_VIDEOについては第2期間T2にのみハイレベルとなる。
図12は、青色表示の検査が行われるときのソースバスラインSL1~SL3の電位の変化を示す信号波形図である。このとき、上述したように、テスト用映像信号T_VIDEOについては第3期間T3にのみハイレベルとなる。
以上のように、正常なサンプリングスイッチのみを含むラインの領域では、赤色表示,緑色表示,および青色表示の全てが正常に行われる。一方、開放不良のサンプリングスイッチが存在するラインの領域では、赤色表示,緑色表示,および青色表示の全てもしくは一部が正常に行われない。これにより、サンプリングスイッチの開放不良を検出することができる。
遮断不良を検出するためのパネル検査の際には、分配制御信号ASW1~ASW3のうちいずれか2つが所定期間(第1期間T1)ハイレベルとされる。図13には、分配制御信号のうちASW1とASW2とが第1期間T1にハイレベルにされる場合の信号波形図を示している。切替制御信号T_SMPについては、上述したように、パネル検査が行われている期間を通じてハイレベルで維持される。これにより、第1期間T1には、ハイレベルにされた分配制御信号に対応する2つの通常用分配制御信号および2つの検査用分配制御信号がハイレベルとなる。テスト用映像信号T_VIDEOについては、第1期間T1にハイレベルとされる。ところで、この検査には、赤色用および青色用のソースバスラインへの書き込み検査(以下、「R/B書込検査」という。)と、赤色用および緑色用のソースバスラインへの書き込み検査(以下、「R/G書込検査」という。)と、緑色用および青色用のソースバスラインへの書き込み検査(以下、「G/B書込検査」という。)とが含まれている。
図14は、R/B書込検査が行われるときのソースバスラインSL1~SL3の電位の変化を示す信号波形図である。このとき、第1期間T1には、分配制御信号のうちASW1とASW2とがハイレベルにされる。
図15は、R/G書込検査が行われるときのソースバスラインSL1~SL3の電位の変化を示す信号波形図である。このとき、第1期間T1には、分配制御信号のうちASW2とASW3とがハイレベルにされる。
図16は、G/B書込検査が行われるときのソースバスラインSL1~SL3の電位の変化を示す信号波形図である。このとき、第1期間T1には、分配制御信号のうちASW1とASW3とがハイレベルにされる。
以上のように、正常なサンプリングスイッチのみを含むラインの領域では、R/B書込検査,R/G書込検査,およびG/B書込検査の全てにおいて白色表示が行われる。一方、遮断不良のサンプリングスイッチが存在するラインの領域では、R/B書込検査,R/G書込検査,およびG/B書込検査の全てもしくは一部において白色表示が行われない。これにより、サンプリングスイッチの遮断不良を検出することができる。
本実施形態によれば、サンプリングスイッチおよび検査用スイッチのオン/オフ状態を制御する3つの分配制御信号のうちの任意の信号を着目制御信号としたとき、着目制御信号によってオン状態にされるサンプリングスイッチに接続されたソースバスラインと着目制御信号によってオン状態にされる検査用スイッチに接続されたソースバスラインとは異なっている。このため、テスト用映像信号T_VIDEOがハイレベルになっているときに或る分配制御信号に基づいてサンプリングスイッチと検査用スイッチとをオン状態にすると、開放不良のサンプリングスイッチが存在しなければ、1組の映像信号線群を構成する3本のソースバスラインのうち1本のソースバスラインのみにハイレベルの電圧が印加される。これに対して、開放不良のサンプリングスイッチが存在すれば、1組の映像信号線群を構成する3本のソースバスラインのうち2本以上のソースバスラインにハイレベルの電圧が印加されることや1本のソースバスラインに蓄積されていた電荷が2本以上のソースバスラインに分配されることが生じる。これにより、パネル検査の際に、サンプリングスイッチの開放不良を検出することができる。また、テスト用映像信号T_VIDEOがハイレベルになっているときに2つの分配制御信号に基づいてサンプリングスイッチと検査用スイッチとをオン状態にすると、遮断不良のサンプリングスイッチが存在しなければ、1組の映像信号線群を構成する3本のソースバスラインの全てにハイレベルの電圧が印加される。これに対して、遮断不良のサンプリングスイッチが存在すれば、1組の映像信号線群を構成する3本のソースバスラインのうち2本のソースバスラインのみにハイレベルの電圧が印加されることが生じ得る。詳しくは、遮断不良のサンプリングスイッチが存在すれば、テスト用映像信号T_VIDEOがハイレベルになっているときに、3つの分配制御信号のうちの2つの分配制御信号についての全ての組み合わせに基づいてサンプリングスイッチおよび検査用スイッチをオン状態にすると、1組の映像信号線群を構成する3本のソースバスラインのうち2本のソースバスラインのみにハイレベルの電圧が印加されることが必ず生じる。これにより、パネル検査の際に、サンプリングスイッチの遮断不良を検出することができる。
上記第1の実施形態においては、第2の分配回路30内の分配部31に与えられる検査用分配制御信号の伝達を3個のスイッチSW1~SW3で制御することによってソースバスラインへのテスト用映像信号T_VIDEOの出力が制御されていたが、本発明はこれに限定されない。例えば、図17において符号33で示すように、分配部31と画素回路部10との間に各ソースバスラインへのテスト用映像信号T_VIDEOの出力を制御するスイッチ(例えば、薄膜トランジスタ)を備える構成にしても良い。また、図17に示した構成に代えて、図18において符号34で示すように、テスト用映像信号T_VIDEOを伝達する信号線と分配部31内のサンプリングスイッチとの間にテスト用映像信号T_VIDEOの伝達を制御するスイッチ(例えば、薄膜トランジスタ)を備える構成にしても良い。なお、図17に示す構成においては、符号33で示す領域内の複数個のスイッチによって動作制御部が実現され、図18に示す構成においては、符号34で示す領域内の複数個のスイッチによって動作制御部が実現されている。
<2.1 分配回路の構成および動作>
図19は、本発明の第2の実施形態における第1の分配回路20および第2の分配回路30の詳細な構成を示す回路図である。なお、図1には、複数本のソースバスラインのうちの6本のソースバスラインSL1~SL6のみを示している。液晶パネルの全体構成については、上記第1の実施形態と同様であるので説明を省略する(図2,図3参照)。本実施形態においては、上記第1の実施形態とは異なり、第1の分配回路20には、6本のソースバスライン毎に1入力6出力のデマルチプレクサが設けられている。同様に、第2の分配回路30内の分配部35にも、6本のソースバスライン毎に1入力6出力のデマルチプレクサが設けられている。図19に示す6本のソースバスラインSL1~SL6に対応する構成要素に着目すると、第1の分配回路20には、6個のサンプリングスイッチTRU1,TGU1,TBU1,TRU2,TGU2,およびTBU2が設けられ、第2の分配回路30内の分配部35には、6個の検査用スイッチTRT1,TGT1,TBT1,TRT2,TGT2,およびTBT2が設けられている。また、1入力6出力のデマルチプレクサが分配部35に設けられているので、動作制御部36には6個のスイッチSW1~SW6が設けられている。これら6個のスイッチSW1~SW6のオン/オフ状態は、上記第1の実施形態と同様、外部から送られる制御信号T_SMPによって制御される。
次に、図21~図28を参照しつつ、本実施形態に係る液晶パネルの検査方法について説明する。なお、上記第1の実施形態と同様、以下のパネル検査に関し、「テスト用映像信号T_VIDEOの書き込みが行われる前には、ソースバスラインの電位は中間階調のレベルになっている」と仮定する。以下、ソースバスラインSL1~SL6と、サンプリングスイッチTRU1,TGU1,TBU1,TRU2,TGU2,およびTBU2と、検査用スイッチTRT1,TGT1,TBT1,TRT2,TGT2,およびTBT2とに着目して説明する。
開放不良を検出するためのパネル検査の際には、図21に示すように、例えばASW2、ASW3、ASW4、ASW5、ASW6、ASW1の順序で分配制御信号が所定期間ずつハイレベルとされる。なお、図21で符号T1,T2,T3,T4,T5,およびT6で示す期間のことを、以下、それぞれ第1期間,第2期間,第3期間,第4期間,第5期間,および第6期間という。切替制御信号T_SMPについては、上述したように、パネル検査が行われている期間を通じてハイレベルで維持される。これにより、通常用分配制御信号については、第1期間T1,第2期間T2,第3期間T3,第4期間T4,第5期間T5,および第6期間T6には、それぞれU_ASW2,U_ASW3,U_ASW4,U_ASW5,U_ASW6,およびU_ASW1がハイレベルとなる。検査用分配制御信号については、第1期間T1,第2期間T2,第3期間T3,第4期間T4,第5期間T5,および第6期間T6には、それぞれT_ASW1,T_ASW2,T_ASW3,T_ASW4,T_ASW5,およびT_ASW6がハイレベルとなる。また、本実施形態においては、図21に示すように、赤色表示の検査の際には第1期間T1および第4期間T4にテスト用映像信号T_VIDEOがハイレベルにされ、緑色表示の検査の際には第2期間T2および第5期間T5にテスト用映像信号T_VIDEOがハイレベルにされ、青色表示の検査の際には第3期間T3および第6期間T6にテスト用映像信号T_VIDEOがハイレベルにされる。
遮断不良を検出するためのパネル検査の際には、分配制御信号ASW1~ASW6のうちの4つが所定期間(第1期間T1)ハイレベルとされる。具体的には、R/B書込検査の際にはASW1,ASW2,ASW4,およびASW5がハイレベルにされ、R/G書込検査の際にはASW2,ASW3,ASW5,およびASW6がハイレベルにされ、G/B書込検査の際にはASW1,ASW3,ASW4,およびASW6がハイレベルにされる。図25には、分配制御信号のうちASW1,ASW2,ASW4,およびASW5が第1期間T1にハイレベルにされる場合の信号波形図を示している。切替制御信号T_SMPについては、上述したように、パネル検査が行われている期間を通じてハイレベルで維持される。これにより、第1期間T1には、ハイレベルにされた分配制御信号に対応する4つの通常用分配制御信号および4つの検査用分配制御信号がハイレベルとなる。テスト用映像信号T_VIDEOについては、第1期間T1にハイレベルとされる。
図26は、R/B書込検査が行われるときのソースバスラインSL1~SL6の電位の変化を示す信号波形図である。このとき、第1期間T1には、分配制御信号のうちASW1,ASW2,ASW4,およびASW5がハイレベルにされる。
図27は、R/G書込検査が行われるときのソースバスラインSL1~SL6の電位の変化を示す信号波形図である。このとき、第1期間T1には、分配制御信号のうちASW2,ASW3,ASW5,およびASW6がハイレベルにされる。サンプリングスイッチに遮断不良がない場合には、上述したR/B書込検査と同様の動作が行われ、白色表示が行われる。
図28は、G/B書込検査が行われるときのソースバスラインSL1~SL6の電位の変化を示す信号波形図である。このとき、第1期間T1には、分配制御信号のうちASW1,ASW3,ASW4,およびASW6がハイレベルにされる。サンプリングスイッチに遮断不良がない場合には、上述したR/B書込検査と同様の動作が行われ、白色表示が行われる。
以上のように、本実施形態においても、遮断不良のサンプリングスイッチが存在するラインの領域では、R/B書込検査,R/G書込検査,およびG/B書込検査の全てもしくは一部において白色表示が行われない。これにより、1入力6出力のデマルチプレクサが第1の分配回路20に設けられた構成においても、サンプリングスイッチの遮断不良を検出することができる。
本実施形態によれば、第1の分配回路20および第2の分配回路30に1入力6出力のデマルチプレクサが設けられた構成の液晶パネルに関し、回路規模を増大させることなく、パネル検査の際に通常時に動作するサンプリングスイッチの不良をも検出することが可能となる。
<3.1 構成>
本発明の第3の実施形態に係る液晶パネルの構成は、第1の実施形態における構成と同様である(図1~図5参照)。第1の実施形態においては、第2の分配回路30は(典型的にはドライバICを実装する前の)パネル検査用の回路として用いられていたが、本実施形態においては、ソースバスラインについてのプリチャージ(予備充電)用の回路として用いられる。従って、この第2の分配回路30は、パネル検査用の回路として用いられることもできるし、プリチャージ用の回路として用いられることもできる。なお、説明の便宜上、第1の実施形態における「テスト用映像信号」のことを「プリチャージ用映像信号」といい、第1の実施形態における「検査用スイッチ」のことを「プリチャージ用スイッチ」という。
以下、図29を参照しつつ、第2の分配回路30がプリチャージ用の回路として用いられるときのソースバスラインの駆動方法について説明する。なお、本実施形態においては、液晶層への印加電圧の正負極性を1ゲートバスライン毎に反転させるいわゆるライン反転駆動方式が採用されている。従って、各ソースバスラインには1水平走査期間毎に極性の異なる映像信号が印加される。図29では、時点t10に或る水平走査期間が開始され、時点t20に次の水平走査期間が開始されている。プリチャージ用映像信号T_VIDEOについては、中間階調の電位に固定されている。なお、図29ではソースバスラインに印加される映像信号VIDEOを1つの波形で示しているが、実際には、表示すべき画像に応じて異なる電位の映像信号が各ソースバスラインに印加される。
本実施形態によれば、ソースバスラインの一端側には、映像信号VIDEOを複数のソースバスラインに出力するためのデマルチプレクサを含む第1の分配回路20が設けられ、ソースバスラインの他端側には、所定の入力信号を複数のソースバスラインに出力するためのデマルチプレクサを含む第2の分配回路30が設けられている。このような構成において、中間階調の電位に固定されたプリチャージ用映像信号T_VIDEOが上記所定の入力信号として第2の分配回路30に与えられる。そして、各水平走査期間の最初の所定期間において、第2の分配回路30内のデマルチプレクサを構成する全てのスイッチがオン状態にされる。これにより、全てのソースバスラインにプリチャージ電位が書き込まれる。その後、第2の分配回路30内のデマルチプレクサを構成する全てのスイッチはオフ状態にされ、表示すべき画像に応じた映像信号VIDEOが第1の分配回路20側から各ソースバスラインに印加される。このように、各水平走査期間においてソースバスラインへのプリチャージが行われるので、各画素形成部において目標印加電圧への到達時間が短縮され、表示品位が改善される。
上記第3の実施形態においては、全てのソースバスラインにプリチャージ電位が書き込まれた後、赤色用、緑色用、青色用の順序で表示すべき画像に応じた映像信号VIDEOのソースバスラインへの印加が行われているが、本発明はこれに限定されない。以下のように、青色用、緑色用、赤色用の順序でソースバスラインへのプリチャージ電位の書き込みと映像信号電位の書き込みとが行われるようにすることもできる。以下、図30を参照しつつ、本変形例におけるソースバスラインの駆動方法について説明する。なお、本変形例においても、プリチャージ用映像信号T_VIDEOは、中間階調の電位に固定されている。
上記各実施形態においては液晶パネルを例に挙げて説明したが、本発明はこれに限定されない。有機EL(Electro Luminescence)パネルなど液晶パネル以外の表示パネルにも本発明を適用することができる。
20…第1の分配回路
30…第2の分配回路
31,35…分配部
32,33,34,36…動作制御部
40…ソースドライバ(映像信号線駆動回路)
DMU1~DMUn,DMT1~DMTn…デマルチプレクサ
SL1~SL(3n)…ソースバスライン
TRT1~TRTn,TGT1~TGTn,TBT1~TBTn,…検査用スイッチ
TRU1~TRUn,TGU1~TGUn,TBU1~TBUn,…サンプリングスイッチ
ASW1~ASW6…分配制御信号
U_ASW1~U_ASW6…通常用分配制御信号
T_ASW1~T_ASW6…検査用分配制御信号
T_SMP…切替制御信号
T_VIDEO…テスト用映像信号
Claims (9)
- 表示パネルであって、
n本毎(nは2以上の自然数)に1組の映像信号線群を構成する複数本の映像信号線が配設された表示部と、
前記複数本の映像信号線の一端側に前記1組の映像信号線群毎に設けられ、外部から送られる第1の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第1スイッチからなる第1のデマルチプレクサと、
前記複数本の映像信号線の他端側に前記1組の映像信号線群毎に設けられ、外部から送られる第2の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第2スイッチからなる第2のデマルチプレクサと、
前記複数本の映像信号線への前記第2の映像信号の印加を可能とするか否かを切り替える動作制御部と
を備え、
前記第1のデマルチプレクサに含まれる前記n個の第1スイッチの状態は、互いに異なるn個の制御信号によって制御され、
前記第2のデマルチプレクサに含まれる前記n個の第2スイッチの状態は、互いに異なる前記n個の制御信号によって制御され、
前記n個の制御信号のうちの任意の制御信号を着目制御信号としたとき、各映像信号線群について、前記着目制御信号によってオン状態にされる第1スイッチに接続された映像信号線と前記着目制御信号によってオン状態にされる第2スイッチに接続された映像信号線とは異なることを特徴とする、表示パネル。 - 前記動作制御部は、前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのそれぞれに対応して設けられるn個の制御スイッチからなり、
各制御スイッチは、外部から与えられる切替制御信号に基づいて、前記第2スイッチに前記制御信号を与えるか否かを制御することを特徴とする、請求項1に記載の表示パネル。 - 前記動作制御部は、前記第2のデマルチプレクサの出力部と前記表示部との間に前記複数本の映像信号線のそれぞれに対応して設けられる複数個の制御スイッチからなり、
各制御スイッチは、外部から与えられる切替制御信号に基づいて、前記第2のデマルチプレクサの出力部から前記複数本の映像信号線への前記第2の映像信号の印加を可能とするか否かを切り替えることを特徴とする、請求項1に記載の表示パネル。 - 前記動作制御部は、前記第2のデマルチプレクサの入力部近傍に前記複数本の映像信号線のそれぞれに対応して設けられる複数個の制御スイッチからなり、
各制御スイッチは、外部から与えられる切替制御信号に基づいて、前記第2の映像信号を前記第2のデマルチプレクサの入力部に与えるか否かを切り替えることを特徴とする、請求項1に記載の表示パネル。 - 前記第2の映像信号は、前記複数本の映像信号線の他端側に設けられている全ての第2のデマルチプレクサの入力部に共通的に与えられていることを特徴とする、請求項1に記載の表示パネル。
- 前記第1のデマルチプレクサに含まれる前記n個の第1スイッチおよび前記第2のデマルチプレクサに含まれる前記n個の第2スイッチは、薄膜トランジスタであることを特徴とする、請求項1に記載の表示パネル。
- 請求項1に記載の表示パネルを備えた表示モジュールであって、
前記第1のデマルチプレクサに前記第1の映像信号を与える映像信号線駆動回路が前記表示パネルに実装されていることを特徴とする、表示モジュール。 - n本毎(nは2以上の自然数)に1組の映像信号線群を構成する複数本の映像信号線が配設された表示部と、前記複数本の映像信号線の一端側に前記1組の映像信号線群毎に設けられ、外部から送られる第1の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第1スイッチからなる第1のデマルチプレクサと、前記複数本の映像信号線の他端側に前記1組の映像信号線群毎に設けられ、外部から送られる第2の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第2スイッチからなる第2のデマルチプレクサと、前記複数本の映像信号線への前記第2の映像信号の印加を可能とするか否かを切り替える動作制御部と、外部から送られるn個の制御信号を受け取るための制御信号入力部とを備えた表示パネルの検査方法であって、
前記動作制御部が前記複数本の映像信号線への前記第2の映像信号の印加を可能とする検査準備ステップと、
前記第2の映像信号の信号レベルが所定の第1レベルになっているときに、各映像信号線群に対応して設けられている前記第1のデマルチプレクサに含まれる前記n個の第1スイッチのうちの1つおよび各映像信号線群に対応して設けられている前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのうちの1つが所定期間オン状態で維持されるように前記n個の制御信号のうちの1つの信号レベルを変化させる第1レベル印加ステップと、
前記第2の映像信号の信号レベルが前記第1レベルとは異なる第2レベルになっているときに、各映像信号線群に対応して設けられている前記第1のデマルチプレクサに含まれる前記n個の第1スイッチのうちの1つおよび各映像信号線群に対応して設けられている前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのうちの1つが所定期間オン状態で維持されるように前記n個の制御信号のうちの1つの信号レベルを変化させる第2レベル印加ステップと
を含み、
前記n個の制御信号のうちの任意の制御信号を着目制御信号としたとき、各映像信号線群について、前記着目制御信号によってオン状態にされる第1スイッチに接続された映像信号線と前記着目制御信号によってオン状態にされる第2スイッチに接続された映像信号線とは異なり、
検査対象の表示色に対応する映像信号線には前記第1レベルの前記第2の映像信号が印加されるよう前記第1レベル印加ステップが行われ、
検査対象以外の表示色に対応する映像信号線には前記第2レベルの前記第2の映像信号が印加されるよう前記第2レベル印加ステップが行われることを特徴とする、検査方法。 - n本毎(nは2以上の自然数)に1組の映像信号線群を構成する複数本の映像信号線が配設された表示部と、前記複数本の映像信号線の一端側に前記1組の映像信号線群毎に設けられ、外部から送られる第1の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第1スイッチからなる第1のデマルチプレクサと、前記複数本の映像信号線の他端側に前記1組の映像信号線群毎に設けられ、外部から送られる第2の映像信号を前記映像信号線群に含まれるn本の映像信号線のそれぞれに印加するか否かを切り替えるためのn個の第2スイッチからなる第2のデマルチプレクサと、前記複数本の映像信号線への前記第2の映像信号の印加を可能とするか否かを切り替える動作制御部と、外部から送られるn個の制御信号を受け取るための制御信号入力部とを備えた表示パネルの検査方法であって、
前記動作制御部が前記複数本の映像信号線への前記第2の映像信号の印加を可能とする検査準備ステップと、
前記第2の映像信号の信号レベルが所定の第1レベルになっているときに、各映像信号線群に対応して設けられている前記第1のデマルチプレクサに含まれる前記n個の第1スイッチのうちのm個(mはn未満の自然数)および各映像信号線群に対応して設けられている前記第2のデマルチプレクサに含まれる前記n個の第2スイッチのうちのm個が所定期間オン状態で維持されるように前記n個の制御信号のうちのm個の信号レベルを変化させるmライン書き込みステップと
を含み、
前記n個の制御信号のうちの任意の制御信号を着目制御信号としたとき、各映像信号線群について、前記着目制御信号によってオン状態にされる第1スイッチに接続された映像信号線と前記着目制御信号によってオン状態にされる第2スイッチに接続された映像信号線とは異なることを特徴とする、検査方法。
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WO2014133176A1 (en) * | 2013-02-27 | 2014-09-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, driver circuit, and display device |
US9337343B2 (en) | 2013-02-27 | 2016-05-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, driver circuit, and display device |
US9553205B2 (en) | 2013-02-27 | 2017-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, driver circuit, and display device |
TWI611567B (zh) * | 2013-02-27 | 2018-01-11 | 半導體能源研究所股份有限公司 | 半導體裝置、驅動電路及顯示裝置 |
US10304555B2 (en) | 2013-02-27 | 2019-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, driver circuit, and display device |
Also Published As
Publication number | Publication date |
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CN102687188B (zh) | 2015-01-14 |
JP5349620B2 (ja) | 2013-11-20 |
US20120249499A1 (en) | 2012-10-04 |
EP2528051A1 (en) | 2012-11-28 |
JPWO2011089762A1 (ja) | 2013-05-20 |
EP2528051A4 (en) | 2013-05-22 |
CN102687188A (zh) | 2012-09-19 |
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