Classifications

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  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/568—Temporary substrate used as encapsulation process aid
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  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/495—Lead-frames or other flat leads
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  • H01L23/495—Lead-frames or other flat leads
  • H01L23/49541—Geometry of the lead-frame
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  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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  • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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  • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
  • H01L21/4814—Conductive parts
  • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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  • H01L2924/01043—Technetium [Tc]
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  • H01L2924/01—Chemical elements
  • H01L2924/01047—Silver [Ag]
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  • H01L2924/01082—Lead [Pb]
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  • H01L2924/013—Alloys
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  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
  • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
  • H01L2924/15747—Copper [Cu] as principal constituent
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  • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
  • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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  • H01L2924/181—Encapsulation
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  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19041—Component type being a capacitor

Definitions

• the present invention relates to a method for packaging semiconductor dies on a panel using a lead frame.
• the present invention also relates to a device made by such method and in particular wherein the device is capable of package-on-package stacking.
• FIG. 1 A cross-sectional view of a packaged semiconductor die using a lead frame.
• a plan view of a lead frame 20 of the prior art is shown in Figure 20.
• the packaged die 10 comprises a lead frame 20 having a central recessed portion 14 and a plurality of spaced apart leads 12.
• An integrated circuit die 22 has a top surface 24 and a bottom surface 26, with the top surface 24 having a plurality of bonding pads which electrically connect to the various circuit elements in the integrated circuit die 24.
• the die 22 is positioned in the recessed portion 14, such that the bottom surface 26 of the die 22 rests on the recessed portion 14, through a conductive paste and is electrically connected to the recessed portion 14.
• the recessed portion 14 is formed of a conductive material.
• a plurality of bonding wires 30 connect certain of the bonding pads on the top surface of the die 22 to the top side of certain of the leads 12.
• Each of the leads 12 has a bottom side 32, opposite to the top side, which are will be connected to various electrical pads on a printed circuit board (PCB) for system application.
• the recessed portion 14 is also connected to an electrical contact, typically ground, on the printed circuit board on the same side as the bottom side 32 of the leads 12.
• the die 22 is first placed on the recessed portion 14 of a preformed lead frame 20.
• the die 22 may be attached to the recessed portion 14 by adhesive to prevent movement of the die 22 in the subsequent steps.
• a wire bonding machine bonds certain of the bonding pads of the die 22 to the top side of certain of the leads 12.
• resin is injected into a mold chest to encapsulate and insulate the die 22, the wires 30 and the top sides of the leads 12.
• the structure is then singulated or cut and each packaged die can then be used to connect to other packaged semiconductor devices, by well known techniques, such as by soldering the packaged die 10 on a printed circuit board PCB.
• the packaged semiconductor die of the prior art as shown in Figure 1 has electrical connections to only one side of the packaged die for connection to a printed circuit board.
• FIG. 2a there is shown the first step in another method of forming a packaged semiconductor die 40 of another prior art, which is very similar to the method shown and described in Figure 1.
• the method begins with a slab of copper alloy 42, having a top side and a bottom side.
• Photoresist 44 is applied to both the top side and the bottom side, and a masking step is formed on both sides.
• a solderable material 46 such as tin is sputtered to fill the removed portions.
• the resultant structure is shown in Figure 2b.
• the photoresist 44 is then removed, leaving the solderable material 46 on the copper alloy 42.
• the resultant structure is shown in Figure 2c.
• a wet etch of the copper is performed on the top side of the copper alloy 42. The etch forms a recessed central portion 50.
• the resultant structure is shown in Figure 2d.
• a die 22 is placed in the recessed cavity 50 with the bonding pads of the die 22 facing outwardly. Wires are then bonded to the bonding pads of the die 22 and to the solderable posts 46 on the top side. An insulator encapsulation material is then applied to the top side of the die 22 and the etched copper alloy at the bottom side. The resultant structure is then singulated or cut and the result is shown in Figure 2f.
• a method of packaging an integrated circuit die comprises placing a plurality of integrated circuit dies on a first substrate having a planar surface, with each of the plurality of dies having a top surface and a bottom surface.
• the top surface has a plurality of bonding pads for electrical connection to the die.
• the plurality of dies are positioned with the top surface in contact with the planar surface of the first substrate.
• a conductive adhesive is applied to the bottom surface of each of the dies.
• a plurality of preformed lead frames are placed on the plurality of dies with each lead frame having a central recessed portion, and a plurality of conductive leads.
• Each lead has a top side and a bottom side, with the central recessed portion connected to the plurality of leads by a connection for electrical conductivity.
• the central recessed portion has a top portion and a bottom portion with the bottom portion substantially co-planar with the bottom side of the plurality of leads.
• the central recessed portion of the lead frame is placed on the conductive adhesive back side of the plurality of dies with the top portion of the recessed portion in contact with the conductive adhesive until the top side of each lead is in contact with the planar surface of the first substrate.
• the first substrate is then removed.
• the plurality of lead frames are placed with the plurality of dies on a second substrate having a planar surface, with the bottom side of each lead and the bottom portion of the recessed portion on the planar surface of the second substrate.
• a conductive layer is deposited on the top surface of the die and the top side of the leads and is patterned to form electrical connection between certain of the bonding pads of one of the plurality of dies to certain of the conductive leads associated with the one die.
• the connection of each lead frame is cut from its adjacent lead frames and the leads from said recessed portion. The bottom sides of the leads and central recessed portion are exposed to form package terminals.
• a packaged die made by the foregoing described method is also disclosed. BRIEF DESCRIPTION OF THE DRAWINGS
• Figure 1 is a cross-sectional view of a packaged die with a lead frame packaged with the method of the prior art
• Figure 2(a-f) are cross-sectional views of another method of the prior art.
• Figure 3 is a cross-sectional view of the first step in the method of the present invention.
• Figure 4 is a cross-sectional view of the next step in the method of the present invention.
• Figure 5 is a cross sectional view of the next step in the method of the present invention.
• Figure 6 is a cross sectional view of the next step in the method of the present invention.
• Figures 7 is a cross sectional view of the next step in the method of the present invention.
• Figure 8 is a cross-sectional view of the next step in the method of the present invention.
• Figure 9 is a cross-sectional view of the next step in the method of the present invention.
• Figure 10 is a cross-sectional view of the next step in the method of the present invention.
• Figure 1 1 is a cross-sectional view of the next step in the method of the present invention.
• Figure 12 is a cross-sectional view of the next step in the method of the present invention.
• Figure 13 is a cross-sectional view of the next step in the method of the present invention.
• Figure 14 is a cross-sectional view of the next step in the method of the present invention.
• Figure 15 is a cross-sectional view of the next step in the method of the present invention.
• Figure 16 is a cross-sectional view of the next step in the method of the present invention.
• Figure 17 is a cross-sectionai view of the next step in the method of the present invention.
• Figure 18 is a cross-sectional view of one method of stacking the packaged dies of the present invention.
• Figure 19 is a cross-sectional view of another method of stacking the packaged dies of the present invention.
• Figure 20 is a top view of a preformed lead frame of the prior art.
• Figure 21 is a top view of a preformed lead frame of the present invention for use in the method of the present invention.
• Figure 22 is a top view of a die packaged with a preformed lead frame of the present invention using the method of the present invention, in which an inductor is incorporated into the package.
• FIG. 3 there is shown a cross-sectional view of a first step in the method of the present invention.
• the method begins with a first substrate 60.
• the first substrate 60 can be glass or any material that has rigid characteristics.
• the first substrate 60 has a top surface 62 and a bottom surface 64, opposite thereto.
• the top surface 62 is marked with a plurality of marks 66.
• the marks 66 correspond to locations where an integrated circuit die 70 whose bonding pads 72 will be placed.
• the resultant structure is shown in Figure 3.
• a layer of PET 68 ts applied to the top surface 62 of the first substrate 60.
• the material PET 68 can be a double sided adhesive film. Thus the PET layer 68 attaches to the first substrate 60.
• a printed glue layer 69 such as Q2-7406 from Dow Corning corporation is then applied to the PET layer 68.
• the glue layer 69 adheres to the PET layer 68.
• it will permit the die 70 (discussed in the next step) to adhere to the PET layer 68.
• the use of the PET layer 68 as well as the glue layer 69 is to ensure that a strong adhesive layer attaches the die 70 to attach to the PET layer 68 to prevent any void between the surface of the die 70 and the PET layer 68.
• the use of the PET layer 68, with its low adhesi ve property is so that that the PET layer 68 can be readily removed from the first substrate 60, in subsequent processing.
• the resultant structure is shown in Figure 4.
• a plurality of integrated circuit dies 70 are then placed on the layer 69.
• Each of the integrated circuit dies 70 has bonding pads 72, and each die 70 is placed with its bonding pads 72 aligned with the marks 66. This is done by conventional well known die placement tools.
• Each of the dies 70 has a front surface 74 and a back surface 76. The bonding pads 72 are located on the front surface 74.
• a conductive silver paste 78 is applied to the back surface 76 of each of the dies 70.
• the resultant structure is shown in Figure 6.
• a preformed lead frame 80 is then applied to the structure shown in Figure 6.
• the preformed lead frame 80 which will be discussed in greater detail, has a central recessed portion 14 and a plurality of spaced apart leads 12.
• Each of the spaced apart leads 12 has bottom side 82 and a top side 84.
• Each of the recessed cavity 14 has a top portion and a bottom portion with the bottom portion of the recessed cavity 14 substantially co-planar with the bottom side 82 of the leads 12.
• the lead frame 80 is applied such that the dies 70 each with its conductive silver paste 78 are placed in the recessed cavities 14 of the lead frame 80, contacting the top portion of the recessed cavity 14.
• the lead frame 80 is then "pressed” downward, i.e. the lead frame 80 is pressed against the conductive silver paste 78 until the top side 84 of the leads 12 press against the layer 69.
• the resultant structure is shown in Figure 7.
• An insulator 90 is applied onto the structure shown in Figure 7.
• Examples of insulators 90 that can be used include X-35, TC-27 or EF-342X or other epoxies and compounds. All of these materials have the property that they generally have a high thermal conductivity property and flow relatively easily, such that they can be applied as in a liquid or paste form.
• the insulator 90 can be applied by any means including printing or spreading on the structure formed after Figure 7.
• the insulator 90 is applied everywhere such that it even enters into the recessed portion 14, between the die 70 and the adjacent leads 12.
• the resultant structure is shown in Figure 8.
• the first glass substrate 60 is then removed. Since the PET layer 68 is only lightly adhered to the first glass substrate 60, the first glass substrate 60 can simply be "peeled off'. The resultant structure is shown in Figure 9.
• the layers 68 and 69 are then removed by conventional means. Finally, the surface of the lead frame 80 which contains the bottom side 82 of the leads 12 is planarized to remove the excess insulator 90.
• the excess insulator 90 is removed by a planarization process, such as by any grinding process, including the use of sand paper (or any other abrasive material) against the surface of the lead frame 80 until the bottom side 82 of the leads 12 is exposed.
• a planarization process such as by any grinding process, including the use of sand paper (or any other abrasive material) against the surface of the lead frame 80 until the bottom side 82 of the leads 12 is exposed.
• the structure is then mounted or placed on a second substrate 92, such as glass, with the surface of the lead frame 80 which contains the bottom side 82 of the leads 12 on the substrate 92.
• the structure can be placed on the second substrate 92 with a layer of adhesive, such as Q2- 7406 from Dow Corning corporation.
• the second substrate 92 provides only rigid mechanical support for the subsequent processing.
• the resultant structure is shown in Figure 1 1.
• the layer 94 is similar to a photoresist, and is applied on the surface that contains the top side 84 of the leads 12, as well as the bonding pads 72.
• the layer 94 is patterned to expose desired connections between certain of the bonding pads 72 to certain of the top sides 84 of certain of the leads 12. The resultant structure is shown in Figure 12.
• a conductive layer 96 is then deposited on the photoresist layer 94. Where the photoresist pattern is exposed, the conductive layer 94 forms an electrical connection between certain of the bonding pads 72 to certain of the top sides 84 of certain of the leads 12. In the process of form ing the electrical connection between certain of the bonding pads 72 to certain of the top sides 84 of certain of the leads 12, the conductive layer 94 can be patterned to form an inductor 200. This is shown in Figure 22.
• one of the significant benefits of the method and package of the present invention is that as a part of the packaging of the integrated circuit die 70, a passive circuit element such as an inductor 200 (or a resistor) can be formed and packaged along with the die 70 in the same package in which capacitors can be integrated.
• a passive circuit element such as an inductor 200 (or a resistor) can be formed and packaged along with the die 70 in the same package in which capacitors can be integrated.
• the resultant structure is shown in Figure 1 .
• a second insulator 98 is then applied to the structure formed in Figure 13, and in particular to cover the conductive layer 96.
• the resultant structure is shown in Figure 14.
• the second insulator 98 can be another layer of SiNR which is a photosensitive dielectric material. After the layer 98 is deposited, openings can be formed in the layer 98 to expose portions of the conductive layer 94.
• UBM Under Bump Metallization
• the UBM 100 forms a reaction barrier layer for the solder balls 102 that are formed in the subsequent step to connect electrically to the exposed portion of the conductive layer 94.
• Solder balls 102 are then placed into the same openings of the second insulator 98 on the layer of UBM 100.
• the balls 102 can be positioned by a conventional placement tool or printing method. The resultant structure is shown in Figure 15.
• FIG. 16 The structure of Figure 16 is then immersed in a tin plating solution.
• the tin will adhere only to the exposed copper lead frame and will not adhere to the insulator 90.
• tin will adhere to the bottom side 82 of each lead 12, and to the bottom portion of the recessed cavity 14.
• the resultant structure is shown in Figure 17.
• a packaged integrated circuit die with integrated passive elements such as resistors and inductors and capacitors can be directly packaged with the die.
• a P-O-P (Package-On-Package) device can be achieved. Referring to Figure 18, there is shown a first embodiment of a P-O-P embodiment using the device of the present invention.
• a first packaged integrated circuit die 150a has a first surface 152a which has solderable balls 154a with the solderable balls 154a electrically connected to the bonding pads 72a.
• the second surface 160a opposite to the first surface 152a has conductive contacts to the bottom side 82a of the leads 12a.
• a second packaged integrated circuit die 150b has a first surface 1 52b which has solderable balls 154b with the solderable balls 154b electrically connected to the bonding pads 72b.
• the second surface 160b, opposite to the first surface 152b has conductive contacts to the bottom side 82b of the leads 12b.
• the first and second packages 150a and 150b are positioned such that the surfaces 152a and 152b face one another with the solderable balls 154a and 154b in contact with one another. In this manner the two packages 150a and 150b can be soldered to one another and still provide electrical contacts through the bottom of the leads 82a and 82b.
• a first packaged integrated circuit die 150a has a first surface 152a which has solderable balls 154a with the solderable balls 154a electrically connected to the bonding pads 72a.
• the second surface 160a opposite to the first surface 152a has conducti ve contacts to the bottom side 82a of the leads 12a.
• a second packaged integrated circuit die 150b has a first surface 1 2b which has solderable balls 154b with the solderable balls 154b electrically connected to the bonding pads 72b.
• the second surface 160b, opposite to the first surface 152b has conductive contacts to the bottom side 82b of the leads 12b.
• the first and second packages 150a and 150b are positioned such that the surfaces 152a and 160b face one another with the solderable balls 154a in contact with the bottom sides 82b of the package 150b. In this manner the two packages 150a and 150b can be soldered to one another and still provide electrical contacts through the bottom of the leads 82a and through the solderable balls 154b.
• FIG. 21 there is shown a top view of a lead frame 80 of the present invention for use in the method and device of the present invention.
• the lead frame 80 when used in the method of the present invention comprises a recessed portion 14.
• the recessed portion 14 is connected to the rest of the lead frame 80 by a connection member 120.
• the lead frame 80 also comprises a plurality of leads 12 (a-f) and another lead 12g, which is electrically connected to the recessed portion 14. Although only 6 leads 12 are shown, it will be appreciated that the present invention may use a lead frame 80 with any number of leads 12.
• the lead frame 80 is singulated, i.e.
• the method of the present invention provides for a compact means to package integrated circuit dies, and a compact integrated circuit die is made thereby.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Geometry (AREA)
• Lead Frames For Integrated Circuits (AREA)
• Wire Bonding (AREA)

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