WO2011055755A1 - Dispositif de mémoire non volatile à semi-conducteurs et procédé d'écriture dans celui-ci - Google Patents

Dispositif de mémoire non volatile à semi-conducteurs et procédé d'écriture dans celui-ci Download PDF

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Publication number
WO2011055755A1
WO2011055755A1 PCT/JP2010/069622 JP2010069622W WO2011055755A1 WO 2011055755 A1 WO2011055755 A1 WO 2011055755A1 JP 2010069622 W JP2010069622 W JP 2010069622W WO 2011055755 A1 WO2011055755 A1 WO 2011055755A1
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well
voltage
memory device
semiconductor memory
nonvolatile semiconductor
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PCT/JP2010/069622
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English (en)
Japanese (ja)
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高 三井田
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Miida Takashi
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Definitions

  • the present invention relates to a writing method in a nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device, and is particularly useful when applied to a NAND flash memory device.
  • a NAND flash memory device in which a memory cell has a floating gate as a nonvolatile semiconductor memory device, and a plurality of memory cells are arranged in series in a NAND bundle in which adjacent source / drain regions are connected in series It has been known.
  • writing and reading operations are simultaneously performed on all memory cells connected to one control gate line (word line).
  • This write / read unit is hereinafter referred to as a page.
  • the erase operation is performed for all NAND bundles selected by one row decoder. This erase unit is hereinafter referred to as a block.
  • the self-boost writing method is generally employed (for example, see Non-Patent Document 1).
  • VCC is applied to the gate of the select gate transistor on the drain side for selecting the NAND bundle
  • VPASS intermediate potential
  • 0V is applied to the gate of the select gate transistor to turn it off
  • a high voltage VPGM for writing of about 20V is applied to the control gate of the selected memory cell.
  • VPASS voltage
  • VPASS voltage is applied to these non-selected word lines
  • VPASS disturb erroneous writing
  • VPASS intermediate potential
  • the present invention provides a writing method in a non-volatile semiconductor memory device and a non-volatile semiconductor memory device capable of significantly increasing the number of additional writes (NOP) by suppressing write disturb. For the purpose.
  • the first aspect of the present invention for achieving the above object is as follows: A P well made of a P type semiconductor is formed in an N well made of an N type semiconductor, and a plurality of electrically rewritable nonvolatile memory cells are connected in series on the surface of the P well.
  • a writing method in a nonvolatile semiconductor memory device including a memory cell array in which NAND bundles are arranged in a matrix A first voltage is applied to the word lines of all the memory cells of the NAND bundle in a period before a write operation (period t3 ⁇ t4) by applying a program voltage in a write period (period t0 ⁇ t4) to the memory cell.
  • a second voltage higher than the first voltage is applied to the P well, and a voltage that reversely biases the bit line and the source line with respect to the P well is applied.
  • a reverse bias voltage is applied between the P well and the N well so that the N well is reverse biased with respect to the P well.
  • the second aspect of the present invention is: A writing method in the nonvolatile semiconductor memory device according to the first aspect, In the writing method in the nonvolatile semiconductor memory device, the reverse bias voltage is applied in a period before the writing operation.
  • the third aspect of the present invention is: A writing method in the nonvolatile semiconductor memory device according to the first aspect, In the writing method in the nonvolatile semiconductor memory device, the reverse bias voltage is applied during the writing operation.
  • the fourth aspect of the present invention is: A writing method in the nonvolatile semiconductor memory device according to the first aspect, In the writing method in the nonvolatile semiconductor memory device, the reverse bias voltage is applied in a period before the writing operation and a period of the writing operation.
  • a writing method in the nonvolatile semiconductor memory device is characterized in that the first voltage is a ground potential and the second voltage is a positive potential.
  • the sixth aspect of the present invention is: A writing method in the nonvolatile semiconductor memory device according to the second or fourth aspect, The writing method in the nonvolatile semiconductor memory device is characterized in that the first voltage is a ground potential and the second voltage is a positive potential.
  • the seventh aspect of the present invention is A writing method in the nonvolatile semiconductor memory device according to the sixth aspect, Due to capacitive coupling between the P well and the N well by applying a reverse bias voltage between the N well and the P well in a period before the write operation and then bringing the N well into a floating state.
  • the voltage generated in this manner is the reverse bias voltage.
  • the eighth aspect of the present invention is A writing method in a nonvolatile semiconductor memory device according to any one of the first to fourth aspects,
  • the writing method in the nonvolatile semiconductor memory device is characterized in that the first voltage is a negative potential and the second voltage is a ground potential.
  • the ninth aspect of the present invention provides A P well made of a P type semiconductor is formed in an N well made of an N type semiconductor, and a plurality of electrically rewritable nonvolatile memory cells are connected in series on the surface of the P well.
  • a nonvolatile semiconductor memory device comprising a memory cell array in which NAND bundles are arranged in a matrix, A word line voltage generating circuit for applying a first voltage to the word lines of the memory cell array via a word line driving circuit; A P well voltage generation circuit for applying a second voltage higher than the first voltage to the P well via a P well bias circuit; An N-well voltage generating circuit for applying a reverse bias voltage to the N-well via an N-well bias circuit so that the N-well is reverse-biased with respect to the P-well; A first voltage is applied to the word lines of all the memory cells of the NAND bundle through the word line voltage generation circuit and the word line driving circuit during a period before a write operation by applying a program voltage in the write period to the memory cell
  • a second voltage higher than the first voltage is applied to the P well, and a voltage at which the bit line and the source line are reverse-biased with respect to the P well is applied.
  • a write control circuit for controlling to apply the reverse bias voltage to the N well via the N well voltage generation circuit and the N well bias circuit.
  • the tenth aspect of the present invention provides In the nonvolatile semiconductor memory device according to the ninth aspect, In the nonvolatile semiconductor memory device, the write control circuit controls the reverse bias voltage to be applied during a period before the write operation.
  • the eleventh aspect of the present invention is In the nonvolatile semiconductor memory device according to the ninth aspect, In the nonvolatile semiconductor memory device, the write control circuit controls the reverse bias voltage to be applied during the write operation.
  • the twelfth aspect of the present invention provides In the nonvolatile semiconductor memory device according to the ninth aspect, In the nonvolatile semiconductor memory device, the write control circuit controls the reverse bias voltage to be applied in a period before the write operation and a period of the write operation.
  • the thirteenth aspect of the present invention provides In the nonvolatile semiconductor memory device according to the ninth or eleventh aspect, In the nonvolatile semiconductor memory device, the word line voltage generation circuit has the first voltage as a ground potential, and the P well voltage generation circuit has the second voltage as a positive potential. .
  • the fourteenth aspect of the present invention provides In the nonvolatile semiconductor memory device according to the tenth or twelfth aspect, In the nonvolatile semiconductor memory device, the word line voltage generation circuit has the first voltage as a ground potential, and the P well voltage generation circuit has the second voltage as a positive potential. .
  • the fifteenth aspect of the present invention provides In the nonvolatile semiconductor memory device according to the fourteenth aspect,
  • the write control circuit applies a reverse bias voltage between the N well and the P well in a period before the write operation, and then sets the N well to be in a floating state so that the P well and the N well
  • a nonvolatile semiconductor memory device is characterized in that a voltage generated due to capacitive coupling is controlled to be the reverse bias voltage.
  • the sixteenth aspect of the present invention provides in the nonvolatile semiconductor memory device according to any one of the ninth to twelfth aspects,
  • the word line voltage generation circuit has the first voltage as a negative potential
  • the P well voltage generation circuit has the second voltage as a ground potential.
  • the first voltage is applied to the word line of the memory cell and the second voltage higher than the first voltage is applied to the P well in the period before the write operation, and the bit line And a source line is applied with a voltage that is reverse-biased with respect to the P-well, and the N-well in which the P-well memory cell is formed so that the N-well is reverse-biased with respect to the P-well during the writing period Since a period in which a reverse bias voltage is applied between the P well and the P well is provided, it is possible to completely prevent residual electrons from remaining or flowing into the P well of the non-selected memory cell.
  • write disturb program disturb
  • NOP number of additional writes
  • FIG. 1 is a cross-sectional view showing a string structure of stacked gates of a NAND flash memory constituting a nonvolatile semiconductor memory device according to an embodiment of the present invention.
  • FIG. 2 is a configuration diagram illustrating a part of a memory cell array extracted from the NAND flash memory illustrated in FIG. 1.
  • 1 is a block diagram showing an entire NAND flash memory device which is a nonvolatile semiconductor memory device according to an embodiment of the present invention.
  • 3 is a timing chart according to the first embodiment showing, in time series, voltages applied to each part of the NAND flash memory.
  • FIG. 5 is a schematic diagram showing an electron state in a memory cell of an unselected bit line when a voltage shown in a period from t1 to t2 in FIG. 4 is applied.
  • FIG. 5 is a schematic diagram showing an electron state in a memory cell of an unselected bit line when a voltage shown in a period from t2 to t3 in FIG. 4 is applied.
  • FIG. 5 is a schematic diagram showing an electron state in a memory cell of an unselected bit line when a voltage shown in a period from t3 to t4 in FIG. 4 is applied.
  • It is a timing chart concerning the 2nd example which shows the voltage impressed to each part of NAND type flash memory in time series.
  • It is a timing chart concerning the 3rd example which shows the voltage impressed to each part of NAND type flash memory in time series.
  • 9A and 9B are diagrams demonstrating the effect of suppressing erroneous writing in the write operation according to the third embodiment shown in FIG. 9, in which FIG.
  • FIG. 9A is a characteristic diagram showing characteristics of threshold change with respect to VPASS
  • FIG. 9B is a normal distribution with respect to threshold voltage. It is a characteristic view which shows a cumulative frequency. It is a timing chart concerning the 4th example which shows the voltage impressed to each part of NAND type flash memory in time series. It is a timing chart concerning the 5th example which shows the voltage impressed to each part of NAND type flash memory in time series. It is a timing chart which concerns on the 6th Example which shows the voltage applied to each part of NAND type flash memory in time series. It is a timing chart which concerns on the 7th Example which shows the voltage applied to each part of NAND type flash memory in a time series.
  • FIG. 1 is a cross-sectional view showing a string structure of a stacked gate of a NAND flash memory constituting a nonvolatile semiconductor memory device according to an embodiment of the present invention.
  • the NAND flash memory I includes an N well 2 made of an N type semiconductor in a P type semiconductor substrate 1 and a P type semiconductor in the N well 2.
  • P well 3 is formed.
  • a plurality of memory cells 4 formed of electrically rewritable N-type non-volatile transistors are connected in series to form a NAND bundle 5.
  • the NAND bundle 5 is disposed between the drain side select gate 6 and the source side select gate 7.
  • the select gate 6 extends in the left-right direction in the figure and is connected to the bit line 8 connected to another NAND bundle adjacent in the same direction, and the select gate 7 is orthogonal to the bit line 8.
  • the source side of the source line 9 is connected to a source line 9 that is connected to another NAND bundle adjacent in the same direction.
  • Such a configuration itself is basically the same as a conventional NAND flash memory. That is, in such a NAND flash memory I, the memory cell 4 has a stacked gate type structure composed of a stacked structure of a floating gate and a control gate, and a tunnel oxide film between the surface of the semiconductor substrate and the floating gate is formed.
  • the threshold value of the memory cell is changed by injecting or emitting electrons to and from the floating gate, and stored data is written, read, and erased.
  • an operation of injecting electrons into the floating gate is referred to as a write operation, and a state where normal electrons are injected is referred to as a “0” state, and a state where electrons are emitted is referred to as a “1” state. Therefore, each memory cell 4 is in the “1” state in the erased state.
  • the well electrodes 10 and 11 are formed so that independent voltages can be applied to the N well 2 and the P well 3, respectively.
  • FIG. 2 is a configuration diagram showing a part of the memory cell array (two NAND bundles 5) extracted from the NAND flash memory I shown in FIG. 1, and the bit line selected to perform writing in the writing period.
  • the positional relationship between the VPASS disturb and the program disturb generation cells in the (NAND bundle) and the non-selected bit line (NAND bundle) is shown. That is, in the selected bit line 8A (NAND bundle 5A), adjacent memory cells 4B (rectangular) on both sides in the same NAND bundle 5A as the memory cell 4A selected for writing (the cell surrounded by an ellipse with a dotted line).
  • Program disturb may occur at 4C (cell surrounded by a rectangular solid line).
  • bit line 8A selected for writing in the writing period is grounded, and a predetermined voltage (for example, power supply voltage VCC) for prohibiting writing is applied to the non-selected bit line 8B.
  • a writing operation injection of electrons into the floating gate
  • VPROG program voltage
  • VPASS pass voltage
  • writing in this embodiment is performed by a so-called self-boosting writing method, but the time series relationship of voltages applied to each part of the NAND flash memory I will be described in detail later.
  • the non-selected bit line 8B, the select gate 7 and the source line 9 are basically held at a predetermined fixed potential (for example, a ground potential).
  • a predetermined fixed potential for example, a ground potential.
  • the bit line 8B and the source line 9 may be in a floating state for a specific period. This point will be described in detail later.
  • FIG. 3 is a block diagram showing an entire NAND flash memory device which is a nonvolatile semiconductor memory device according to an embodiment of the present invention.
  • the NAND flash memory device according to this embodiment has a feature in the write mode, and the read and erase operations are executed in the same manner as in the prior art. Therefore, the following description will mainly describe the write operation.
  • the NAND flash memory I has an N well 2 and a P well 3 formed in the N well 2, and a memory cell 4 on the surface of the P well 3 (see FIGS. 1 and 2). ) Are arranged in a matrix form.
  • predetermined predetermined processing in each operation of writing, reading and erasing is executed by control via the writing control circuit 22, the reading control circuit 23 and the erasing control circuit 24.
  • the control at this time is executed with the word line voltage generating circuit 25, the word line driving circuit 26, the N well voltage generating circuit 27, the N well bias circuit 28, the P well voltage generating circuit 29, and the P well bias circuit 30 being controlled. .
  • command data input via the interface circuit 31 is decoded by the command decoder 32 to generate command data related to writing, reading and erasing, and the write control circuit 22, the read control circuit 23 and the erase control circuit 24. It is configured to supply to either.
  • the read operation is performed simultaneously for all the memory cells 4 (see FIG. 1 and FIG. 2) connected to any one of the word lines WL0 to WLn + 3 at the same time as in the prior art.
  • the erase operation is performed on a block basis for all NAND bundles (see FIGS. 1 and 2) selected by one row decoder (not shown).
  • the word line voltage generation circuit 25 applies the first voltage to the word lines of the memory cell array 21 via the word line drive circuit 26.
  • the P well voltage generation circuit 29 applies a second voltage higher than the first voltage to the P well 3 through the P well bias circuit 30.
  • the N well voltage generation circuit 27 applies a reverse bias voltage to the N well 2 via the N well bias circuit 28 so that the N well 2 is reverse biased with respect to the P well 3.
  • the second voltage and the reverse bias voltage are applied to the P well 3 and the N well 2 via the well electrodes 11 and 10 shown in FIG.
  • the “writing period” used in this specification is a period from time t1 to time t4 in the timing chart shown in FIG. 4 and the like, and the “writing operation” is an application period of a program voltage (VPROG). It means the period from time t3 to time t4.
  • VPROG program voltage
  • the waveforms of the timing charts shown in each figure are, in order from the top, (a) gate voltage VG applied to the word line WLn (see FIG. 2) to which the memory cell 4A to be written (see FIG. 2) is connected, (B) Gate voltage VG applied to word lines WL0 to WLn + 3 (see FIG. 2) other than word line WLn, (c) Voltage SGD applied to drain side select gate 6 (see FIG. 2), (d) P well 3 (see FIGS. 1 to 3), and (e) a voltage CNW applied to the N well 2 (see FIGS. 1 to 3).
  • These voltages VPROG and the like are generated by the word line voltage generation circuit 25, the P well voltage generation circuit 29, and the N well voltage generation circuit 27 under the control of the write control circuit 22 shown in FIG. 26, and applied to predetermined word lines WL0 to WLn + 3, P well 3 and N well 2 through the P well bias circuit 30 and the N well bias circuit 28, respectively.
  • FIG. 4 is a timing chart according to the first embodiment. Each time-series operation will be described with reference to FIG. 1) Assuming that the floating gates of the memory cells 4 are in an erased state at the time of writing, the floating gates of the memory cells 4 have positive charges and the transistors constituting the memory cells 4 even if the word lines WL0 to WLn + 3 are grounded May be considered to be in an ON state, and in an equilibrium state, an inversion layer of electrons is always formed in the channel of the NAND bundle 5.
  • SGD is raised to 5V at t-1, and then is lowered to 1.5V at t0.
  • a predetermined voltage for example, power supply voltage VCC
  • VCC power supply voltage
  • this period is a preprocessing period preceding the writing period, and is not necessarily a necessary process. 2) During the period from t0 to t1 in the writing period, the state when the SGD falls is maintained. 3) During the period from t1 to t2, all the word lines WL0 to WLn + 3 are set to the ground voltage (first voltage), and a positive voltage higher than the ground voltage is applied to the P well 3 (in this example, 4 V (second voltage) )) Is applied.
  • a predetermined positive voltage (6 V (reverse bias voltage) in this example) is applied to the N well 2 so that a reverse bias is applied to the P well 3.
  • the non-selected bit line 8B and the source line 9 are precharged to the P well potential or higher, and then set in a floating state at the time of reverse bias. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.
  • the electrons accumulated on the surfaces of the memory cells 4 and 4C related to the non-selected bit line 8B so far are separated and moved in the direction of the semiconductor substrate 1. Further, since holes are induced near the surface, the electrons in the neutral region in the N-type diffusion layer forming the drain and source are also reduced by recombination with the holes. Thus, the surface of the memory cells 4 and 4C has a sufficient hole accumulation state, and the repelled electrons leave the channel surface and float in the P well.
  • VPASS for example, 6 V
  • the electrons existing in the P well 3 and the N type diffusion layer remain in the N well 2 without being absorbed. Things are neutralized by the accumulation of holes. As a result, it is possible to further assist the reduction of free electrons in the channel under the gate.
  • the voltage applied to the P well 3 at t2 is stepped down to the ground voltage, and the voltage applied to the N well 2 is stepped down to 2V, but the reverse bias voltage (2V in this example) continues between them. Is applied. 5)
  • VPROG (20 + V in this example) is applied to the word line WLn to which the gate of the memory cell 4A to be written is connected, and other word lines WN0 to WLn + 3 Is continuously applied with VPASS (6 V in this example).
  • a reverse bias voltage (2 V in this example) is continuously applied between the N well 2 and the P well 3.
  • the surface potential of the memory cell 4C increases greatly, but the depletion layer of the P well 3 is also significantly deeper. spread.
  • a reverse bias voltage (2 V in this example) is applied between the N well 2 and the P well 3 even during a program operation by applying VPROG.
  • VPROG a reverse bias voltage
  • FIG. 8 is a timing chart according to the second embodiment.
  • the voltage is different.
  • Others are the same as those of the first embodiment (see FIG. 4). That is, in the period from t1 to t2, the ground voltage (second voltage) is higher than the negative voltage in the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to a negative voltage (-4V (first voltage) in this example). Voltage).
  • a predetermined positive voltage in this example, 2 V (reverse bias voltage)
  • 2 V reverse bias voltage
  • the electrons accumulated on the surfaces of the memory cells 4 and 4C related to the non-selected bit line 8B so far move away in the direction of the semiconductor substrate 1. Be made. Further, since holes are induced in the vicinity of the surface, the neutral region in the N-type diffusion layer forming the drain and source is also regressed to reduce electrons. Thus, the surface of the memory cells 4 and 4C is in a sufficient hole accumulation state.
  • the depletion layer spreads at the junction of the reverse-biased N-well 2 and P-well 3, so that free electrons are swept out by the electric field at this time. . That is, electrons are absorbed from the P-well 3 to the end of the depletion layer of the P-well 3 as a minority carrier diffusion current. Thus, excess electrons can be removed.
  • a reverse bias voltage (2 V in this example) is applied between the N well 2 and the P well 3 even during the period of t3 ⁇ t4 (write operation) in this embodiment.
  • FIG. 9 is a timing chart according to the third embodiment. As shown in the figure, in this embodiment, the application of the reverse bias voltage from t3 to t4 in the first embodiment (see FIG. 4) is omitted. Others are the same as the first embodiment.
  • FIG. 10 is a diagram demonstrating the effect of suppressing erroneous writing in the write operation according to the present embodiment.
  • I is the characteristic of the present embodiment
  • II is the characteristic of the patent document (when a voltage higher than the applied voltage of the word line is applied to the well at t1 ⁇ t2)
  • III is the conventional technique (well at t1 ⁇ t2). In the case of the same voltage as that of the word line).
  • FIG. 10 (a) shows the dependence of the VPASS voltage applied to the non-selected cell on the threshold fluctuation due to the disturb of the selected cell whose write is prohibited.
  • the reverse bias voltage is applied at t1 ⁇ t2 and t3 ⁇ t4, the removal of electrons is promoted, and the case of this embodiment in which inflow prevention is taken is more prominent than the case of Patent Document 1. It can be seen that the program disturb in the low pressure range can be suppressed.
  • FIG. 10 (b) shows the result of 500 additional writes of the cell threshold cumulative distribution in the non-selected cells.
  • the characteristic I of the present embodiment shows the distribution in the initial state.
  • the threshold value fluctuates about 10 times, and the distribution greatly collapses at 500 times, which shows that severe program disturb occurs.
  • the characteristic I of the present embodiment in which a reverse bias voltage is also applied, has a distribution that overlaps the initial value even when 500 additional programs are given, no change in threshold is observed, and no program disturb occurs. It is shown that.
  • FIG. 11 is a timing chart according to the fourth embodiment.
  • the application of the reverse bias voltage from t1 to t2 in the first embodiment is omitted.
  • Others are the same as the first embodiment. That is, during the period from t1 to t2, a positive voltage (4 V (second voltage in this example) is applied to the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to the ground voltage (first voltage). )) Is applied.
  • the non-selected bit line 8B and the source line 9 are set in a floating state. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.
  • the neutral region in the N-type diffusion layer forming the drain and source is also reduced.
  • the surface of the memory cells 4 and 4C is in a sufficient hole accumulation state. That is, in this embodiment, the N well 2 and the P well 3 are not reverse-biased, but a certain excess electron removing function is exhibited.
  • a reverse bias voltage (4 V in this example) is applied between the N well 2 and the P well 3 during the period from t3 to t4 (write operation).
  • FIG. 12 is a timing chart according to the fifth embodiment.
  • the application of the reverse bias voltage from t3 to t4 in the second embodiment is omitted.
  • the rest is the same as in the second embodiment. That is, in the period from t1 to t2, the ground voltage (second voltage) is higher than the negative voltage in the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to a negative voltage (-4V (first voltage) in this example). Voltage).
  • a predetermined positive voltage (2 V (reverse bias voltage) in this example) is applied to the N well 2 so that the bias between the P well 3 and the P well 3 is reversed.
  • FIG. 13 is a timing chart according to the sixth embodiment. As shown in the figure, in this embodiment, the application of the reverse bias voltage from t1 to t2 in the second embodiment (see FIG. 8) is omitted. The rest is the same as in the second embodiment. That is, in the period from t1 to t2, the ground voltage (second voltage) is higher than the negative voltage in the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to a negative voltage (-4V (first voltage) in this example). Voltage).
  • a reverse bias voltage (2 V in this example) is applied between the N well 2 and the P well 3 in the period of t3 ⁇ t4 (write operation).
  • the thermal potential is lowered so that no reverse flow due to the diffusion current of electrons to the P-well 3 occurs. can do. This can prevent injection of electrons into the P-well 3 and contribute to prevention of erroneous writing (program disturb).
  • FIG. 14 is a timing chart according to the seventh embodiment.
  • a voltage in the same manner as in the first embodiment (see FIG. 4) is applied.
  • the reverse bias voltage from t1 to t2 is formed by bringing the N-well 2 into a floating state. More specifically, the P-well 3 is grounded (0 V) from t0 to t1, and at the same time, a reverse bias voltage (2 V in this example) is applied to the N-well 2 and between the P-well 3 and the N-well 2 The charge is precharged in the depletion layer capacitor formed in the first step.
  • the application of the reverse bias voltage (2 V) is stopped at t1, and immediately thereafter, a positive bias is applied to the P well.
  • the application of the P well bias boosts the N well through the coupling of the depletion layer capacitance, and this is superimposed on the P well bias application voltage when the application of the reverse bias voltage is stopped.
  • the N well 2 is maintained at a floating voltage higher than the precharge voltage during the period from t1 to t2.
  • the floating voltage is set to be higher than the second voltage (4 V in this example) applied to the P-well 3 from t1 to t2, and as a result, the N-well 2 and P are changed from t1 to t2.
  • a reverse bias voltage is applied to the well.
  • the element configuration of the N-well voltage generation circuit and the N-well bias circuit can be simplified, and the same operations and effects as those of the first embodiment (see FIG. 4) are exhibited. Similarly to the example, erroneous writing can be effectively prevented.
  • the non-selected bit line 8B and the source line 9 are in a floating state. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.
  • FIG. 15 is a timing chart according to the eighth embodiment. As shown in the figure, in this embodiment, in the seventh embodiment (see FIG. 14), the application of the reverse bias voltage from t3 to t4 is omitted. Therefore, the same operation and effect as in the third embodiment (see FIG. 9) can be achieved to prevent erroneous writing.
  • the non-selected bit line 8B and the source line 9 are in a floating state. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.
  • FIG. 16 is a timing chart according to the ninth embodiment. As shown in the figure, before t3 ⁇ t4 (write operation) in this embodiment, the P well 3 and the N well 2 are set to the same ground voltage as all the word lines WL0 to WLn + 3, and only the t3 ⁇ t4 has the N well 2 A reverse bias voltage is applied between the P well 3 and the P well 3.
  • the present invention can be effectively used in the industrial field of manufacturing and selling semiconductor memories.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé d'écriture dans un dispositif de mémoire non volatile à semi-conducteurs, sur la surface d'un puits de type P, ledit puits de type P étant constitué de semi-conducteurs de type P dans un puits de type N constitué de semi-conducteurs de type N, lequel dispositif de mémoire non volatile à semi-conducteurs, comporte un réseau de cellules de mémoire constitué d'un agencement sous forme de matrice d'un ensemble de NON-ET qui connecte en série une pluralité de cellules de mémoire non volatile électriquement réinscriptible. Une première tension est appliquée sur les lignes de mot de toutes les cellules de mémoire dudit ensemble NON-ET dans une période précédant une opération d'écriture (période t3→t4) par application d'une tension de programme dans une période d'écriture (période t0→t4) dans lesdites cellules de mémoire; et au même moment une seconde tension (CPW) plus élevée que ladite première tension est appliquée dans ledit puits de type P. En outre, une tension de polarité inverse (CNW) est appliquée entre ledit puits de type P et ledit puits de type N, de manière à polariser ledit puits de type N à l'inverse dudit puits de type P pendant ladite période d'écriture.
PCT/JP2010/069622 2009-11-04 2010-11-04 Dispositif de mémoire non volatile à semi-conducteurs et procédé d'écriture dans celui-ci WO2011055755A1 (fr)

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JP2009253487A JP4511627B1 (ja) 2009-11-04 2009-11-04 不揮発性半導体記憶装置における書き込み方法及び不揮発性半導体記憶装置
JP2009-253487 2009-11-04

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KR102127105B1 (ko) 2013-11-11 2020-06-29 삼성전자 주식회사 비휘발성 메모리 장치의 구동 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279566A (ja) * 1995-04-06 1996-10-22 Hitachi Ltd 並列型不揮発性半導体記憶装置及び同装置の使用方法
JP2001230391A (ja) * 2000-02-17 2001-08-24 Toshiba Corp 不揮発性半導体記憶装置及びその書き込み方法
JP2002245785A (ja) * 2000-12-28 2002-08-30 Samsung Electronics Co Ltd 不揮発性半導体メモリ装置のプログラム方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279566A (ja) * 1995-04-06 1996-10-22 Hitachi Ltd 並列型不揮発性半導体記憶装置及び同装置の使用方法
JP2001230391A (ja) * 2000-02-17 2001-08-24 Toshiba Corp 不揮発性半導体記憶装置及びその書き込み方法
JP2002245785A (ja) * 2000-12-28 2002-08-30 Samsung Electronics Co Ltd 不揮発性半導体メモリ装置のプログラム方法

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