WO2011055755A1

WO2011055755A1 - Method for writing in non-volatile semiconductor memory device and non-volatile semiconductor memory device

Info

Publication number: WO2011055755A1
Application number: PCT/JP2010/069622
Authority: WO
Inventors: 高三井田
Original assignee: Miida Takashi
Priority date: 2009-11-04
Filing date: 2010-11-04
Publication date: 2011-05-12
Also published as: JP2011100507A; JP4511627B1

Abstract

Disclosed is a method for writing in a non-volatile semiconductor memory device which has a P well made from a P-type semiconductor formed in an N well made from an N-type semiconductor, and which is provided with a memory cell array formed by arranging in matrix form on the surface of the P well NAND bundles wherein a plurality of electrically rewritable non-volatile memory cells are connected in series. A first voltage is applied to the word lines of all of the memory cells in the NAND bundles in a period prior to the writing operation (period t3 → t4) performed by applying program voltage in the writing period (period t0 → t4) with respect to the memory cells, and a second voltage (CPW) that is higher than the first voltage is applied to the P well. Further, a reverse bias voltage (CNW) is applied between the P well and the N well in such a way that the N well is reverse-biased with respect to the P well in the writing period.

Description

WRITE METHOD IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

The present invention relates to a writing method in a nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device, and is particularly useful when applied to a NAND flash memory device.

A NAND flash memory device in which a memory cell has a floating gate as a nonvolatile semiconductor memory device, and a plurality of memory cells are arranged in series in a NAND bundle in which adjacent source / drain regions are connected in series It has been known.

In the NAND flash memory device according to the prior art, writing and reading operations are simultaneously performed on all memory cells connected to one control gate line (word line). This write / read unit is hereinafter referred to as a page. The erase operation is performed for all NAND bundles selected by one row decoder. This erase unit is hereinafter referred to as a block.

In the writing to the NAND flash memory according to the prior art, the self-boost writing method is generally employed (for example, see Non-Patent Document 1). In this writing method, VCC is applied to the gate of the select gate transistor on the drain side for selecting the NAND bundle, and an intermediate potential (VPASS) of about 10 V is applied to the control gate of the non-selected memory cell in the NAND bundle, and the source side of the NAND bundle is selected. 0V is applied to the gate of the select gate transistor to turn it off, and a high voltage VPGM for writing of about 20V is applied to the control gate of the selected memory cell.

Here, when “0” data is written, 0V (ground potential) of the bit line is transmitted to the channel portion of the selected memory cell via the drain-side select gate transistor and the channel portion of the non-selected memory cell. Since the electron inversion layer is formed, a tunneling current flows through the tunnel oxide film due to a high electric field applied to the tunnel oxide film, and electrons are injected into the floating gate. For this reason, the threshold value of the memory cell changes to the positive side.

On the other hand, in the case of not writing data which is a write-inhibit mode and “1” data write mode, by initially charging the channel portion of the memory cell from the bit line, by turning off the select gate transistor on the drain side, By blocking the supply of electrons to the channel and raising the potential of the channel part by coupling the control gate of the non-selected memory cell and the channel part, the tunnel current is blocked and the negative threshold of the memory cell is maintained (erase) Maintain state). However, the remaining surplus electrons exist in the channel region under the memory cell where writing is not performed. As a result, electric field stress is applied to the tunnel oxide film, and so-called program disturb occurs in which erroneous writing due to unnecessary tunnel current occurs in a memory cell that is not originally written.

Therefore, it is desirable to apply as high a voltage (VPASS) as possible to these unselected word line bundles in order not to change the threshold value of the erased memory cell in the positive direction during non-writing (to prevent program disturb). .

However, the higher the voltage is applied to these non-selected word lines (VPASS), the more the oxide film electric field becomes stronger for the non-selected memory cells connected to the bit line for writing “0” data. There is a problem that erroneous writing (VPASS disturb) is likely to occur.

For this reason, conventionally, it is applied to the gate line of the non-selected memory cell so that the erroneous writing resistance of the selected memory cell at the time of non-writing and the erroneous writing resistance of the non-selected memory cell at the time of writing “0” data are approximately the same. An intermediate potential (VPASS) is set.

However, the conventional NAND-type non-volatile semiconductor memory device has a problem in that, when rewriting in units of pages due to this limitation, erroneous writing (program disturb) easily occurs in the selected memory cell at the time of non-writing. Therefore, the number of additional writings on the page is strictly limited (Number of Programming: NOP = 1).

As a method of preventing such erroneous writing (program disturb), a method of biasing a P well in which a memory cell is formed to a positive potential or biasing a word line to a negative potential before performing a write operation to the memory cell. (See Patent Document 1) has been proposed. More specifically, all word lines are temporarily grounded for a certain period before the write operation, and the P-type well is biased to a positive potential, or the P-type well is grounded and a negative bias voltage is applied to all the word lines for a certain period. Is.

JP 2001-230391 A

However, as described in Patent Document 1, only by applying a bias voltage before the write operation, the channel surface potential of the selected memory cell in which the write is prohibited as described above is lowered and the electric field stress is caused in the tunnel oxide film. The excess electrons in the P-well are insufficiently removed, and the depletion layer in the P-type well extends deeply when a high program voltage is applied, for example, to cope with multilevel (MLC) operation. Since the electrons reach the well junction and flow electrons into the depletion layer, the write disturb cannot be completely prevented.

In view of the above-described problems of the prior art, the present invention provides a writing method in a non-volatile semiconductor memory device and a non-volatile semiconductor memory device capable of significantly increasing the number of additional writes (NOP) by suppressing write disturb. For the purpose.

The first aspect of the present invention for achieving the above object is as follows:
A P well made of a P type semiconductor is formed in an N well made of an N type semiconductor, and a plurality of electrically rewritable nonvolatile memory cells are connected in series on the surface of the P well. A writing method in a nonvolatile semiconductor memory device including a memory cell array in which NAND bundles are arranged in a matrix,
A first voltage is applied to the word lines of all the memory cells of the NAND bundle in a period before a write operation (period t3 → t4) by applying a program voltage in a write period (period t0 → t4) to the memory cell. In addition, a second voltage higher than the first voltage is applied to the P well, and a voltage that reversely biases the bit line and the source line with respect to the P well is applied. In the writing method in the nonvolatile semiconductor memory device, a reverse bias voltage is applied between the P well and the N well so that the N well is reverse biased with respect to the P well.

The second aspect of the present invention is:
A writing method in the nonvolatile semiconductor memory device according to the first aspect,
In the writing method in the nonvolatile semiconductor memory device, the reverse bias voltage is applied in a period before the writing operation.

The third aspect of the present invention is:
A writing method in the nonvolatile semiconductor memory device according to the first aspect,
In the writing method in the nonvolatile semiconductor memory device, the reverse bias voltage is applied during the writing operation.

The fourth aspect of the present invention is:
A writing method in the nonvolatile semiconductor memory device according to the first aspect,
In the writing method in the nonvolatile semiconductor memory device, the reverse bias voltage is applied in a period before the writing operation and a period of the writing operation.

According to a fifth aspect of the present invention,
A writing method in the nonvolatile semiconductor memory device according to the first or third aspect,
The writing method in the nonvolatile semiconductor memory device is characterized in that the first voltage is a ground potential and the second voltage is a positive potential.

The sixth aspect of the present invention is:
A writing method in the nonvolatile semiconductor memory device according to the second or fourth aspect,
The writing method in the nonvolatile semiconductor memory device is characterized in that the first voltage is a ground potential and the second voltage is a positive potential.

The seventh aspect of the present invention is
A writing method in the nonvolatile semiconductor memory device according to the sixth aspect,
Due to capacitive coupling between the P well and the N well by applying a reverse bias voltage between the N well and the P well in a period before the write operation and then bringing the N well into a floating state. The voltage generated in this manner is the reverse bias voltage.

The eighth aspect of the present invention is
A writing method in a nonvolatile semiconductor memory device according to any one of the first to fourth aspects,
The writing method in the nonvolatile semiconductor memory device is characterized in that the first voltage is a negative potential and the second voltage is a ground potential.

The ninth aspect of the present invention provides
A P well made of a P type semiconductor is formed in an N well made of an N type semiconductor, and a plurality of electrically rewritable nonvolatile memory cells are connected in series on the surface of the P well. A nonvolatile semiconductor memory device comprising a memory cell array in which NAND bundles are arranged in a matrix,
A word line voltage generating circuit for applying a first voltage to the word lines of the memory cell array via a word line driving circuit;
A P well voltage generation circuit for applying a second voltage higher than the first voltage to the P well via a P well bias circuit;
An N-well voltage generating circuit for applying a reverse bias voltage to the N-well via an N-well bias circuit so that the N-well is reverse-biased with respect to the P-well;
A first voltage is applied to the word lines of all the memory cells of the NAND bundle through the word line voltage generation circuit and the word line driving circuit during a period before a write operation by applying a program voltage in the write period to the memory cell. In addition, a second voltage higher than the first voltage is applied to the P well, and a voltage at which the bit line and the source line are reverse-biased with respect to the P well is applied. And a write control circuit for controlling to apply the reverse bias voltage to the N well via the N well voltage generation circuit and the N well bias circuit.

The tenth aspect of the present invention provides
In the nonvolatile semiconductor memory device according to the ninth aspect,
In the nonvolatile semiconductor memory device, the write control circuit controls the reverse bias voltage to be applied during a period before the write operation.

The eleventh aspect of the present invention is
In the nonvolatile semiconductor memory device according to the ninth aspect,
In the nonvolatile semiconductor memory device, the write control circuit controls the reverse bias voltage to be applied during the write operation.

The twelfth aspect of the present invention provides
In the nonvolatile semiconductor memory device according to the ninth aspect,
In the nonvolatile semiconductor memory device, the write control circuit controls the reverse bias voltage to be applied in a period before the write operation and a period of the write operation.

The thirteenth aspect of the present invention provides
In the nonvolatile semiconductor memory device according to the ninth or eleventh aspect,
In the nonvolatile semiconductor memory device, the word line voltage generation circuit has the first voltage as a ground potential, and the P well voltage generation circuit has the second voltage as a positive potential. .

The fourteenth aspect of the present invention provides
In the nonvolatile semiconductor memory device according to the tenth or twelfth aspect,
In the nonvolatile semiconductor memory device, the word line voltage generation circuit has the first voltage as a ground potential, and the P well voltage generation circuit has the second voltage as a positive potential. .

The fifteenth aspect of the present invention provides
In the nonvolatile semiconductor memory device according to the fourteenth aspect,
The write control circuit applies a reverse bias voltage between the N well and the P well in a period before the write operation, and then sets the N well to be in a floating state so that the P well and the N well A nonvolatile semiconductor memory device is characterized in that a voltage generated due to capacitive coupling is controlled to be the reverse bias voltage.

The sixteenth aspect of the present invention provides
In the nonvolatile semiconductor memory device according to any one of the ninth to twelfth aspects,
In the nonvolatile semiconductor memory device, the word line voltage generation circuit has the first voltage as a negative potential, and the P well voltage generation circuit has the second voltage as a ground potential. .

According to the present invention, the first voltage is applied to the word line of the memory cell and the second voltage higher than the first voltage is applied to the P well in the period before the write operation, and the bit line And a source line is applied with a voltage that is reverse-biased with respect to the P-well, and the N-well in which the P-well memory cell is formed so that the N-well is reverse-biased with respect to the P-well during the writing period Since a period in which a reverse bias voltage is applied between the P well and the P well is provided, it is possible to completely prevent residual electrons from remaining or flowing into the P well of the non-selected memory cell.

As a result, write disturb (program disturb) can be suppressed, and the number of additional writes (NOP) can be significantly increased.

1 is a cross-sectional view showing a string structure of stacked gates of a NAND flash memory constituting a nonvolatile semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a configuration diagram illustrating a part of a memory cell array extracted from the NAND flash memory illustrated in FIG. 1. 1 is a block diagram showing an entire NAND flash memory device which is a nonvolatile semiconductor memory device according to an embodiment of the present invention. 3 is a timing chart according to the first embodiment showing, in time series, voltages applied to each part of the NAND flash memory. FIG. 5 is a schematic diagram showing an electron state in a memory cell of an unselected bit line when a voltage shown in a period from t1 to t2 in FIG. 4 is applied. FIG. 5 is a schematic diagram showing an electron state in a memory cell of an unselected bit line when a voltage shown in a period from t2 to t3 in FIG. 4 is applied. FIG. 5 is a schematic diagram showing an electron state in a memory cell of an unselected bit line when a voltage shown in a period from t3 to t4 in FIG. 4 is applied. It is a timing chart concerning the 2nd example which shows the voltage impressed to each part of NAND type flash memory in time series. It is a timing chart concerning the 3rd example which shows the voltage impressed to each part of NAND type flash memory in time series. 9A and 9B are diagrams demonstrating the effect of suppressing erroneous writing in the write operation according to the third embodiment shown in FIG. 9, in which FIG. 9A is a characteristic diagram showing characteristics of threshold change with respect to VPASS, and FIG. 9B is a normal distribution with respect to threshold voltage. It is a characteristic view which shows a cumulative frequency. It is a timing chart concerning the 4th example which shows the voltage impressed to each part of NAND type flash memory in time series. It is a timing chart concerning the 5th example which shows the voltage impressed to each part of NAND type flash memory in time series. It is a timing chart which concerns on the 6th Example which shows the voltage applied to each part of NAND type flash memory in time series. It is a timing chart which concerns on the 7th Example which shows the voltage applied to each part of NAND type flash memory in a time series. It is a timing chart which concerns on the 8th Example which shows the voltage applied to each part of NAND type flash memory in a time series. It is a timing chart which concerns on the 9th Example which shows the voltage applied to each part of NAND type flash memory in a time series.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a cross-sectional view showing a string structure of a stacked gate of a NAND flash memory constituting a nonvolatile semiconductor memory device according to an embodiment of the present invention. As shown in the figure, the NAND flash memory I includes an N well 2 made of an N type semiconductor in a P type semiconductor substrate 1 and a P type semiconductor in the N well 2. P well 3 is formed. On the surface of the P well 3, a plurality of memory cells 4 formed of electrically rewritable N-type non-volatile transistors are connected in series to form a NAND bundle 5. The NAND bundle 5 is disposed between the drain side select gate 6 and the source side select gate 7. The select gate 6 extends in the left-right direction in the figure and is connected to the bit line 8 connected to another NAND bundle adjacent in the same direction, and the select gate 7 is orthogonal to the bit line 8. The source side of the source line 9 is connected to a source line 9 that is connected to another NAND bundle adjacent in the same direction. Thus, although not clearly shown in FIG. 1, a memory cell array in which the memory cells 4 are arranged in a matrix is formed.

Such a configuration itself is basically the same as a conventional NAND flash memory. That is, in such a NAND flash memory I, the memory cell 4 has a stacked gate type structure composed of a stacked structure of a floating gate and a control gate, and a tunnel oxide film between the surface of the semiconductor substrate and the floating gate is formed. The threshold value of the memory cell is changed by injecting or emitting electrons to and from the floating gate, and stored data is written, read, and erased. Here, an operation of injecting electrons into the floating gate is referred to as a write operation, and a state where normal electrons are injected is referred to as a “0” state, and a state where electrons are emitted is referred to as a “1” state. Therefore, each memory cell 4 is in the “1” state in the erased state.

On the other hand, in the NAND flash memory I according to the present embodiment, the

well electrodes

10 and 11 are formed so that independent voltages can be applied to the N well 2 and the P well 3, respectively.

FIG. 2 is a configuration diagram showing a part of the memory cell array (two NAND bundles 5) extracted from the NAND flash memory I shown in FIG. 1, and the bit line selected to perform writing in the writing period. The positional relationship between the VPASS disturb and the program disturb generation cells in the (NAND bundle) and the non-selected bit line (NAND bundle) is shown. That is, in the selected bit line 8A (NAND bundle 5A), adjacent memory cells 4B (rectangular) on both sides in the same NAND bundle 5A as the memory cell 4A selected for writing (the cell surrounded by an ellipse with a dotted line). Memory cell in which a VPASS disturbance occurs in the non-selected bit line 8B and a gate is connected to the same word line WLn as the memory cell 4A in the memory cell 4 (cell of the NAND bundle 5B) in the unselected bit line 8B. Program disturb may occur at 4C (cell surrounded by a rectangular solid line).

Here, the bit line 8A selected for writing in the writing period is grounded, and a predetermined voltage (for example, power supply voltage VCC) for prohibiting writing is applied to the non-selected bit line 8B. Further, a writing operation (injection of electrons into the floating gate) in this writing period is performed by applying a program voltage (VPROG) which is a predetermined high voltage (for example, 20 V). That is, VPROG is applied to the word line WLn to which the gate of the memory cell 4A is connected. At this time, a pass voltage (VPASS) lower than VPROG is applied to the other word lines WL0 to WLn + 3.

As described above, writing in this embodiment is performed by a so-called self-boosting writing method, but the time series relationship of voltages applied to each part of the NAND flash memory I will be described in detail later.

In the writing period, the non-selected bit line 8B, the select gate 7 and the source line 9 are basically held at a predetermined fixed potential (for example, a ground potential). However, the bit line 8B and the source line 9 may be in a floating state for a specific period. This point will be described in detail later.

FIG. 3 is a block diagram showing an entire NAND flash memory device which is a nonvolatile semiconductor memory device according to an embodiment of the present invention. In the figure, only a portion for applying a predetermined voltage to the word lines WL0 to WLn + 3, the N well 2 and the P well 3 is shown, but other portions are the same as those of the NAND flash memory device according to the prior art. It is. That is, the NAND flash memory device according to this embodiment has a feature in the write mode, and the read and erase operations are executed in the same manner as in the prior art. Therefore, the following description will mainly describe the write operation.

As shown in FIG. 3, the NAND flash memory I has an N well 2 and a P well 3 formed in the N well 2, and a memory cell 4 on the surface of the P well 3 (see FIGS. 1 and 2). ) Are arranged in a matrix form. For the NAND flash memory I, predetermined predetermined processing in each operation of writing, reading and erasing is executed by control via the writing control circuit 22, the reading control circuit 23 and the erasing control circuit 24. The control at this time is executed with the word line voltage generating circuit 25, the word line driving circuit 26, the N well voltage generating circuit 27, the N well bias circuit 28, the P well voltage generating circuit 29, and the P well bias circuit 30 being controlled. .

For this reason, command data input via the interface circuit 31 is decoded by the command decoder 32 to generate command data related to writing, reading and erasing, and the write control circuit 22, the read control circuit 23 and the erase control circuit 24. It is configured to supply to either.

Here, the read operation is performed simultaneously for all the memory cells 4 (see FIG. 1 and FIG. 2) connected to any one of the word lines WL0 to WLn + 3 at the same time as in the prior art. In addition, the erase operation is performed on a block basis for all NAND bundles (see FIGS. 1 and 2) selected by one row decoder (not shown).

On the other hand, in the write mode in this embodiment, the word line voltage generation circuit 25, the word line drive circuit 26, the N well voltage generation circuit 27, the N well bias circuit 28, the P well voltage generation circuit 29 and the P well bias circuit 30 are used. The following control is performed. That is, the word line voltage generation circuit 25 applies the first voltage to the word lines of the memory cell array 21 via the word line drive circuit 26. The P well voltage generation circuit 29 applies a second voltage higher than the first voltage to the P well 3 through the P well bias circuit 30. The N well voltage generation circuit 27 applies a reverse bias voltage to the N well 2 via the N well bias circuit 28 so that the N well 2 is reverse biased with respect to the P well 3. Here, the second voltage and the reverse bias voltage are applied to the P well 3 and the N well 2 via the

well electrodes

11 and 10 shown in FIG.

Although not shown in FIG. 3, application of a predetermined voltage to the

select gates

6 and 7 and the source line 9 (see FIGS. 1 and 2) is also performed through the word line driving circuit 26.

In this embodiment, the write operation to the NAND flash memory I will be described in more detail for each embodiment based on the timing chart of the voltage applied to each part.

Note that the “writing period” used in this specification is a period from time t1 to time t4 in the timing chart shown in FIG. 4 and the like, and the “writing operation” is an application period of a program voltage (VPROG). It means the period from time t3 to time t4.

The waveforms of the timing charts shown in each figure are, in order from the top, (a) gate voltage VG applied to the word line WLn (see FIG. 2) to which the memory cell 4A to be written (see FIG. 2) is connected, (B) Gate voltage VG applied to word lines WL0 to WLn + 3 (see FIG. 2) other than word line WLn, (c) Voltage SGD applied to drain side select gate 6 (see FIG. 2), (d) P well 3 (see FIGS. 1 to 3), and (e) a voltage CNW applied to the N well 2 (see FIGS. 1 to 3). These voltages VPROG and the like are generated by the word line voltage generation circuit 25, the P well voltage generation circuit 29, and the N well voltage generation circuit 27 under the control of the write control circuit 22 shown in FIG. 26, and applied to predetermined word lines WL0 to WLn + 3, P well 3 and N well 2 through the P well bias circuit 30 and the N well bias circuit 28, respectively.

<First embodiment>
FIG. 4 is a timing chart according to the first embodiment. Each time-series operation will be described with reference to FIG.
1) Assuming that the floating gates of the memory cells 4 are in an erased state at the time of writing, the floating gates of the memory cells 4 have positive charges and the transistors constituting the memory cells 4 even if the word lines WL0 to WLn + 3 are grounded May be considered to be in an ON state, and in an equilibrium state, an inversion layer of electrons is always formed in the channel of the NAND bundle 5.

Therefore, as shown in the period from t-1 to t0, in the cell string of the non-selected bit line 8B, SGD is raised to 5V at t-1, and then is lowered to 1.5V at t0. After a predetermined voltage (for example, power supply voltage VCC) is applied to the cell string via the selected bit line 8B, the transistor constituting the select gate 6 is cut off to cut off the supply of electrons.

As a result, the channel of the memory cell 4 of the unselected bit line 8B rises to the potential of the bit line 8B, and surplus electrons in the channel can be suppressed. However, it cannot be completely removed from within the channel. Note that this period is a preprocessing period preceding the writing period, and is not necessarily a necessary process.
2) During the period from t0 to t1 in the writing period, the state when the SGD falls is maintained.
3) During the period from t1 to t2, all the word lines WL0 to WLn + 3 are set to the ground voltage (first voltage), and a positive voltage higher than the ground voltage is applied to the P well 3 (in this example, 4 V (second voltage) )) Is applied. Further, in the present embodiment, a predetermined positive voltage (6 V (reverse bias voltage) in this example) is applied to the N well 2 so that a reverse bias is applied to the P well 3. At this time, the non-selected bit line 8B and the source line 9 are precharged to the P well potential or higher, and then set in a floating state at the time of reverse bias. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.

As a result, as shown in FIG. 5, the electrons accumulated on the surfaces of the

memory cells

4 and 4C related to the non-selected bit line 8B so far are separated and moved in the direction of the semiconductor substrate 1. Further, since holes are induced near the surface, the electrons in the neutral region in the N-type diffusion layer forming the drain and source are also reduced by recombination with the holes. Thus, the surface of the

memory cells

4 and 4C has a sufficient hole accumulation state, and the repelled electrons leave the channel surface and float in the P well.

In this embodiment, since the depletion layer spreads at the junction between the N-well 2 and the P-well 3 that are further reverse-biased, the electrons in the P-well are swept out to the N-well by the electric field at this time. That is, electrons are absorbed from the P-well 3 to the end of the depletion layer of the P-well 3 as a minority carrier diffusion current. Thus, excess electrons can be removed.
4) In the period from t2 to t3, VPASS (for example, 6 V) is applied to all the word lines WL0 to WLn + 3. As a result, as shown in FIG. 6, in the

memory cells

4 and 4C related to the non-selected bit line 8B, the electrons existing in the P well 3 and the N type diffusion layer remain in the N well 2 without being absorbed. Things are neutralized by the accumulation of holes. As a result, it is possible to further assist the reduction of free electrons in the channel under the gate.

In this embodiment, the voltage applied to the P well 3 at t2 is stepped down to the ground voltage, and the voltage applied to the N well 2 is stepped down to 2V, but the reverse bias voltage (2V in this example) continues between them. Is applied.
5) During the period from t3 to t4 (write operation), VPROG (20 + V in this example) is applied to the word line WLn to which the gate of the memory cell 4A to be written is connected, and other word lines WN0 to WLn + 3 Is continuously applied with VPASS (6 V in this example). A reverse bias voltage (2 V in this example) is continuously applied between the N well 2 and the P well 3.

In this period, as shown in FIG. 7, electrons in the channel of the memory cell 4 related to the non-selected bit line 8B are largely removed. This is because the electrons in the channel are largely removed in the period up to t3 prior to the period from t3 to t4.

As a result, generally, when a high voltage VPROG is applied to the word line WLn, the potential of the channel portion of the memory cell 4C connected to the word line WLn becomes intensively deep and remains in other memory cell regions. The collected electrons gather in the channel portion of 4C, but these surplus electrons are greatly reduced by the discharge operation in the period preceding this, so that the potential drop on the surface of the memory cell 4C is smaller than in the conventional method, It still holds a high potential. Thus, the voltage drop in the tunnel oxide film of the memory cell 4C can be reduced and the electric field can be relaxed, so that the tunnel current can be prevented from flowing. That is, erroneous writing (program disturb) to the memory cell 4C can be prevented.

However, the higher the voltage VPROG is, the deeper the depletion layer of the P well 3 is. In particular, when electrons are significantly removed during a period prior to the program operation (particularly t1 → t2) as in this embodiment, the surface potential of the memory cell 4C increases greatly, but the depletion layer of the P well 3 is also significantly deeper. spread.

As a result, in any case, when the depletion layer extends to the vicinity of the N well 2, the thermal potential of the PN junction with the P well 3 is lowered, and electrons are injected from the N region into the P region. Accelerated in the direction of the interface within the layer. Thus, there is a possibility that electrons having a high energy state will overcome the energy barrier of the oxide film and be injected into the floating gate. That is, there is a high possibility of erroneous writing (program disturb).

Therefore, in this embodiment, a reverse bias voltage (2 V in this example) is applied between the N well 2 and the P well 3 even during a program operation by applying VPROG. Thus, by reverse-biasing the N-well 2 with respect to the P-well 3, even if the depletion layer of the P-well 3 reaches the vicinity of the junction, the thermal potential is lowered, and no reverse flow due to the diffusion current of electrons to the P-well 3 occurs. Can be. Thus, as shown in FIG. 7, in the memory cell 4C, injection of electrons into the P well 3 is prevented, thereby preventing erroneous writing (program disturb) more reliably.

<Second embodiment>
FIG. 8 is a timing chart according to the second embodiment. As shown in the figure, in this embodiment, the first voltage applied to all the word lines WL0 to WLn + 3, the second voltage applied to the P well 3, and the reverse bias applied between the N well 2 and the P well 3. The voltage is different. Others are the same as those of the first embodiment (see FIG. 4). That is, in the period from t1 to t2, the ground voltage (second voltage) is higher than the negative voltage in the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to a negative voltage (-4V (first voltage) in this example). Voltage). Further, in this embodiment, a predetermined positive voltage (in this example, 2 V (reverse bias voltage)) is applied to the N well 2 so that the gap with the P well 3 is reversely biased.

As a result, as in “3)” of the first embodiment, the electrons accumulated on the surfaces of the

memory cells

4 and 4C related to the non-selected bit line 8B so far move away in the direction of the semiconductor substrate 1. Be made. Further, since holes are induced in the vicinity of the surface, the neutral region in the N-type diffusion layer forming the drain and source is also regressed to reduce electrons. Thus, the surface of the

memory cells

4 and 4C is in a sufficient hole accumulation state.

Also in this embodiment, as in the first embodiment, the depletion layer spreads at the junction of the reverse-biased N-well 2 and P-well 3, so that free electrons are swept out by the electric field at this time. . That is, electrons are absorbed from the P-well 3 to the end of the depletion layer of the P-well 3 as a minority carrier diffusion current. Thus, excess electrons can be removed.

Also, a reverse bias voltage (2 V in this example) is applied between the N well 2 and the P well 3 even during the period of t3 → t4 (write operation) in this embodiment.

As a result, as in “5)” of the first embodiment, even if the depletion layer of the P-well 3 reaches the vicinity of the junction, the thermal potential is lowered so that no reverse flow due to the diffusion current of electrons to the P-well 3 occurs. can do. This can prevent injection of electrons into the P-well 3 and more reliably prevent erroneous writing (program disturb).

<Third embodiment>
FIG. 9 is a timing chart according to the third embodiment. As shown in the figure, in this embodiment, the application of the reverse bias voltage from t3 to t4 in the first embodiment (see FIG. 4) is omitted. Others are the same as the first embodiment.

As a result, the same operation and effect as “3)” of the first embodiment can be obtained, and even in this case, it is possible to further prevent erroneous writing better than the technique disclosed in the prior art and Patent Document 1. it can.

FIG. 10 is a diagram demonstrating the effect of suppressing erroneous writing in the write operation according to the present embodiment. In the figure, I is the characteristic of the present embodiment, II is the characteristic of the patent document (when a voltage higher than the applied voltage of the word line is applied to the well at t1 → t2), and III is the conventional technique (well at t1 → t2). In the case of the same voltage as that of the word line).

FIG. 10 (a) shows the dependence of the VPASS voltage applied to the non-selected cell on the threshold fluctuation due to the disturb of the selected cell whose write is prohibited. Referring to the figure, if all the word lines WL0 to WLn + 3 are grounded from t1 to t2 and a positive voltage (4 V in this example) is applied to the P-well 3, no program disturb occurs even if VPASS is lowered during the write operation. A VPASS voltage having a sufficient margin for VPASS disturbance can be set. As a result, erroneous writing can be comprehensively suppressed.

Here, the reverse bias voltage is applied at t1 → t2 and t3 → t4, the removal of electrons is promoted, and the case of this embodiment in which inflow prevention is taken is more prominent than the case of Patent Document 1. It can be seen that the program disturb in the low pressure range can be suppressed.

FIG. 10 (b) shows the result of 500 additional writes of the cell threshold cumulative distribution in the non-selected cells. Referring to the figure, the characteristic I of the present embodiment shows the distribution in the initial state. On the other hand, in the conventional technique shown by the characteristic III, the threshold value fluctuates about 10 times, and the distribution greatly collapses at 500 times, which shows that severe program disturb occurs.

On the other hand, the characteristic II in the case of Patent Document 1 in which a reverse bias voltage is not applied between the N well and the P well only by applying a voltage higher than the voltage applied to the word line from t1 to t2 is compared with the characteristic III. Although the change in distribution is much smaller, tailing occurs in the distribution. This indicates that program disturb cannot be completely prevented.

On the other hand, the characteristic I of the present embodiment, in which a reverse bias voltage is also applied, has a distribution that overlaps the initial value even when 500 additional programs are given, no change in threshold is observed, and no program disturb occurs. It is shown that.

<Fourth embodiment>
FIG. 11 is a timing chart according to the fourth embodiment. As shown in the figure, in this embodiment, the application of the reverse bias voltage from t1 to t2 in the first embodiment (see FIG. 4) is omitted. Others are the same as the first embodiment. That is, during the period from t1 to t2, a positive voltage (4 V (second voltage in this example) is applied to the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to the ground voltage (first voltage). )) Is applied. At this time, the non-selected bit line 8B and the source line 9 are set in a floating state. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.

memory cells

4 and 4C related to the non-selected bit line 8B so far move away in the direction of the semiconductor substrate 1. Be made. In addition, the neutral region in the N-type diffusion layer forming the drain and source is also reduced. Thus, the surface of the

memory cells

4 and 4C is in a sufficient hole accumulation state. That is, in this embodiment, the N well 2 and the P well 3 are not reverse-biased, but a certain excess electron removing function is exhibited.

On the other hand, a reverse bias voltage (4 V in this example) is applied between the N well 2 and the P well 3 during the period from t3 to t4 (write operation).

As a result, as in the case of “5)” of the first embodiment, even if the depletion layer of the P well 3 reaches the vicinity of the junction, the thermal potential decreases and a reverse flow due to the diffusion current of electrons from the N well 2 to the P well 3 occurs. It can be prevented from happening. This can prevent injection of electrons into the P-well 3 and contribute to prevention of erroneous writing (program disturb).

<Fifth embodiment>
FIG. 12 is a timing chart according to the fifth embodiment. As shown in the figure, in this embodiment, the application of the reverse bias voltage from t3 to t4 in the second embodiment (see FIG. 8) is omitted. The rest is the same as in the second embodiment. That is, in the period from t1 to t2, the ground voltage (second voltage) is higher than the negative voltage in the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to a negative voltage (-4V (first voltage) in this example). Voltage). Further, in this embodiment, a predetermined positive voltage (2 V (reverse bias voltage) in this example) is applied to the N well 2 so that the bias between the P well 3 and the P well 3 is reversed.

As a result, the same operation and effect as in the case of t1 → t2 of the second embodiment are exhibited, and erroneous writing can be satisfactorily prevented.

<Sixth embodiment>
FIG. 13 is a timing chart according to the sixth embodiment. As shown in the figure, in this embodiment, the application of the reverse bias voltage from t1 to t2 in the second embodiment (see FIG. 8) is omitted. The rest is the same as in the second embodiment. That is, in the period from t1 to t2, the ground voltage (second voltage) is higher than the negative voltage in the P-well 3 in a state where all the word lines WL0 to WLn + 3 are set to a negative voltage (-4V (first voltage) in this example). Voltage).

As a result, the same operation and effect as in the fourth embodiment (see FIG. 11) are exhibited. That is, in this embodiment, the N well 2 and the P well 3 are not reverse-biased, but a certain excess electron removing function is exhibited.

On the other hand, a reverse bias voltage (2 V in this example) is applied between the N well 2 and the P well 3 in the period of t3 → t4 (write operation).

As a result, as in the fourth embodiment (see FIG. 11), even if the depletion layer of the P-well 3 reaches the vicinity of the junction, the thermal potential is lowered so that no reverse flow due to the diffusion current of electrons to the P-well 3 occurs. can do. This can prevent injection of electrons into the P-well 3 and contribute to prevention of erroneous writing (program disturb).

<Seventh embodiment>
FIG. 14 is a timing chart according to the seventh embodiment. As shown in the figure, in this embodiment, a voltage in the same manner as in the first embodiment (see FIG. 4) is applied. However, the reverse bias voltage from t1 to t2 is formed by bringing the N-well 2 into a floating state. More specifically, the P-well 3 is grounded (0 V) from t0 to t1, and at the same time, a reverse bias voltage (2 V in this example) is applied to the N-well 2 and between the P-well 3 and the N-well 2 The charge is precharged in the depletion layer capacitor formed in the first step. Thereafter, the application of the reverse bias voltage (2 V) is stopped at t1, and immediately thereafter, a positive bias is applied to the P well. As a result, the application of the P well bias boosts the N well through the coupling of the depletion layer capacitance, and this is superimposed on the P well bias application voltage when the application of the reverse bias voltage is stopped. As a result, the N well 2 is maintained at a floating voltage higher than the precharge voltage during the period from t1 to t2. Here, the floating voltage is set to be higher than the second voltage (4 V in this example) applied to the P-well 3 from t1 to t2, and as a result, the N-well 2 and P are changed from t1 to t2. A reverse bias voltage is applied to the well. At this time, in order to supplement the capacitance between the N well 2 and the P well 3, it is possible to connect decoupling capacitors inside and outside the chip between the

well electrodes

10 and 11 in parallel.

As a result, in this embodiment, the element configuration of the N-well voltage generation circuit and the N-well bias circuit can be simplified, and the same operations and effects as those of the first embodiment (see FIG. 4) are exhibited. Similarly to the example, erroneous writing can be effectively prevented.

In this embodiment, the non-selected bit line 8B and the source line 9 are in a floating state. This is to prevent the junction with the N-type semiconductor from being forward when the P-well 3 has a positive potential.

<Eighth embodiment>
FIG. 15 is a timing chart according to the eighth embodiment. As shown in the figure, in this embodiment, in the seventh embodiment (see FIG. 14), the application of the reverse bias voltage from t3 to t4 is omitted. Therefore, the same operation and effect as in the third embodiment (see FIG. 9) can be achieved to prevent erroneous writing.

<Ninth embodiment>
FIG. 16 is a timing chart according to the ninth embodiment. As shown in the figure, before t3 → t4 (write operation) in this embodiment, the P well 3 and the N well 2 are set to the same ground voltage as all the word lines WL0 to WLn + 3, and only the t3 → t4 has the N well 2 A reverse bias voltage is applied between the P well 3 and the P well 3.

In this way, even when a reverse bias voltage is applied only during a write operation by applying VPROG (t3 → t4), an increase in the thermal potential accompanying the expansion of the depletion layer when VPROG is set to a high voltage is suppressed. The backflow due to the diffusion current of electrons to 3 can be suppressed. As a result, the injection of electrons into the P-well 3 can be prevented to a certain extent, thereby contributing to prevention of erroneous writing (program disturb).

The present invention can be effectively used in the industrial field of manufacturing and selling semiconductor memories.

I NAND flash memory 2 N well 3

P well

4, 4A, 4B, 4C Memory cell 5

NAND bundle

8, 8A,

8B Bit line

10, 11 Well electrode 21 Memory cell array 22 Write control circuit 25 Word line voltage generation circuit 26 Word Line drive circuit 27 N well voltage generation circuit 28 N well bias circuit 29 P well voltage generation circuit 30 P well bias circuit

Claims

A P well made of a P type semiconductor is formed in an N well made of an N type semiconductor, and a plurality of electrically rewritable nonvolatile memory cells are connected in series on the surface of the P well. A writing method in a nonvolatile semiconductor memory device comprising a memory cell array in which NAND bundles are arranged in a matrix,
A first voltage is applied to the word lines of all the memory cells of the NAND bundle in a period before a write operation (period t3 → t4) by applying a program voltage in a write period (period t0 → t4) to the memory cell. In addition, a second voltage higher than the first voltage is applied to the P well, and a voltage that reversely biases the bit line and the source line with respect to the P well is applied. A writing method in a nonvolatile semiconductor memory device, wherein a reverse bias voltage is applied between the P well and the N well so that the N well is reverse biased with respect to the P well.
A writing method in the nonvolatile semiconductor memory device according to claim 1,
A writing method in a nonvolatile semiconductor memory device, wherein the reverse bias voltage is applied in a period before the writing operation.
A writing method in the nonvolatile semiconductor memory device according to claim 1,
A writing method in a nonvolatile semiconductor memory device, wherein the reverse bias voltage is applied during the writing operation.
A writing method in the nonvolatile semiconductor memory device according to claim 1,
A writing method in a nonvolatile semiconductor memory device, wherein the reverse bias voltage is applied in a period before the writing operation and a period of the writing operation.
A writing method in the nonvolatile semiconductor memory device according to claim 1 or 3,
A writing method in a nonvolatile semiconductor memory device, wherein the first voltage is a ground potential and the second potential is a positive potential.
A writing method in the nonvolatile semiconductor memory device according to claim 2, wherein:
A writing method in a nonvolatile semiconductor memory device, wherein the first voltage is a ground potential and the second potential is a positive potential.
A writing method in the nonvolatile semiconductor memory device according to claim 6,
Due to capacitive coupling between the P well and the N well by applying a reverse bias voltage between the N well and the P well in a period before the write operation and then bringing the N well into a floating state. A writing method in a nonvolatile semiconductor memory device, characterized in that a voltage generated in this manner is the reverse bias voltage.
A writing method in the nonvolatile semiconductor memory device according to claim 1, comprising:
A writing method in a nonvolatile semiconductor memory device, wherein the first voltage is a negative potential and the second potential is a ground potential.
A P well made of a P type semiconductor is formed in an N well made of an N type semiconductor, and a plurality of electrically rewritable nonvolatile memory cells are connected in series on the surface of the P well. A nonvolatile semiconductor memory device comprising a memory cell array in which NAND bundles are arranged in a matrix,
A word line voltage generating circuit for applying a first voltage to the word lines of the memory cell array via a word line driving circuit;
A P well voltage generation circuit for applying a second voltage higher than the first voltage to the P well via a P well bias circuit;
An N-well voltage generating circuit for applying a reverse bias voltage to the N-well via an N-well bias circuit so that the N-well is reverse-biased with respect to the P-well;
A first voltage is applied to the word lines of all the memory cells of the NAND bundle through the word line voltage generation circuit and the word line driving circuit during a period before a write operation by applying a program voltage in the write period to the memory cell. In addition, a second voltage higher than the first voltage is applied to the P well, and a voltage at which the bit line and the source line are reverse-biased with respect to the P well is applied. And a write control circuit for controlling the reverse bias voltage to be applied to the N well via the N well voltage generation circuit and the N well bias circuit.
The nonvolatile semiconductor memory device according to claim 9,
The nonvolatile semiconductor memory device, wherein the write control circuit controls the reverse bias voltage to be applied in a period before the write operation.
The nonvolatile semiconductor memory device according to claim 9,
The non-volatile semiconductor memory device, wherein the write control circuit controls the reverse bias voltage to be applied during the write operation.
The nonvolatile semiconductor memory device according to claim 9,
The non-volatile semiconductor memory device, wherein the write control circuit controls the reverse bias voltage to be applied in a period before the write operation and a period of the write operation.
The nonvolatile semiconductor memory device according to claim 9 or 11,
The nonvolatile semiconductor memory device, wherein the word line voltage generation circuit uses the first voltage as a ground potential, and the P well voltage generation circuit uses the second potential as a positive potential.
The nonvolatile semiconductor memory device according to claim 10 or 12,
The nonvolatile semiconductor memory device, wherein the word line voltage generation circuit uses the first voltage as a ground potential, and the P well voltage generation circuit uses the second potential as a positive potential.
The nonvolatile semiconductor memory device according to claim 14,
The write control circuit applies a reverse bias voltage between the N well and the P well in a period before the write operation, and then sets the N well to be in a floating state so that the P well and the N well A non-volatile semiconductor memory device, wherein a voltage generated due to capacitive coupling is controlled to be the reverse bias voltage.
The nonvolatile semiconductor memory device according to any one of claims 9 to 12,
The non-volatile semiconductor memory device, wherein the word line voltage generation circuit uses the first voltage as a negative potential, and the P well voltage generation circuit uses the second potential as a ground potential.