WO2011052746A1 - Substrat de support d'élément, module semi-conducteur, et appareil portable - Google Patents

Substrat de support d'élément, module semi-conducteur, et appareil portable Download PDF

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Publication number
WO2011052746A1
WO2011052746A1 PCT/JP2010/069353 JP2010069353W WO2011052746A1 WO 2011052746 A1 WO2011052746 A1 WO 2011052746A1 JP 2010069353 W JP2010069353 W JP 2010069353W WO 2011052746 A1 WO2011052746 A1 WO 2011052746A1
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WIPO (PCT)
Prior art keywords
opening
main surface
electrode pad
insulating layer
layered
Prior art date
Application number
PCT/JP2010/069353
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English (en)
Japanese (ja)
Inventor
正幸 長松
清司 柴田
崇紀 林
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2009250413A external-priority patent/JP2011096895A/ja
Priority claimed from JP2009250414A external-priority patent/JP2011096896A/ja
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Publication of WO2011052746A1 publication Critical patent/WO2011052746A1/fr

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
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    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
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    • H05K2203/05Patterning and lithography; Masks; Details of resist
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    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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Abstract

La présente invention concerne un substrat de support d'élément (110), comprenant : un matériau de base (10) ; une couche isolante (30), pourvue sur une surface principale du matériau de base (10), avec une ouverture (32) comprenant une région de formation d'électrode sur le matériau de base (10) exposé depuis cet emplacement ; et un plot d'électrode (22) pourvu dans l'ouverture (32). La couche isolante (30) présente une structure multicouche, avec une pluralité de corps isolants de type couche (33, 34, 35) stratifiés. Les corps isolants de type couche (33, 34, 35) sont configurés de façon à ce que la partie d'extrémité inférieure de l'ouverture dans le corps isolant de type couche supérieure soit positionné sur la surface principale de la périphérie de l'ouverture dans le corps isolant de type couche inférieure. Le plot d'électrode (22) est configuré de façon à ce que sa surface supérieure soit positionnée plus haut que la surface principale inférieure du corps isolant de type couche (35) de la couche la plus haute.
PCT/JP2010/069353 2009-10-30 2010-10-29 Substrat de support d'élément, module semi-conducteur, et appareil portable WO2011052746A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2009250413A JP2011096895A (ja) 2009-10-30 2009-10-30 素子搭載用基板、半導体モジュール、および携帯機器
JP2009250414A JP2011096896A (ja) 2009-10-30 2009-10-30 素子搭載用基板、半導体モジュール、および携帯機器
JP2009-250413 2009-10-30
JP2009-250414 2009-10-30

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WO2011052746A1 true WO2011052746A1 (fr) 2011-05-05

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0487211A (ja) * 1990-07-31 1992-03-19 Furukawa Electric Co Ltd:The 低風騒音低コロナ騒音架空電線
JP2013232445A (ja) * 2012-04-27 2013-11-14 Toshiba Corp 半導体装置
EP3065173A1 (fr) * 2015-03-04 2016-09-07 MediaTek, Inc Ensemble de boîtier de semi-conducteur
CN113113374A (zh) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 一种封装用圆球及其封装结构
WO2023130573A1 (fr) * 2022-01-07 2023-07-13 长鑫存储技术有限公司 Structure semi-conductrice et son procédé de formation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256789A (ja) * 1985-05-10 1986-11-14 株式会社日立製作所 プリント配線板製造方法
JP2005217054A (ja) * 2004-01-28 2005-08-11 Kyocera Corp レジスト付き配線基板及び電気装置並びにその製造方法
JP2009135241A (ja) * 2007-11-30 2009-06-18 Panasonic Corp 回路基板、その製造方法、およびそれを用いた半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61256789A (ja) * 1985-05-10 1986-11-14 株式会社日立製作所 プリント配線板製造方法
JP2005217054A (ja) * 2004-01-28 2005-08-11 Kyocera Corp レジスト付き配線基板及び電気装置並びにその製造方法
JP2009135241A (ja) * 2007-11-30 2009-06-18 Panasonic Corp 回路基板、その製造方法、およびそれを用いた半導体装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0487211A (ja) * 1990-07-31 1992-03-19 Furukawa Electric Co Ltd:The 低風騒音低コロナ騒音架空電線
JP2013232445A (ja) * 2012-04-27 2013-11-14 Toshiba Corp 半導体装置
EP3065173A1 (fr) * 2015-03-04 2016-09-07 MediaTek, Inc Ensemble de boîtier de semi-conducteur
US9704792B2 (en) 2015-03-04 2017-07-11 Mediatek Inc. Semiconductor package assembly
US10147674B2 (en) 2015-03-04 2018-12-04 Mediatek Inc. Semiconductor package assembly
CN113113374A (zh) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 一种封装用圆球及其封装结构
WO2023130573A1 (fr) * 2022-01-07 2023-07-13 长鑫存储技术有限公司 Structure semi-conductrice et son procédé de formation

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