WO2011046020A1 - Substrat de carbure de silicium et son procédé de fabrication et dispositif à semi-conducteurs - Google Patents

Substrat de carbure de silicium et son procédé de fabrication et dispositif à semi-conducteurs Download PDF

Info

Publication number
WO2011046020A1
WO2011046020A1 PCT/JP2010/066963 JP2010066963W WO2011046020A1 WO 2011046020 A1 WO2011046020 A1 WO 2011046020A1 JP 2010066963 W JP2010066963 W JP 2010066963W WO 2011046020 A1 WO2011046020 A1 WO 2011046020A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
silicon carbide
layer
sic
base
Prior art date
Application number
PCT/JP2010/066963
Other languages
English (en)
Japanese (ja)
Inventor
太郎 西口
信 佐々木
真 原田
伸介 藤原
靖生 並川
健良 増田
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to CN2010800237854A priority Critical patent/CN102449733A/zh
Priority to CA2759856A priority patent/CA2759856A1/fr
Priority to US13/258,801 priority patent/US20120012862A1/en
Publication of WO2011046020A1 publication Critical patent/WO2011046020A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a method for manufacturing a silicon carbide substrate, a silicon carbide substrate, and a semiconductor device, and more specifically, a method for manufacturing a silicon carbide substrate and a silicon carbide capable of reducing the manufacturing cost of a semiconductor device using the silicon carbide substrate.
  • the present invention relates to a substrate and a semiconductor device.
  • silicon carbide (SiC) is being adopted as a material constituting a semiconductor device in order to enable a semiconductor device to have a high breakdown voltage, low loss, and use in a high temperature environment.
  • Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device.
  • a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
  • silicon carbide does not have a liquid phase at normal pressure.
  • the crystal growth temperature is as high as 2000 ° C. or higher, and it is difficult to control the growth conditions and stabilize the growth conditions. Therefore, it is difficult to increase the diameter of silicon carbide single crystal while maintaining high quality, and it is not easy to obtain a high-quality silicon carbide substrate having a large diameter.
  • due to the difficulty in manufacturing a large-diameter silicon carbide substrate not only the manufacturing cost of the silicon carbide substrate increases, but also when manufacturing a semiconductor device using the silicon carbide substrate, one batch There is a problem that the number of per-manufactured products decreases and the manufacturing cost of semiconductor devices increases. Further, it is considered that the manufacturing cost of the semiconductor device can be reduced by effectively using the silicon carbide single crystal having a high manufacturing cost as the substrate.
  • an object of the present invention is to provide a method for manufacturing a silicon carbide substrate, a silicon carbide substrate, and a semiconductor device that can reduce the manufacturing cost of a semiconductor device using the silicon carbide substrate.
  • a method of manufacturing a silicon carbide substrate according to the present invention includes a step of preparing a base substrate made of silicon carbide and a SiC substrate made of single crystal silicon carbide, and an intermediate made of a conductor or a semiconductor between the base substrate and the SiC substrate. Forming a layer to join the base substrate and the SiC substrate.
  • a SiC substrate made of single crystal silicon carbide different from the base substrate is bonded onto the base substrate.
  • a base substrate made of low-quality silicon carbide crystal having a high defect density is processed into the predetermined shape and size, and a high-quality but desired shape or the like is not realized on the base substrate.
  • a silicon single crystal can be employed as a SiC substrate for bonding. Since the silicon carbide substrate manufactured by such a process is unified in a predetermined shape and size, it can contribute to the efficiency of manufacturing the semiconductor device.
  • a silicon carbide substrate manufactured by such a process a semiconductor device is manufactured using a SiC substrate made of a high-quality silicon carbide single crystal that has not been used because it cannot be processed into a desired shape or the like. Therefore, the silicon carbide single crystal can be used effectively. Furthermore, in the method for manufacturing a silicon carbide substrate of the present invention, since the base substrate and the SiC substrate are joined by the intermediate layer, the resulting silicon carbide substrate can be handled as an integral free-standing substrate. As a result, according to the method for manufacturing a silicon carbide substrate of the present invention, a silicon carbide substrate capable of reducing the manufacturing cost of a semiconductor device using the silicon carbide substrate can be manufactured.
  • an intermediate layer containing carbon may be formed in the step of bonding the base substrate and the SiC substrate.
  • the base substrate and the SiC substrate are joined by forming an intermediate layer that is made of a conductor containing carbon, for example, a semiconductor device in which a current flows in the thickness direction of the silicon carbide substrate is manufactured. Even when the silicon carbide substrate is used, the presence of the bonding region (intermediate layer) between the base substrate and the SiC substrate can be prevented from adversely affecting the characteristics of the semiconductor device.
  • the step of bonding the base substrate and the SiC substrate is a step of forming a precursor layer that becomes an intermediate layer by heating so as to contact the main surface of the base substrate. And a step of producing a laminated substrate by placing the SiC substrate in contact with the precursor layer, and heating the laminated substrate to make the precursor layer the intermediate layer, thereby forming the base substrate and the SiC substrate. And a step of achieving bonding with the substrate. Thereby, joining of a base substrate and a SiC substrate can be achieved easily.
  • a carbon adhesive may be applied as a precursor on the main surface of the base substrate.
  • a carbon adhesive is suitable as the precursor.
  • the method for manufacturing the silicon carbide substrate at least one of a main surface of the base substrate and a main surface of the SiC substrate that should be opposed to each other with the intermediate layer interposed therebetween before the step of bonding the base substrate and the SiC substrate.
  • the method further includes a step of flattening one of them.
  • the base substrate and the SiC substrate can be more reliably bonded by flattening the surfaces to be bonded surfaces in advance.
  • a plurality of SiC substrates may be arranged side by side on the intermediate layer as viewed in plan. If it demonstrates from another viewpoint, a plurality of SiC substrates may be arranged side by side along the main surface of the base substrate.
  • the plurality of SiC substrates are preferably spread in a matrix as viewed in a plan view.
  • the end surface of an adjacent SiC substrate is substantially perpendicular
  • a silicon carbide substrate can be easily manufactured.
  • the angle formed by the end surface and the main surface is not less than 85 ° and not more than 95 °, it can be determined that the end surface and the main surface are substantially perpendicular.
  • the main surface of the SiC substrate opposite to the base substrate has an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane. It may be.
  • Hexagonal single crystal silicon carbide can be produced in a ⁇ 0001> direction to efficiently produce a high quality single crystal. And from the silicon carbide single crystal grown in the ⁇ 0001> direction, a silicon carbide substrate having a ⁇ 0001 ⁇ plane as a main surface can be efficiently collected. On the other hand, there may be a case where a high-performance semiconductor device can be manufactured by using a silicon carbide substrate having a main surface with an off angle with respect to the plane orientation ⁇ 0001 ⁇ of 50 ° to 65 °.
  • a silicon carbide substrate used for manufacturing a MOSFET generally has a main surface with an off angle of about 8 ° with respect to the plane orientation ⁇ 0001 ⁇ .
  • An epitaxial growth layer is formed on the main surface, and an oxide film, an electrode, and the like are formed on the epitaxial growth layer, thereby obtaining a MOSFET.
  • a channel region is formed in a region including the interface between the epitaxial growth layer and the oxide film.
  • the off-angle of the main surface of the substrate with respect to the ⁇ 0001 ⁇ plane is about 8 °, so that the interface between the epitaxial growth layer and the oxide film in which the channel region is formed Many interface states are formed in the vicinity, hindering carrier travel, and channel mobility is lowered.
  • the off-angle of the main surface of the SiC substrate opposite to the base substrate with respect to the ⁇ 0001 ⁇ plane is set to 50 ° or more and 65 ° or less. Since the off angle of the main surface of the silicon carbide substrate to the ⁇ 0001 ⁇ plane is not less than 50 ° and not more than 65 °, formation of the interface state is reduced, and a MOSFET with reduced on-resistance can be manufactured. .
  • the angle formed between the off orientation of the main surface of the SiC substrate opposite to the base substrate and the ⁇ 1-100> direction is 5 It may be below °.
  • the ⁇ 1-100> direction is a typical off orientation in the silicon carbide substrate. Then, by setting the variation in off orientation due to the variation in slicing in the substrate manufacturing process to 5 ° or less, the formation of an epitaxially grown layer on the silicon carbide substrate can be facilitated.
  • the main surface of the SiC substrate opposite to the base substrate with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction can be -3 ° or more and 5 ° or less.
  • the channel mobility when a MOSFET is manufactured using a silicon carbide substrate can be further improved.
  • the off angle with respect to the plane orientation ⁇ 03-38 ⁇ is set to ⁇ 3 ° or more and + 5 ° or less.
  • the channel mobility is particularly high within this range. Is based on the obtained.
  • the “off angle with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction” is an orthogonal projection of the normal of the principal surface to the plane extending in the ⁇ 1-100> direction and the ⁇ 0001> direction, This is an angle formed with the normal of the ⁇ 03-38 ⁇ plane, and its sign is positive when the orthographic projection approaches parallel to the ⁇ 1-100> direction, and the orthographic projection is in the ⁇ 0001> direction. The case of approaching parallel to is negative.
  • the surface orientation of the main surface is more preferably ⁇ 03-38 ⁇ , and the surface orientation of the main surface is more preferably ⁇ 03-38 ⁇ .
  • the surface orientation of the main surface is substantially ⁇ 03-38 ⁇ , taking into account the processing accuracy of the substrate, etc., the substrate is within an off-angle range where the surface orientation can be substantially regarded as ⁇ 03-38 ⁇ .
  • the off angle range is, for example, a range of ⁇ 2 ° with respect to ⁇ 03-38 ⁇ .
  • the angle formed between the off orientation of the main surface of the SiC substrate opposite to the base substrate and the ⁇ 11-20> direction is 5 It may be below °.
  • the ⁇ 11-20> direction is a typical off orientation in the silicon carbide substrate, similarly to the ⁇ 1-100> direction. Then, by setting the variation in the off orientation due to the variation in the slice processing in the substrate manufacturing process to ⁇ 5 °, it is possible to facilitate the formation of the epitaxial growth layer on the SiC substrate.
  • the base substrate is made of single crystal silicon carbide, and in the step of bonding the base substrate and the SiC substrate, the surface of the main surface of the base substrate that should be opposed to each other with the intermediate layer interposed therebetween
  • the base substrate and the SiC substrate may be arranged so that the orientation and the surface orientation of the main surface of the SiC substrate coincide.
  • the thermal expansion coefficient of single crystal silicon carbide has anisotropy due to the crystal plane. For this reason, when crystal faces having greatly different thermal expansion coefficients are joined, stress due to the difference in the thermal expansion coefficient acts between the base substrate and the SiC substrate. This stress may cause distortion or cracking of the silicon carbide substrate in the manufacture of the silicon carbide substrate and the manufacturing process of the semiconductor device using the silicon carbide substrate. On the other hand, the stress can be relieved by making the plane orientations of the silicon carbide single crystals constituting the surfaces to be bonded coincide as described above. It should be noted that the state in which the surface orientation of the main surface of the base substrate and the surface orientation of the main surface of the SiC substrate coincide with each other does not require that the surface orientations coincide with each other in a strict sense.
  • the plane orientation of the main surface of the base substrate and the SiC substrate is substantially the same.
  • the main surface of the base substrate and the main surface of the SiC substrate that should be opposed to each other with the intermediate layer interposed therebetween may be either the silicon surface side or the carbon surface side, or one of them may be the silicon surface side.
  • the other surface may be a surface on the carbon surface side.
  • the main surface of the SiC substrate opposite to the base substrate has an off angle of 1 ° to 60 ° with respect to the ⁇ 0001 ⁇ plane. It may be.
  • a hexagonal silicon carbide single crystal can be efficiently produced as a high-quality single crystal by growing it in the ⁇ 0001> direction. And, from a silicon carbide single crystal grown in the ⁇ 0001> direction, a surface with a relatively large off angle from the ⁇ 0001 ⁇ plane, specifically a surface with an off angle of 60 ° or less, is relatively efficient. A SiC substrate can be collected. On the other hand, by setting the off angle to 1 ° or more, it becomes easy to form a high-quality epitaxial growth layer on the SiC substrate.
  • the step of bonding the base substrate and the SiC substrate is opposed to the step of bonding the base substrate and the SiC substrate before the step of bonding the base substrate and the SiC substrate. It may be carried out without polishing the main surface of the base substrate and the SiC substrate to be processed.
  • the manufacturing cost of the silicon carbide substrate can be reduced.
  • the main surfaces of the base substrate and the SiC substrate that are to face each other in the step of bonding the base substrate and the SiC substrate may not be polished as described above.
  • a step of bonding the base substrate and the SiC substrate after performing a step of removing the damaged layer by etching Is preferably implemented.
  • the silicon carbide substrate manufacturing method may further include a step of polishing the main surface of the SiC substrate corresponding to the main surface of the SiC substrate opposite to the base substrate.
  • a semiconductor device including the high-quality epitaxially grown layer as an active layer can be manufactured. That is, by adopting such a process, it is possible to obtain a silicon carbide substrate capable of manufacturing a high-quality semiconductor device including an epitaxially grown layer formed on the SiC substrate.
  • the main surface of the SiC substrate may be polished after the base substrate and the SiC substrate are joined, or the main surface of the SiC substrate to be the main surface opposite to the base substrate is previously polished. As a result, it may be performed before the base substrate and the SiC substrate are joined.
  • a silicon carbide substrate according to the present invention includes a base layer made of silicon carbide, an intermediate layer formed in contact with the base layer, and an SiC made of single crystal silicon carbide and disposed in contact with the intermediate layer. With layers.
  • the intermediate layer is made of a conductor or a semiconductor, and joins the base layer and the SiC layer.
  • a SiC layer made of single-crystal silicon carbide different from the base layer is joined on the base layer. Therefore, for example, a high-quality silicon carbide crystal having a high defect density is processed into a base layer by processing a low-quality silicon carbide crystal into a predetermined shape and size convenient for manufacturing a semiconductor device. It is possible to dispose a silicon carbide single crystal in which a favorable shape or the like is not realized as a SiC layer. Since such a silicon carbide substrate is unified in the predetermined shape and size, it can contribute to the efficiency of manufacturing the semiconductor device.
  • the silicon carbide substrate of the present invention since the base layer and the SiC layer are joined and integrated by an intermediate layer made of a conductor or a semiconductor, they can be handled as an integral free-standing substrate. Thus, according to the silicon carbide substrate of the present invention, it is possible to provide a silicon carbide substrate capable of reducing the manufacturing cost of a semiconductor device using the silicon carbide substrate.
  • the intermediate layer may contain carbon.
  • the intermediate layer becomes a conductor by containing carbon, so that the base layer
  • the presence of the junction region (intermediate layer) between the SiC layer and the SiC layer can be prevented from adversely affecting the characteristics of the semiconductor device.
  • the intermediate layer may include graphite particles and non-graphitizable carbon.
  • the graphite particles and the non-graphitizable carbon in the intermediate layer, it is possible to ensure the electrical conductivity between the base layer and the SiC layer more reliably and to firmly bond the base layer and the SiC layer.
  • the intermediate layer has a composite structure of carbon including graphite particles and non-graphitizable carbon, the base layer and the SiC layer can be bonded more firmly.
  • a plurality of the SiC layers may be arranged in a plan view. If it demonstrates from another viewpoint, the SiC layer may be arranged side by side along the main surface of a base layer.
  • the manufacturing process of the semiconductor device can be made efficient.
  • adjacent SiC layers among the plurality of SiC layers are arranged in contact with each other. More specifically, for example, the plurality of SiC layers are preferably laid out in a matrix when viewed in a plan view.
  • the end surface of an adjacent SiC layer is substantially perpendicular
  • a silicon carbide substrate can be easily manufactured.
  • the angle formed by the end surface and the main surface is not less than 85 ° and not more than 95 °, it can be determined that the end surface and the main surface are substantially perpendicular.
  • the base layer may be made of single crystal silicon carbide. In this case, it is preferable that the micropipe of the base layer does not propagate to the SiC layer.
  • the base layer single crystal silicon carbide containing a relatively large number of defects such as micropipes can be employed.
  • a high-quality epitaxial growth layer can be formed on the SiC layer.
  • the silicon carbide substrate of the present invention is not formed by directly growing the SiC layer on the base layer, but can be produced by bonding a separately grown layer on the base layer. It is easy not to propagate the micropipe to the SiC layer.
  • the main surface of the SiC layer opposite to the base layer may have an off angle of 50 ° to 65 ° with respect to the ⁇ 0001 ⁇ plane.
  • the silicon carbide substrate of the present invention by setting the off angle of the main surface of the SiC layer opposite to the base layer to the ⁇ 0001 ⁇ plane to be 50 ° or more and 65 ° or less, for example, the silicon carbide substrate In the case of manufacturing a MOSFET using the same, it is possible to manufacture a MOSFET in which the formation of interface states in the vicinity of the interface between the epitaxial growth layer where the channel region is formed and the oxide film is reduced and the on-resistance is reduced.
  • the angle formed between the off orientation of the main surface opposite to the base layer of the SiC layer and the ⁇ 1-100> direction may be 5 ° or less.
  • the ⁇ 1-100> direction is a typical off orientation in the silicon carbide substrate. Then, by setting the variation in the off orientation due to the variation in the slice processing in the manufacturing process of the substrate to 5 ° or less, the formation of the epitaxial growth layer on the silicon carbide substrate can be facilitated.
  • the off-angle of the main surface of the SiC layer opposite to the base layer with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction may be not less than ⁇ 3 ° and not more than 5 °. .
  • the “off angle with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction” means an orthogonal projection of the normal of the principal surface to the plane extending in the ⁇ 1-100> direction and the ⁇ 0001> direction.
  • the surface orientation of the principal surface is more preferably ⁇ 03-38 ⁇ , and the surface orientation of the principal surface is more preferably ⁇ 03-38 ⁇ .
  • the surface orientation of the main surface is substantially ⁇ 03-38 ⁇ , taking into account the processing accuracy of the substrate, etc., the substrate is within an off-angle range where the surface orientation can be substantially regarded as ⁇ 03-38 ⁇ .
  • the off angle range is, for example, a range of ⁇ 2 ° with respect to ⁇ 03-38 ⁇ .
  • the angle formed between the off orientation of the main surface of the SiC layer opposite to the base layer and the ⁇ 11-20> direction may be 5 ° or less.
  • the ⁇ 11-20> direction is a typical off orientation in the silicon carbide substrate, similarly to the ⁇ 1-100> direction. Then, by setting the variation in off orientation due to the variation in slicing in the manufacturing process of the substrate to ⁇ 5 °, formation of an epitaxially grown layer on the silicon carbide substrate can be facilitated.
  • the main surface of the SiC layer opposite to the base layer may have an off angle with respect to the ⁇ 0001 ⁇ plane of 1 ° or more and 60 ° or less.
  • the base layer may be made of single crystal silicon carbide. In this case, it is preferable that the surface orientation of the main surface of the base layer facing each other across the intermediate layer and the surface orientation of the main surface of the SiC layer coincide.
  • the state that “the plane orientation of the main surface of the base layer and the plane orientation of the main surface of the SiC layer coincide with each other” does not require that the plane orientations coincide with each other in a strict sense. As long as it matches. More specifically, if the angle formed by the crystal plane constituting the main surface of the base layer and the crystal plane constituting the main surface of the SiC layer is 1 ° or less, the plane orientation of the main surface of the base layer and the SiC layer It can be said that the plane orientation of the main surface of this is substantially the same.
  • the main surface of the base layer and the main surface of the SiC layer facing each other across the intermediate layer may both be a silicon surface surface or a carbon surface surface, or one of them may be a silicon surface surface. And the other may be a surface on the carbon surface side.
  • the main surface of the SiC layer opposite to the base layer may be polished. Thereby, a high quality epitaxial growth layer can be formed on the main surface of the SiC layer opposite to the base layer. As a result, a semiconductor device including the high-quality epitaxially grown layer as an active layer can be manufactured. That is, by adopting such a structure, a silicon carbide substrate capable of manufacturing a high-quality semiconductor device including an epitaxial growth layer formed on the SiC layer can be obtained.
  • a semiconductor device includes a silicon carbide substrate, an epitaxial growth layer formed on the silicon carbide substrate, and an electrode formed on the epitaxial growth layer.
  • the silicon carbide substrate is the silicon carbide substrate of the present invention. According to the semiconductor device of the present invention, it is possible to provide a semiconductor device with reduced manufacturing costs by including the silicon carbide substrate of the present invention.
  • a silicon carbide substrate that can reduce the manufacturing cost of a semiconductor device using the silicon carbide substrate can be obtained.
  • a manufacturing method, a silicon carbide substrate, and a semiconductor device can be provided.
  • FIG. 1 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a first embodiment. It is a schematic sectional drawing which shows the structure of the silicon carbide substrate in which the epitaxial growth layer was formed.
  • 3 is a flowchart showing an outline of a method for manufacturing a silicon carbide substrate in the first embodiment. 3 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the first embodiment.
  • FIG. FIG. 6 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a second embodiment. 5 is a flowchart showing an outline of a method for manufacturing a silicon carbide substrate in a second embodiment.
  • FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the second embodiment.
  • FIG. 7 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a third embodiment.
  • 12 is a flowchart showing an outline of a method for manufacturing a silicon carbide substrate in a third embodiment.
  • FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the third embodiment.
  • FIG. 6 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a fourth embodiment.
  • FIG. 6 is a schematic plan view showing the structure of a silicon carbide substrate in a fourth embodiment. It is the schematic which shows the other structure of a silicon carbide substrate.
  • silicon carbide substrate 1 in the present embodiment includes a base layer 10 made of silicon carbide, an intermediate layer 80 formed in contact with base layer 10, and single crystal silicon carbide.
  • SiC layer 20 disposed in contact with intermediate layer 80.
  • Intermediate layer 80 is made of a conductor and joins base layer 10 and SiC layer 20 together. More specifically, the intermediate layer 80 becomes a conductor by containing carbon.
  • the intermediate layer 80 for example, a layer containing graphite particles and non-graphitizable carbon can be employed.
  • the intermediate layer 80 preferably has a composite structure of carbon including graphite particles and non-graphitizable carbon.
  • SiC layer 20 made of single crystal silicon carbide different from base layer 10 is bonded onto base layer 10. Therefore, for example, a silicon carbide crystal having a high defect density and a low quality is processed into a shape and size suitable for the manufacturing process of the semiconductor device to form the base layer 10.
  • a silicon carbide single crystal whose shape or the like favorable for the manufacturing process is not realized can be arranged as SiC layer 20. Since this silicon carbide substrate 1 is unified into an appropriate shape and size, it can contribute to the efficiency of manufacturing the semiconductor device. In silicon carbide substrate 1, since it is possible to manufacture a semiconductor device using silicon carbide single crystal as SiC layer 20 that is high quality but difficult to process into a shape that is convenient for the manufacturing process.
  • silicon carbide substrate 1 is a silicon carbide substrate that can reduce the manufacturing cost of the semiconductor device.
  • intermediate layer 80 is made of a conductor.
  • the intermediate layer can be made of, for example, carbon.
  • the base layer 10 is made of silicon carbide
  • various structures can be employed.
  • the base layer 10 may be polycrystalline silicon carbide or a sintered body of silicon carbide.
  • the base layer 10 may be made of single crystal silicon carbide. In this case, it is preferable that the micropipe of the base layer 10 does not propagate to the SiC layer 20.
  • silicon carbide substrate 1 in the present embodiment can be manufactured by joining separately grown SiC layer 20 on base layer 10 instead of SiC layer 20 grown on base layer 10, It is easy not to propagate the formed micropipes to the SiC layer 20.
  • the electrical resistivity of the base layer 10 is 50Emuomegacm 2 or less, and more preferably 10Emuomegacm 2 or less.
  • the resistance of silicon carbide substrate 1 in the thickness direction is reduced by reducing the thickness of intermediate layer 80.
  • the thickness of the intermediate layer 80 is preferably 10 ⁇ m or less, and more preferably 1 ⁇ m or less. Furthermore, the thickness of the intermediate layer 80 may be 100 nm or less.
  • the electrical resistivity of the intermediate layer 80 is small. Specifically, preferably to 50Emuomegacm 2 or less, and more preferably to 10Emuomegacm 2 or less. Furthermore, the electrical resistivity of the intermediate layer 80 may be 1 m ⁇ cm 2 or less.
  • the intermediate layer 80 may be obtained by baking a carbon adhesive, and may contain a metal element as an additive or as an unintended impurity.
  • the bonding between base layer 10 and SiC layer 20 cannot be maintained due to high-temperature heating (for example, activation annealing of ion-implanted impurities) when silicon carbide substrate 1 is used for manufacturing a semiconductor device.
  • the melting point (or sublimation point) of the intermediate layer 80 is preferably high, and specifically, it is preferably 1800 ° C. or higher.
  • base layer 10 is made of single crystal silicon carbide
  • the plane orientation of the main surface of base layer 10 facing each other across intermediate layer 80 coincides with the plane orientation of the main surface of SiC layer 20. It is preferable. Thereby, the stress which acts between base layer 10 and SiC layer 20 due to the anisotropy of the thermal expansion coefficient can be suppressed.
  • main surface 20A of SiC layer 20 opposite to base layer 10 may have an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane.
  • the angle formed between the off orientation of main surface 20A and the ⁇ 1-100> direction may be 5 ° or less.
  • the ⁇ 1-100> direction is a typical off orientation in a silicon carbide substrate. Then, by setting the variation in the off orientation due to the variation in the slice processing in the substrate manufacturing process to 5 ° or less, the formation of the epitaxial growth layer on the silicon carbide substrate 1 can be facilitated.
  • the off angle of the main surface 20A with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction may be -3 ° or more and 5 ° or less.
  • the angle formed between the off orientation of main surface 20A and the ⁇ 11-20> direction may be 5 ° or less.
  • the ⁇ 11-20> direction is a typical off orientation in the silicon carbide substrate, similarly to the ⁇ 1-100> direction. Then, by setting the variation in off orientation due to the variation in slicing in the substrate manufacturing process to ⁇ 5 °, the formation of an epitaxially grown layer on silicon carbide substrate 1 can be facilitated.
  • main surface 20A may have an off angle of 1 ° or more and 60 ° or less with respect to the ⁇ 0001 ⁇ plane.
  • the thickness of the silicon carbide substrate 1 is preferably 300 ⁇ m or more from the viewpoint of facilitating handling as a self-supporting substrate. Further, when silicon carbide substrate 1 is used for manufacturing a power device, the polytype of SiC layer 20 is preferably 4H type.
  • silicon carbide substrate 1 in the present embodiment it is preferable that main surface 20A of SiC layer 20 on the side opposite to base layer 10 is polished. This makes it possible to form a high quality epitaxial growth layer on the main surface 20A. As a result, a semiconductor device including the high-quality epitaxially grown layer as an active layer can be manufactured. That is, by adopting such a structure, silicon carbide substrate 1 capable of manufacturing a high-quality semiconductor device including an epitaxial growth layer formed on SiC layer 20 can be obtained.
  • a substrate preparation step is performed as a step (S10).
  • step (S10) referring to FIG. 4, base substrate 10 and single crystal silicon carbide SiC substrate 20 made of silicon carbide are prepared.
  • the main surface of the SiC substrate 20 becomes the main surface 20A of the SiC layer 20 obtained by this manufacturing method (see FIG. 1), so that the SiC substrate 20 is aligned with the surface orientation of the desired main surface 20A.
  • Select the orientation of the principal surface for example, SiC substrate 20 whose main surface is a ⁇ 03-38 ⁇ plane is prepared.
  • the base substrate 10 a substrate having an impurity density higher than that of the SiC substrate 20, for example, a substrate having an impurity density higher than 2 ⁇ 10 19 cm ⁇ 3 is employed.
  • the impurity means an impurity introduced to generate majority carriers in the base substrate 10 and the SiC substrate 20 which are semiconductor substrates, and for example, nitrogen can be adopted.
  • the diameter of base substrate 10 is preferably 2 inches or more, and more preferably 6 inches or more, from the viewpoint that a semiconductor device using silicon carbide substrate 1 can be efficiently manufactured.
  • the base substrate 10 and the SiC substrate 20 have the same crystal structure (the same polytype). It is preferable.
  • a substrate flattening step is performed as a step (S20).
  • the main surface (joint surface) of base substrate 10 and SiC substrate 20 that should face each other with the precursor layer interposed therebetween in step (S40) to be described later is planarized by, for example, polishing.
  • this process (S20) is not an essential process, it will become easy to apply
  • the thickness variation (difference between the maximum value and the minimum value) of each of the base substrate 10 and the SiC substrate 20 is preferably as small as possible, and specifically, is preferably 10 ⁇ m or less.
  • the step (S20) may be performed without omitting the step (S20) and polishing the main surfaces of the base substrate 10 and the SiC substrate 20 to be in contact with each other. Thereby, the manufacturing cost of silicon carbide substrate 1 can be reduced. Further, from the viewpoint of removing the damaged layer near the surface formed by slicing or the like during the production of the base substrate 10 and the SiC substrate 20, for example, the step of removing the damaged layer by etching is replaced with the step (S20). Or after performing after the said process (S20), the process (S30) mentioned later may be implemented.
  • an adhesive application step is performed as a step (S30).
  • a carbon adhesive is applied onto the main surface of base substrate 10 to form precursor layer 90.
  • a carbon adhesive what consists of resin, graphite fine particles, and a solvent can be employ
  • the resin a resin that becomes non-graphitizable carbon when heated, such as a phenol resin, can be employed.
  • the solvent for example, phenol, formaldehyde, ethanol, or the like can be used.
  • the coating amount of the carbon adhesive is preferably 10 mg / cm 2 or more and 40 mg / cm 2 or less, and more preferably 20 mg / cm 2 or more and 30 mg / cm 2 or less.
  • the thickness of the carbon adhesive to be applied is preferably 100 ⁇ m or less, and more preferably 50 ⁇ m or less.
  • a stacking step is performed.
  • SiC substrate 20 is placed in contact with precursor layer 90 formed in contact with the main surface of base substrate 10, and the laminated substrate is Produced.
  • main surface 20A of SiC substrate 20 opposite to base substrate 10 may have an off angle of 50 ° to 65 ° with respect to the ⁇ 0001 ⁇ plane.
  • silicon carbide substrate 1 having main surface 20A having an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane can be easily manufactured.
  • the angle formed between the off orientation of the main surface 20A and the ⁇ 1-100> direction may be 5 ° or less.
  • the off angle of the main surface 20A with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction may be -3 ° or more and 5 ° or less.
  • the channel mobility in the case of manufacturing a MOSFET or the like using manufactured silicon carbide substrate 1 can be further improved.
  • the angle formed between the off orientation of the main surface 20A and the ⁇ 11-20> direction may be 5 ° or less.
  • a pre-baking step is performed.
  • the laminated substrate is heated, whereby the solvent component is removed from the carbon adhesive constituting the precursor layer 90.
  • the multilayer substrate is gradually heated to a temperature range exceeding the boiling point of the solvent component while applying a load to the multilayer substrate in the thickness direction. This heating is preferably performed while the base substrate 10 and the SiC substrate 20 are pressure-bonded using a clamp or the like. Further, by performing pre-baking (heating) as much as possible, degassing from the adhesive proceeds, and the strength of bonding can be improved.
  • a firing step is performed as a step (S60).
  • the laminated substrate heated in step (S50) and pre-baked with precursor layer 90 is heated to a high temperature, preferably 900 ° C. to 1100 ° C., for example, 1000 ° C., preferably 10 minutes to 10 minutes.
  • the precursor layer 90 is fired by being held for a period of time, for example, 1 hour.
  • an atmosphere at the time of firing an inert gas atmosphere such as argon is adopted, and the pressure of the atmosphere can be set to atmospheric pressure, for example.
  • the precursor layer 90 becomes the intermediate layer 80 made of carbon which is a conductor.
  • silicon carbide substrate 1 in the first embodiment in which base substrate (base layer) 10 and SiC substrate (SiC layer) 20 are joined by intermediate layer 80 is obtained.
  • SiC substrate 20 made of single crystal silicon carbide different from base substrate 10 is bonded onto base substrate 10. Therefore, for example, a base substrate 10 made of low-quality silicon carbide crystals, which is inexpensive but has a high defect density, is processed into a shape and size suitable for manufacturing a semiconductor device.
  • a silicon carbide single crystal that is not realized in a shape convenient for manufacturing a semiconductor device can be disposed as SiC substrate 20. Since silicon carbide substrate 1 manufactured by such a process is unified in a predetermined shape and size, the manufacturing of the semiconductor device can be made efficient.
  • SiC substrate 20 (SiC layer 20) made of high-quality silicon carbide single crystal that is difficult to be processed into a shape convenient for manufacturing a semiconductor device is used.
  • SiC substrate 20 SiC layer 20
  • base substrate 10 and SiC substrate 20 are joined by intermediate layer 80, and therefore can be handled as an integral free-standing substrate.
  • a silicon carbide substrate capable of reducing the manufacturing cost of a semiconductor device using silicon carbide substrate 1 can be manufactured.
  • silicon carbide substrate 2 shown in FIG. 2 can be manufactured by epitaxially growing single crystal silicon carbide on the silicon carbide substrate to form epitaxial growth layer 60 on main surface 20A of SiC substrate 20.
  • the laminated substrate is manufactured so that the surface orientation of the main surface of the base substrate 10 facing each other with the precursor layer 90 interposed therebetween coincides with the surface orientation of the main surface of the SiC substrate 20. It is preferable. Thereby, the stress which acts between the base substrate (base layer) 10 and the SiC substrate (SiC layer) 20 due to the anisotropy of the thermal expansion coefficient can be suppressed.
  • the off orientation of main surface 20A on the opposite side of base substrate 10 of SiC substrate 20 is the ⁇ 1-100> direction.
  • the off orientation of the main surface is an orientation in which the angle formed with the ⁇ 11-20> direction is 5 ° or less. Also good.
  • the main surface 20A may have an off angle of 1 ° to 60 ° with respect to the ⁇ 0001 ⁇ plane.
  • the step of polishing the main surface of SiC substrate 20 corresponding to main surface 20A on the opposite side of base substrate 10 of SiC substrate 20 in the laminated substrate is performed. Furthermore, you may provide. Thereby, silicon carbide substrate 1 in which main surface 20 ⁇ / b> A on the side opposite to base layer 10 of SiC layer 20 is polished can be manufactured.
  • the step of performing the polishing may be performed before the bonding of the base substrate 10 and the SiC substrate 20 after the step (S10), or may be performed after the bonding.
  • silicon carbide substrate 1 in the second embodiment has basically the same structure as silicon carbide substrate 1 in the first embodiment, and has the same effects.
  • silicon carbide substrate 1 of the second embodiment is different from that of the first embodiment in the configuration of the intermediate layer.
  • silicon carbide substrate 1 in the second embodiment includes base layer 10 made of silicon carbide, intermediate layer 40 formed in contact with base layer 10, and single crystal silicon carbide. And the SiC layer 20 disposed in contact with the intermediate layer 40.
  • Intermediate layer 40 is made of a semiconductor containing amorphous silicon carbide at least in a region adjacent to base layer 10 and a region adjacent to SiC layer 20, and joins base layer 10 and SiC layer 20.
  • base layer 10 and SiC layer 20 are joined and integrated by intermediate layer 40 containing amorphous silicon carbide. The same effect as that of No. 1 silicon carbide substrate can be obtained.
  • the method for manufacturing the silicon carbide substrate in the second embodiment can be performed basically in the same manner as in the first embodiment, and has the same effects. Specifically, referring to FIG. 6, in the method for manufacturing a silicon carbide substrate in the present embodiment, first, steps (S110) and (S120) are performed in steps (S10) and (S20) in the first embodiment. It is carried out in the same way.
  • Si film 30 made of silicon is formed on the main surface of base substrate 10.
  • the formation of the Si film 30 can be performed by a method such as a sputtering method, a vapor deposition method, a liquid phase growth method, or a vapor phase growth method.
  • nitrogen, phosphorus, aluminum, boron, or the like can be doped as an impurity.
  • the Si film 30 may contain titanium.
  • a stacking step is performed.
  • SiC substrate 20 is placed so as to be in contact with Si film 30 formed in contact with the main surface of base substrate 10 to produce a laminated substrate. Is done.
  • a joining step is performed as a step (S150).
  • the base substrate 10 and the SiC substrate 20 are joined by heating the laminated substrate. More specifically, the laminated substrate is heated to, for example, a temperature range of 1300 ° C. or higher and 1800 ° C. or lower and held for 1 hour or longer and 30 hours or shorter. Thereby, carbon is supplied from base substrate 10 and SiC substrate 20 to Si film 30, and at least a part of Si film 30 is converted to silicon carbide.
  • base substrate 10 and SiC substrate 20 are intermediate layers made of a semiconductor formed by converting at least part of Si film 30 into silicon carbide. Since it is strongly bonded by layer 40, silicon carbide substrate 1 that can be handled as an integral free-standing substrate can be manufactured.
  • the Si film 30 may be doped with a desired impurity by adding nitrogen, trimethylaluminum, diborane, phosphine, or the like to the atmosphere in which the multilayer substrate is heated.
  • silicon carbide substrate 1 in the third embodiment has basically the same structure as silicon carbide substrate 1 in the first embodiment, and has the same effects. However, silicon carbide substrate 1 in the third embodiment is different from that in the first embodiment in the configuration of the intermediate layer.
  • silicon carbide substrate 1 in the present embodiment includes a base layer 10 made of silicon carbide, an intermediate layer 50 formed in contact with base layer 10, and a single crystal silicon carbide. And the SiC layer 20 disposed in contact with the intermediate layer 50.
  • Intermediate layer 50 is made of a metal that is a conductor, and joins base layer 10 and SiC layer 20 together. More specifically, intermediate layer 50 is made of, for example, nickel (Ni), and Ni that forms intermediate layer 50 is silicided at least in a region adjacent to base layer 10 and a region adjacent to SiC layer 20. ing.
  • intermediate layer 50 is made of Ni, and Ni constituting intermediate layer 50 is silicided at least in a region adjacent to base layer 10 and a region adjacent to SiC layer 20. It has become. As a result, intermediate layer 50 forms ohmic contact with base layer 10 and SiC layer 20.
  • the metal constituting the intermediate layer 50 is not limited to the above-described nickel, and includes, for example, at least one metal selected from the group consisting of nickel, molybdenum, titanium, aluminum, and tungsten. it can. Thereby, ohmic contact between intermediate layer 50 and base layer 10 and SiC layer 20 can be achieved relatively easily.
  • the method for manufacturing the silicon carbide substrate in the third embodiment can be implemented basically in the same manner as in the first embodiment, and has the same effects. Specifically, referring to FIG. 9, in the method for manufacturing a silicon carbide substrate in the present embodiment, first, steps (S210) and (S220) are performed in steps (S10) and (S20) in the first embodiment. It is carried out in the same way.
  • a metal film forming step is performed as a step (S230).
  • Ni film 51 made of Ni is formed on the main surface of base substrate 10.
  • the Ni film 51 can be formed by, for example, a sputtering method.
  • a stacking step is performed.
  • SiC substrate 20 is placed so as to be in contact with Ni film 51 formed in contact with the main surface of base substrate 10 to produce a laminated substrate. Is done.
  • a joining step is performed as a step (S250).
  • the base substrate 10 and the SiC substrate 20 are joined by heating the laminated substrate. More specifically, by heating the laminated substrate, at least a region adjacent to the base substrate 10 and a region adjacent to the SiC substrate 20 in the Ni film 51 are silicided.
  • base substrate 10 and SiC substrate 20 are joined by intermediate layer 50.
  • the region adjacent to the base substrate 10 and the region adjacent to the SiC substrate 20 in the intermediate layer 50 and the region adjacent to the SiC substrate 20 are silicided, so that an ohmic contact is established between the intermediate layer 50 and the base substrate 10 and the SiC substrate 20. It is formed.
  • silicon carbide substrate 1 shown in FIG. 8 is obtained.
  • FIG. 11 corresponds to a cross-sectional view taken along line XI-XI in FIG.
  • silicon carbide substrate 1 in the fourth embodiment has basically the same configuration as silicon carbide substrate 1 in the first embodiment, and has the same effects.
  • silicon carbide substrate 1 in the fourth embodiment is different from that in the first embodiment in that a plurality of SiC layers 20 are arranged side by side in plan view.
  • silicon carbide substrate 1 of the fourth embodiment a plurality of SiC layers 20 are arranged side by side in a plan view. That is, a plurality of SiC layers 20 are arranged along the main surface 10 ⁇ / b> A of the base layer 10. More specifically, the plurality of SiC layers 20 are arranged in a matrix so that adjacent SiC layers 20 on base substrate 10 are in contact with each other.
  • silicon carbide substrate 1 in the present embodiment is silicon carbide substrate 1 that can be handled as a large-diameter substrate having high-quality SiC layer 20. And by using this silicon carbide substrate 1, the manufacturing process of a semiconductor device can be made efficient. Referring to FIG.
  • end surface 20 ⁇ / b> B of adjacent SiC layer 20 is substantially perpendicular to main surface 20 ⁇ / b> A of SiC layer 20.
  • silicon carbide substrate 1 of the present embodiment can be easily manufactured.
  • silicon carbide substrate 1 in the fourth embodiment has a plurality of SiC substrates 20 whose end surface 20B is substantially perpendicular to main surface 20A on precursor layer 90 in step (S40) in the first embodiment. Can be manufactured in the same manner as in the first embodiment.
  • the shape of the SiC layer 20 is not limited to this.
  • the planar shape of SiC layer 20 can be any shape such as a hexagonal shape, a trapezoidal shape, a rectangular shape, or a circular shape, and these are mixed. May be.
  • a semiconductor device 101 according to the present invention is a vertical DiMOSFET (Double Implanted MOSFET), and includes a substrate 102, a buffer layer 121, a breakdown voltage holding layer 122, a p region 123, an n + region 124, and p +.
  • a region 125, an oxide film 126, a source electrode 111 and an upper source electrode 127, a gate electrode 110, and a drain electrode 112 formed on the back side of the substrate 102 are provided.
  • buffer layer 121 made of silicon carbide is formed on the surface of substrate 102 made of silicon carbide of n-type conductivity.
  • substrate 102 the silicon carbide substrate of the present invention including silicon carbide substrate 1 described in the first to fourth embodiments is employed.
  • buffer layer 121 is formed on SiC layer 20 of silicon carbide substrate 1.
  • Buffer layer 121 has n-type conductivity, and its thickness is, for example, 0.5 ⁇ m.
  • the density of the n-type conductive impurity in the buffer layer 121 can be set to 5 ⁇ 10 17 cm ⁇ 3 , for example.
  • a breakdown voltage holding layer 122 is formed on the buffer layer 121.
  • the breakdown voltage holding layer 122 is made of silicon carbide of n-type conductivity, and has a thickness of 10 ⁇ m, for example. Further, as the density of the n-type conductive impurity in the breakdown voltage holding layer 122, for example, a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
  • p regions 123 having a p-type conductivity are formed at intervals. Inside the p region 123, an n + region 124 is formed in the surface layer of the p region 123. A p + region 125 is formed at a position adjacent to the n + region 124. From the n + region 124 in one p region 123 to the p region 123, the breakdown voltage holding layer 122 exposed between the two p regions 123, the other p region 123, and the n + region 124 in the other p region 123. An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126.
  • a source electrode 111 is formed on the n + region 124 and the p + region 125.
  • An upper source electrode 127 is formed on the source electrode 111.
  • a drain electrode 112 is formed on the back surface of the substrate 102 which is the surface opposite to the surface on which the buffer layer 121 is formed.
  • a silicon carbide substrate of the present invention such as the silicon carbide substrate 1 described in the first to fourth embodiments is employed as the substrate 102. That is, the semiconductor device 101 includes a substrate 102 as a silicon carbide substrate, a buffer layer 121 and a breakdown voltage holding layer 122 as epitaxial growth layers formed on the substrate 102, and a source electrode 111 formed on the breakdown voltage holding layer 122. It has.
  • the substrate 102 is a silicon carbide substrate of the present invention such as the silicon carbide substrate 1.
  • the silicon carbide substrate of the present invention is a silicon carbide substrate capable of reducing the manufacturing cost of the semiconductor device. Therefore, the semiconductor device 101 is a semiconductor device with reduced manufacturing costs.
  • a substrate preparation step (S310) is performed.
  • a substrate 102 (see FIG. 16) made of silicon carbide having a (03-38) plane as a main surface is prepared.
  • the silicon carbide substrate of the present invention including silicon carbide substrate 1 manufactured by the manufacturing method described in the first to fourth embodiments is prepared.
  • this substrate 102 for example, a substrate having an n-type conductivity and a substrate resistance of 0.02 ⁇ cm may be used.
  • an epitaxial layer forming step (S320) is performed. Specifically, the buffer layer 121 is formed on the surface of the substrate 102. Buffer layer 121 is formed on SiC layer 20 of silicon carbide substrate 1 employed as substrate 102 (see FIGS. 1, 5, 8, and 11). Buffer layer 121 is formed of an n-type silicon carbide, and an epitaxial layer having a thickness of 0.5 ⁇ m, for example, is formed. As the density of the conductive impurities in the buffer layer 121, for example, a value of 5 ⁇ 10 17 cm ⁇ 3 can be used. Then, a breakdown voltage holding layer 122 is formed on the buffer layer 121 as shown in FIG.
  • breakdown voltage holding layer 122 a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method.
  • a thickness of the breakdown voltage holding layer 122 for example, a value of 10 ⁇ m can be used.
  • a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
  • an injection step (S330) is performed as shown in FIG. Specifically, by using an oxide film formed by photolithography and etching as a mask, an impurity having a conductivity type of p type is implanted into the breakdown voltage holding layer 122, whereby the p region 123 is formed as shown in FIG. Form. Further, after removing the used oxide film, an oxide film having a new pattern is formed again by photolithography and etching. Then, by using the oxide film as a mask, an n-type conductive impurity is implanted into a predetermined region, thereby forming an n + region 124. Further, the p + region 125 is formed by injecting a p-type conductive impurity in the same manner. As a result, a structure as shown in FIG. 17 is obtained.
  • activation annealing is performed.
  • this activation annealing treatment for example, argon gas is used as an atmospheric gas, and conditions such as a heating temperature of 1700 ° C. and a heating time of 30 minutes can be used.
  • a gate insulating film formation step (S340) is performed. Specifically, as illustrated in FIG. 18, an oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, the p region 123, the n + region 124, and the p + region 125.
  • a condition for forming this oxide film 126 for example, dry oxidation (thermal oxidation) may be performed.
  • dry oxidation thermal oxidation
  • conditions for this dry oxidation conditions such as a heating temperature of 1200 ° C. and a heating time of 30 minutes can be used.
  • a nitrogen annealing step (S350) is performed as shown in FIG. Specifically, the annealing process is performed using nitrogen monoxide (NO) as the atmosphere gas.
  • NO nitrogen monoxide
  • the heating temperature is 1100 ° C. and the heating time is 120 minutes.
  • nitrogen atoms are introduced near the interface between the oxide film 126 and the underlying breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125.
  • annealing using nitrogen monoxide as an atmospheric gas annealing using nitrogen monoxide as an atmospheric gas.
  • argon (Ar) gas which is an inert gas may be performed.
  • argon gas may be used as the atmosphere gas
  • the heating temperature may be 1100 ° C. and the heating time may be 60 minutes.
  • an electrode formation step is performed as shown in FIG. Specifically, a resist film having a pattern is formed on the oxide film 126 by using a photolithography method. Using the resist film as a mask, portions of the oxide film located on n + region 124 and p + region 125 are removed by etching. After that, a conductor film such as a metal is formed so as to be in contact with the n + region 124 and the p + region 125 on the resist film and inside the opening formed in the oxide film 126. Thereafter, by removing the resist film, the conductor film located on the resist film is removed (lifted off).
  • nickel (Ni) can be used as the conductor.
  • a source electrode 111 and a drain electrode 112 can be obtained as shown in FIG.
  • an argon (Ar) gas that is an inert gas is used as the atmosphere gas, and a heat treatment (alloying treatment) is performed with a heating temperature of 950 ° C. and a heating time of 2 minutes.
  • an upper source electrode 127 (see FIG. 14) is formed on the source electrode 111. Further, a drain electrode 112 (see FIG. 14) is formed on the back surface of the substrate 102. Further, the gate electrode 110 (see FIG. 14) is formed on the oxide film 126. In this way, the semiconductor device 101 shown in FIG. 14 can be obtained. That is, semiconductor device 101 is manufactured by forming an epitaxial growth layer and an electrode on SiC layer 20 of silicon carbide substrate 1.
  • the vertical MOSFET has been described as an example of a semiconductor device that can be manufactured using the silicon carbide substrate of the present invention.
  • the semiconductor device that can be manufactured is not limited thereto.
  • various semiconductor devices such as JFET (Junction Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and Schottky barrier diode can be manufactured using the silicon carbide substrate of the present invention. It is.
  • the semiconductor device is manufactured by forming the epitaxial layer functioning as the operation layer on the silicon carbide substrate having the (03-38) plane as the main surface has been described.
  • the crystal plane that can be used as the main surface is not limited to this, and any crystal plane according to the application including the (0001) plane can be used as the main surface.
  • the off angle with respect to the (0-33-8) plane in the ⁇ 01-10> direction is ⁇ 3 ° or more and + 5 °
  • the (0001) plane of hexagonal single crystal silicon carbide is defined as the silicon plane
  • the (000-1) plane is defined as the carbon plane.
  • the “off angle with respect to the (0-33-8) plane in the ⁇ 01-10> direction” refers to the above described plane extending in the ⁇ 01-10> direction as a reference for the ⁇ 000-1> direction and the off orientation.
  • the main surface having an off angle with respect to the (0-33-8) plane in the ⁇ 01-10> direction of -3 ° or more and + 5 ° or less is a carbon surface satisfying the above conditions in a silicon carbide crystal. Means the side face.
  • the (0-33-8) plane includes an equivalent carbon plane-side plane whose expression differs depending on the setting of an axis for defining a crystal plane, and does not include a silicon plane-side plane. That is, since the ⁇ 03-38 ⁇ plane is a plane on the carbon plane side, the channel mobility when a MOSFET or the like is manufactured using a silicon carbide substrate can be further improved.
  • Example 1 Embodiment 1 of the present invention will be described below.
  • the silicon carbide substrate of the present invention was actually fabricated, and an experiment was conducted to investigate the electrical characteristics in the intermediate layer (bonding interface).
  • the experimental method is as follows.
  • a silicon carbide substrate of the present invention as a sample was produced.
  • the production of the silicon carbide substrate was performed in the same manner as in the first embodiment.
  • a base substrate and a SiC substrate were prepared.
  • the base substrate a substrate having a shape with a diameter of 2 inches and a thickness of 400 ⁇ m, made of single crystal silicon carbide having a polytype of 4H, and having a (03-38) main surface was adopted.
  • the conductivity type of the base substrate was n-type, and the n-type impurity density was 1 ⁇ 10 20 cm ⁇ 3 .
  • the micropipe density of the base substrate was 1 ⁇ 10 4 cm ⁇ 2 and the stacking fault density was 1 ⁇ 10 5 cm ⁇ 1 .
  • the SiC substrate has a rectangular shape of 15 mm ⁇ 30 mm and a thickness of 400 ⁇ m, is made of single crystal silicon carbide having a polytype of 4H, and the main surface is the (03-38) surface.
  • the board was adopted.
  • the conductivity type of the SiC substrate was n-type, and the n-type impurity density was 1 ⁇ 10 19 cm ⁇ 3 .
  • the micropipe density of the SiC substrate was 0.2 cm ⁇ 2 and the stacking fault density was less than 1 cm ⁇ 1 .
  • the main surface to be a bonding surface in the base substrate and the SiC substrate was polished by lapping, mechanical polishing, and CMP (Chemical Mechanical Polishing). Then, a carbon adhesive containing 29% graphite fine particles and containing a resin that becomes non-graphitizable carbon when heated is applied to the main surface of the polished base substrate. Furthermore, the SiC substrate was placed so that the polished main surface was in contact with the main surface of the base substrate to which the carbon adhesive was applied, and a laminated substrate was manufactured.
  • the laminated substrate was placed on a hot plate, and the temperature was increased by 20 ° C. per hour up to 200 ° C. while applying a load of 10 kg in the thickness direction.
  • the thickness of the carbon adhesive layer (precursor layer) after pre-baking was about 5 ⁇ m.
  • the laminated substrate was placed in a resistance heating type heat treatment furnace, heated to 1100 ° C., and held for 1 hour.
  • the main surface of the obtained silicon carbide substrate is ground to make the thickness uniform, and the thickness variation (difference between the maximum value and the minimum value in the silicon carbide substrate) is 5 ⁇ m. did.
  • ohmic electrodes were formed on the main surfaces on both sides of the silicon carbide substrate.
  • the ohmic electrode was formed by forming a nickel film on the principal surfaces on both sides and silicidizing by heating. This silicidation heat treatment can be performed by heating to a temperature of 900 ° C. or higher and 1100 ° C. or lower in an inert gas atmosphere and holding for 10 minutes or longer and 10 hours or shorter. This was carried out by heating to 1000 ° C. and holding for 1 hour in the atmosphere.
  • the voltage was applied between the said ohmic electrodes, and the electrical property in a joining interface (intermediate layer which consists of carbon formed by baking carbon adhesive) was investigated.
  • the electrical resistivity of the intermediate layer calculated from the ohmic characteristics was about 1 m ⁇ cm 2 . From this, it was confirmed that according to the method for manufacturing a silicon carbide substrate of the present invention, it is possible to manufacture a silicon carbide substrate in which a plurality of silicon carbide substrates are bonded while ensuring ohmic characteristics in the thickness direction. It was.
  • Example 2 Next, Example 2 of the present invention will be described.
  • the silicon carbide substrate of the present invention was actually fabricated, and an experiment was conducted to confirm the state of the interface between the base layer and the SiC layer.
  • a silicon carbide substrate of the present invention was produced as an experimental sample in the same procedure as in Example 1 (Example).
  • a silicon carbide substrate outside the scope of the present invention in which the application of the carbon adhesive and the pre-bake treatment were omitted in the same procedure as in Example 1 was also produced (Comparative Example).
  • SEM Sccanning Electron Microscope; Scanning electron microscope.
  • a semiconductor device can be manufactured using the silicon carbide substrate of the present invention. That is, in the semiconductor device of the present invention, an epitaxial growth layer as an operation layer is formed on the silicon carbide substrate manufactured by the method for manufacturing a silicon carbide substrate of the present invention. If it demonstrates from another viewpoint, the epitaxial growth layer as an operation
  • the semiconductor device of the present invention includes a base layer made of silicon carbide, an intermediate layer formed in contact with the base layer, and an SiC layer made of single crystal silicon carbide and disposed in contact with the intermediate layer. And an epitaxial growth layer formed on the SiC layer and an electrode formed on the epitaxial growth layer.
  • the intermediate layer is made of a conductor or a semiconductor, and joins the base layer and the SiC layer.
  • a method for manufacturing a silicon carbide substrate, a silicon carbide substrate and a semiconductor device according to the present invention are particularly applicable to a method for manufacturing a silicon carbide substrate, a silicon carbide substrate and a semiconductor device that require reduction in the manufacturing cost of a semiconductor device using the silicon carbide substrate. It can be advantageously applied.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un substrat de carbure de silicium, comprenant : un substrat de base (10) comprenant du carbure de silicium et un substrat de SiC (20) comprenant du carbure de silicium monocristallin sont préparés ; et une couche intermédiaire (80) comprenant du carbone, qui est un conducteur, est formée entre le substrat de base (10) et le substrat de SiC (20), joignant ainsi le substrat de base (10) et le substrat de SiC (20) l'un à l'autre.
PCT/JP2010/066963 2009-10-13 2010-09-29 Substrat de carbure de silicium et son procédé de fabrication et dispositif à semi-conducteurs WO2011046020A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2010800237854A CN102449733A (zh) 2009-10-13 2010-09-29 制造碳化硅衬底的方法、碳化硅衬底和半导体器件
CA2759856A CA2759856A1 (fr) 2009-10-13 2010-09-29 Substrat de carbure de silicium et son procede de fabrication et dispositif a semi-conducteurs
US13/258,801 US20120012862A1 (en) 2009-10-13 2010-09-29 Method for manufacturing silicon carbide substrate, silicon carbide substrate, and semiconductor device

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2009236211 2009-10-13
JP2009236204 2009-10-13
JP2009-236211 2009-10-13
JP2009-236204 2009-10-13
JP2010170489 2010-07-29
JP2010-170489 2010-07-29

Publications (1)

Publication Number Publication Date
WO2011046020A1 true WO2011046020A1 (fr) 2011-04-21

Family

ID=43876073

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2010/066963 WO2011046020A1 (fr) 2009-10-13 2010-09-29 Substrat de carbure de silicium et son procédé de fabrication et dispositif à semi-conducteurs
PCT/JP2010/066964 WO2011046021A1 (fr) 2009-10-13 2010-09-29 Procédé de fabrication de substrat en carbure de silicone et substrat en carbure de silicone

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/066964 WO2011046021A1 (fr) 2009-10-13 2010-09-29 Procédé de fabrication de substrat en carbure de silicone et substrat en carbure de silicone

Country Status (8)

Country Link
US (2) US20120012862A1 (fr)
EP (1) EP2490247A1 (fr)
JP (1) JPWO2011046021A1 (fr)
KR (2) KR20120022932A (fr)
CN (2) CN102449733A (fr)
CA (2) CA2759861A1 (fr)
TW (2) TW201128773A (fr)
WO (2) WO2011046020A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013061702A1 (fr) * 2011-10-24 2013-05-02 住友電気工業株式会社 Procédé de fabrication de dispositif semi-conducteur
WO2018016417A1 (fr) * 2016-07-19 2018-01-25 株式会社サイコックス Substrat semi-conducteur

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5343984B2 (ja) * 2011-01-17 2013-11-13 株式会社デンソー 化合物半導体基板およびその製造方法
TWI491067B (zh) * 2012-07-19 2015-07-01 華夏光股份有限公司 半導體裝置的形成方法
US8980728B2 (en) 2012-01-06 2015-03-17 Phostek, Inc. Method of manufacturing a semiconductor apparatus
US8963297B2 (en) 2012-01-06 2015-02-24 Phostek, Inc. Semiconductor apparatus
TWI466343B (zh) 2012-01-06 2014-12-21 Phostek Inc 發光二極體裝置
JP2014007325A (ja) * 2012-06-26 2014-01-16 Sumitomo Electric Ind Ltd 炭化珪素半導体装置の製造方法
US8860040B2 (en) 2012-09-11 2014-10-14 Dow Corning Corporation High voltage power semiconductor devices on SiC
US9018639B2 (en) 2012-10-26 2015-04-28 Dow Corning Corporation Flat SiC semiconductor substrate
US9797064B2 (en) 2013-02-05 2017-10-24 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion
US9738991B2 (en) 2013-02-05 2017-08-22 Dow Corning Corporation Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion
US9017804B2 (en) 2013-02-05 2015-04-28 Dow Corning Corporation Method to reduce dislocations in SiC crystal growth
US8940614B2 (en) 2013-03-15 2015-01-27 Dow Corning Corporation SiC substrate with SiC epitaxial film
JP2014203833A (ja) * 2013-04-01 2014-10-27 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP6242640B2 (ja) * 2013-09-20 2017-12-06 株式会社東芝 半導体装置およびその製造方法
US9279192B2 (en) 2014-07-29 2016-03-08 Dow Corning Corporation Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
WO2017090279A1 (fr) * 2015-11-24 2017-06-01 住友電気工業株式会社 Substrat en carbure de silicium monocristallin, substrat épitaxial en carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
CN108899369B (zh) * 2018-06-27 2020-11-03 东南大学 一种石墨烯沟道碳化硅功率半导体晶体管
JP7416935B2 (ja) * 2019-11-14 2024-01-17 ファーウェイ デジタル パワー テクノロジーズ カンパニー リミテッド 半導体基板、その製造方法、及び半導体装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223496A (ja) * 1997-02-12 1998-08-21 Ion Kogaku Kenkyusho:Kk 単結晶ウエハおよびその製造方法
JPH1129397A (ja) * 1997-07-04 1999-02-02 Nippon Pillar Packing Co Ltd 単結晶ＳｉＣおよびその製造方法
WO2001018872A1 (fr) * 1999-09-07 2001-03-15 Sixon Inc. TRANCHE DE SiC, DISPOSITIF A SEMI-CONDUCTEUR DE SiC, ET PROCEDE DE PRODUCTION D'UNE TRANCHE DE SiC
JP2002280531A (ja) * 2001-03-19 2002-09-27 Denso Corp 半導体基板及びその製造方法
JP2003509842A (ja) * 1999-09-03 2003-03-11 ステアーグ アール ティ ピー システムズ インコーポレイテッド 急速加熱中の反射性基板の温度を制御するための系
JP2009117533A (ja) * 2007-11-05 2009-05-28 Shin Etsu Chem Co Ltd 炭化珪素基板の製造方法
JP2009158933A (ja) * 2007-12-04 2009-07-16 Sumitomo Electric Ind Ltd 炭化ケイ素半導体装置およびその製造方法
JP2009172637A (ja) * 2008-01-23 2009-08-06 Seiko Epson Corp 接合体の形成方法および接合体

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308445A (en) * 1991-10-23 1994-05-03 Rohm Co., Ltd. Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate
JP3647515B2 (ja) * 1995-08-28 2005-05-11 株式会社デンソー ｐ型炭化珪素半導体の製造方法
RU2160329C1 (ru) * 1997-06-27 2000-12-10 Ниппон Пиллар Пэкинг Ко., Лтд МОНОКРИСТАЛЛ SiC И СПОСОБ ЕГО ПОЛУЧЕНИЯ
US6248646B1 (en) * 1999-06-11 2001-06-19 Robert S. Okojie Discrete wafer array process
US6528373B2 (en) * 2001-02-12 2003-03-04 Cree, Inc. Layered dielectric on silicon carbide semiconductor structures
DE102005017814B4 (de) * 2004-04-19 2016-08-11 Denso Corporation Siliziumkarbid-Halbleiterbauelement und Verfahren zu dessen Herstellung
US7314521B2 (en) * 2004-10-04 2008-01-01 Cree, Inc. Low micropipe 100 mm silicon carbide wafer
US7531849B2 (en) * 2005-01-25 2009-05-12 Moxtronics, Inc. High performance FET devices
WO2008056698A1 (fr) * 2006-11-10 2008-05-15 Sumitomo Electric Industries, Ltd. Dispositif semi-conducteur de carbure de silicium et procédé de fabrication de celui-ci

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223496A (ja) * 1997-02-12 1998-08-21 Ion Kogaku Kenkyusho:Kk 単結晶ウエハおよびその製造方法
JPH1129397A (ja) * 1997-07-04 1999-02-02 Nippon Pillar Packing Co Ltd 単結晶ＳｉＣおよびその製造方法
JP2003509842A (ja) * 1999-09-03 2003-03-11 ステアーグ アール ティ ピー システムズ インコーポレイテッド 急速加熱中の反射性基板の温度を制御するための系
WO2001018872A1 (fr) * 1999-09-07 2001-03-15 Sixon Inc. TRANCHE DE SiC, DISPOSITIF A SEMI-CONDUCTEUR DE SiC, ET PROCEDE DE PRODUCTION D'UNE TRANCHE DE SiC
JP2002280531A (ja) * 2001-03-19 2002-09-27 Denso Corp 半導体基板及びその製造方法
JP2009117533A (ja) * 2007-11-05 2009-05-28 Shin Etsu Chem Co Ltd 炭化珪素基板の製造方法
JP2009158933A (ja) * 2007-12-04 2009-07-16 Sumitomo Electric Ind Ltd 炭化ケイ素半導体装置およびその製造方法
JP2009172637A (ja) * 2008-01-23 2009-08-06 Seiko Epson Corp 接合体の形成方法および接合体

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
M. NAKABAYASHI ET AL.: "Growth of Crack-free 1 OOmm-diameter 4H-SiC Crystals with Low Micropipe Densities", MATER. SCI. FORUM, vol. 600-603, 2009, pages 3 - 6
M. NAKABAYASHI ET AL.: "Growth of Crack-free 100mm-diameter 4H-SiC Crystals with Low Micropipe Densities", MATER. SCI. FORUM, vol. 600-603, 2009, pages 3 - 6

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013061702A1 (fr) * 2011-10-24 2013-05-02 住友電気工業株式会社 Procédé de fabrication de dispositif semi-conducteur
WO2018016417A1 (fr) * 2016-07-19 2018-01-25 株式会社サイコックス Substrat semi-conducteur
JP2018014372A (ja) * 2016-07-19 2018-01-25 株式会社サイコックス 半導体基板
US10680068B2 (en) 2016-07-19 2020-06-09 Sicoxs Corporation Semiconductor substrate

Also Published As

Publication number Publication date
TW201128773A (en) 2011-08-16
CN102449733A (zh) 2012-05-09
CN102449732A (zh) 2012-05-09
KR20120022932A (ko) 2012-03-12
KR20120022952A (ko) 2012-03-12
CA2759856A1 (fr) 2011-04-21
JPWO2011046021A1 (ja) 2013-03-07
WO2011046021A1 (fr) 2011-04-21
TW201133587A (en) 2011-10-01
US20120012862A1 (en) 2012-01-19
CA2759861A1 (fr) 2011-04-21
EP2490247A1 (fr) 2012-08-22
US20120025208A1 (en) 2012-02-02

Similar Documents

Publication Publication Date Title
WO2011046020A1 (fr) Substrat de carbure de silicium et son procédé de fabrication et dispositif à semi-conducteurs
JP5344037B2 (ja) 炭化珪素基板および半導体装置
JP2011243770A (ja) 炭化珪素基板、半導体装置、炭化珪素基板の製造方法
WO2011052320A1 (fr) Procédé de production d'un substrat en carbure de silicium et substrat en carbure de silicium
WO2011142158A1 (fr) Processus de production d'un substrat de carbure de silicium, processus de production d'un dispositif semi-conducteur, substrat de carbure de silicium, et dispositif semi-conducteur
WO2011052321A1 (fr) Substrat de carbure de silicium et procédé de fabrication associé
WO2010131571A1 (fr) Dispositif à semi-conducteurs
WO2011092893A1 (fr) Procédé de fabrication d'un substrat en carbure de silicium
WO2011077797A1 (fr) Substrat de carbure de silicium
WO2012127748A1 (fr) Substrat de carbure de silicium
WO2011152089A1 (fr) Processus permettant de produire un substrat de carbure de silicium, processus permettant de produire un dispositif à semi-conducteur, substrat de carbure de silicium et dispositif à semi-conducteur
JP2011243618A (ja) 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置
JP2011243617A (ja) 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置
JP2011086660A (ja) 炭化珪素基板の製造方法および炭化珪素基板
JP2011243771A (ja) 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置
WO2011086734A1 (fr) Procédé pour la production de substrat en carbure de silicium
JP2011243640A (ja) 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080023785.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10823288

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 13258801

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2010823288

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2759856

Country of ref document: CA

ENP Entry into the national phase

Ref document number: 20117026944

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE