Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76846—Layer combinations
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
  • H01L21/76883—Post-treatment or after-treatment of the conductive material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76844—Bottomless liners

Definitions

• the present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to an interconnect structure of the single or dual damascene type in which a large grain size conductive structure is employed to reduce resistivity of conductive lines and/or vias, especially narrow conductive lines and/or vias having a feature size below 75 nm.
• semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate.
• a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures.
• the wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, -based interconnects.
• metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as "crosstalk") are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than silicon dioxide.
• the conductive material within the conductive region has a low electromigration resistance due to a high number of electromigration paths inside the conductive region.
• the high number of paths is believed to be a result of the microstructure and the average grain size of the conductive material.
• electromigration is predominately driven by (1) interface diffusion between the conductive material and the dielectric cap, and (2) bulk diffusion along the grain boundaries of the conductive material. The electromigration problem is expected to increase in future semiconductor technologies due to the scaling of such devices.
• One problem addressed in the present invention is the high electrical resistivity that is exhibited for conductive lines and vias. This becomes a significant problem as the features sizes of the conductive lines and/or vias decline below 75 nm.
• a large fraction of the high resistivity can be attributed to small grain size (on the order of 0.02 microns or less) in the conductive features, such as, for example copper, Cu, features.
• Grain boundary scattering can cause an increase in resistance in conductive metals.
• the small grain size of the conductive material within the conductive features is caused by prior process technology used in forming the same. Grain growth that was observed in larger dimension generations is not seen in very small features as grain boundary motion from the overburden does not extend down into small features.
• a method of forming an interconnect structure that substantially reduces, and in some instances eliminates, the high electrical resistance that is exhibited by prior art interconnect structures.
• the method includes forming at least one opening in a dielectric material.
• a grain growth promotion layer is thereafter formed within the at least one opening.
• an agglomerated plating seed layer is formed on the exposed surfaces of the grain growth promotion layer.
• the agglomerated plating seed layer is formed by deposition and a subsequent first anneal. The first anneal is performed under conditions that cause agglomeration of a deposited plating seed layer within the at least one opening.
• a conductive structure is formed within the at least one opening.
• the conductive structure is formed by deposition of a metal-containing conductive material followed by a subsequent second anneal that causes grain growth of the metal-containing conductive material.
• a diffusion barrier is formed within the at least one opening prior to forming the grain growth promotion layer within the at least one opening.
• another plating seed layer can be formed within the at least one opening between the steps of the forming the agglomerated plating seed layer and forming the conductive structure.
• the method described above creates a conductive structure within the at least one opening that has a bamboo microstructure and an average grain size of larger than 0.05 microns.
• the conductive structure within the at least one opening includes grains that have a (111) crystal orientation.
• an interconnect structure having reduced electrical resistance includes a dielectric material including at least one opening therein.
• the at least one opening is filled with a grain growth promotion layer, an agglomerated plating seed layer which is located on upper surfaces of the grain growth promotion layer, and a conductive structure which is located above upper surfaces of the agglomerated plating seed layer.
• the conductive structure which includes a metal- containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns.
• the conductive structure includes grains that have a (111) crystal orientation.
• a diffusion barrier is present within the at least one opening.
• the diffusion barrier is located between exposed sidewalls of the dielectric material including the at least one opening and the grain growth promotion layer.
• another plating seed layer is located between the agglomerated plating seed layer and the conductive structure.
• FIG. 1 is a pictorial representation (through a cross sectional view) illustrating an interconnect structure in accordance with an embodiment of the invention through initial stages wherein at least one opening is provided in a dielectric material;
• FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the interconnect structure of FIG. 1 after formation of an optional diffusion barrier inside the at least one opening;
• FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the interconnect structure of FIG. 2 after formation of a grain growth promotion layer within the at least one opening;
• FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the interconnect structure of FIG. 3 after formation of a plating seed layer;
• FIG. 5 is a pictorial representation (through a cross sectional view) illustrating the interconnect structure of FIG. 4 after performing a first anneal that agglomerates the plating seed layer;
• FIG. 6 is a pictorial representation (through a cross sectional view) illustrating the interconnect structure of FIG. 5 after forming a conductive structure within the at least one opening.
• a closed- via bottom is illustrated on the right hand side;
• FIGS. 7A and 7B are pictorial representations (through cross sectional views) depicting alternative interconnect structures that can be formed in the present invention;
• FIG. 7A includes an interconnect structure with an open- via bottom structure, while
• FIG. 7B includes an interconnect structure with an anchored-via bottom structure.
• FIG. 1 illustrates an initial interconnect structure 10 that can be employed in some embodiments of the invention. Specifically, the initial
• interconnect structure 10 shown in FIG. 1 includes a multilevel interconnect including a lower interconnect level 12 and an upper interconnect level 16 that are separated in part by dielectric capping layer 14.
• the lower interconnect level 12 which may be located above a semiconductor substrate including one or more semiconductor devices, comprises a first dielectric material 18 having at least one conductive feature (i.e., conductive region) 20 that is separated from the first dielectric material 18 by a barrier layer 22.
• the upper interconnect level 12 which may be located above a semiconductor substrate including one or more semiconductor devices, comprises a first dielectric material 18 having at least one conductive feature (i.e., conductive region) 20 that is separated from the first dielectric material 18 by a barrier layer 22.
• the upper conductive feature i.e., conductive region
• interconnect level 16 comprises a second dielectric material 24 that has at least one opening located therein.
• reference number 26 denotes a line opening for a single damascene structure
• reference numeral 28A and 28B denote a via opening and a line opening, respectively for a dual damascene structure.
• FIG. 1 illustrates a separate line opening and an opening for a via and a line
• the present invention also contemplates cases in which only the line opening is present or cases in which the opening for the combined via and line is present.
• the feature size of the at least one opening may vary. In some embodiments, the feature size of the at least one opening is below 75 nm.
• the initial interconnect structure 10 shown in FIG. 1 can be made utilizing standard interconnect processing which is well known in the art.
• the initial interconnect structure 10 can be formed by applying the first dielectric material 18 to a surface of a substrate (not shown).
• the substrate which is not shown, may include a semiconducting material, an insulating material, a conductive material or any combination thereof.
• any semiconductor such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/V or II/VI compound semiconductors can be used.
• the present invention also contemplates cases in which the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).
• the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).
• the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers.
• the substrate may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal silicide, a metal nitride or combinations thereof including multilayers.
• the substrate comprises a semiconducting material, one or more semiconductor devices such as, for example, complementary metal oxide
• CMOS complementary metal-oxide-semiconductor
• the first dielectric material 18 of the lower interconnect level 12 may include any interlevel or intralevel interconnect dielectric including inorganic dielectrics or organic dielectrics.
• the first dielectric material 18 may be porous or non-porous.
• suitable dielectrics that can be used as the first dielectric material 18 include, but are not limited to Si0 2 , silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof.
• polyarylene is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.
• the first dielectric material 18 typically has a dielectric constant that is about 4.0 or less, with a dielectric constant of about 2.8 or less being more typical. These dielectrics generally have a lower parasitic cross talk as compared with dielectric materials that have a higher dielectric constant than 4.0.
• the thickness of the first dielectric material 18 may vary depending upon the dielectric material used as well as the exact number of dielectrics within the lower interconnect level 12. Typically, and for normal interconnect structures, the first dielectric material 18 has a thickness from 200 nm to 450 nm.
• the lower interconnect level 12 also has at least one conductive feature 20 that is embedded in (i.e., located within) the first dielectric material 18.
• the conductive feature 20 comprises a conductive region that is separated from the first dielectric material 18 by a barrier layer 22.
• the conductive feature 20 can be formed by lithography (i.e., applying a photoresist to the surface of the first dielectric material 18, exposing the photoresist to a desired pattern of radiation, and developing the exposed resist utilizing a conventional resist developer), etching (dry etching or wet etching) an opening in the first dielectric material 18 and filling the etched region with the barrier layer 22 and then with a conductive material forming the conductive region.
• the barrier layer 22 which may comprise Ta, TaN, Ti, TiN, Ru, RuN, W, WN or any other material that can serve as a barrier to prevent conductive material from diffusing there through, is typically formed by a deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, chemical solution deposition, or plating.
• ALD atomic layer deposition
• CVD chemical vapor deposition
• PECVD plasma enhanced chemical vapor deposition
• PVD physical vapor deposition
• sputtering chemical solution deposition, or plating.
• the thickness of the barrier layer 22 may vary depending on the exact means of the deposition process as well as the material employed. Typically, the barrier layer 22 has a thickness from 4 nm to 40 nm, with a thickness from 7 nm to 20 nm being more typical.
• the remaining region of the opening within the first dielectric material 18 is filled with a conductive material forming the conductive region.
• the conductive material used in forming the conductive region includes, for example, polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal silicide or combinations thereof.
• the conductive material that can be used in forming the conductive region is a metal-containing conductive material such as, for example, Cu, W or Al, with Cu or a Cu alloy (such as AlCu) being preferred in some embodiment of the present invention.
• the conductive material can be filled into the remaining opening in the first dielectric material 18 utilizing a conventional deposition process including, but not limited to CVD, PECVD, sputtering, chemical solution deposition or plating. After deposition, a conventional planarization process such as, for example, chemical mechanical polishing (CMP) can be used to provide a structure in which the barrier layer 22 and the conductive feature 20 each have an upper surface that is substantially coplanar with the upper surface of the first dielectric material 18.
• CMP chemical mechanical polishing
• the inventive method described herein below can be used to provide the conductive feature 20 with a conductive structure having a bamboo microstructure and an average grain size of larger than 0.05 microns.
• the term "average grain size" is used throughout this application to denote the average grain size of the conductive material of the conductive structure.
• the average grain size is measured utilizing standard techniques such as, for example, by placing a polished and etched specimen under a microscope and counting the number of grains inside a certain area, that are well known to those skilled in the art. The average grain size inside the microstructure is then calculated based on the known magnification, the number of grains, and the inspected area.
• a dielectric capping layer 14 can be formed on the surface of the lower interconnect level 12 utilizing a conventional deposition process such as, for example, CVD, PECVD, chemical solution deposition, or evaporation. In some embodiments, dielectric capping layer 14 is omitted.
• the dielectric capping layer 14 includes any suitable dielectric capping material such as, for example, SiC, Si 4 NH 3 , Si0 2 , a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof.
• the thickness of the capping layer 14 may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the capping layer 14 has a thickness from 15 nm to 55 nm, with a thickness from 25 nm to 45 nm being more typical.
• Upper interconnect level 16 is formed by applying the second dielectric material 24 to the upper exposed surface of the dielectric capping layer 14, if present, or directly atop the lower interconnect level 12 when the dielectric capping layer 14 is not present.
• the second dielectric material 24 may comprise the same or different, preferably the same, dielectric material as that of the first dielectric material 18 of the lower interconnect level 12.
• the processing techniques and thickness ranges for the first dielectric material 18 are also applicable here for the second dielectric material 24.
• At least one opening is formed into the second dielectric material 24 utilizing lithography, as described above, and etching.
• the etching may comprise a dry etching process, a wet chemical etching process or a
• dry etching is used herein to denote an etching technique such as reactive-ion etching, ion beam etching, plasma etching or laser ablation.
• reference number 26 denotes a line opening for a single damascene structure
• reference numeral 28A and 28B denote a via opening and a line opening, respectively for a dual damascene structure. It is again emphasized that the present invention contemplates structures including only opening 26 or openings 28A and 28B.
• the etching step also removes a portion of the dielectric capping layer 14 that is located atop the conductive feature 20 in order to make electrical contact between interconnect level 12 and level 16.
• An optional diffusion barrier 30 having diffusion barrier properties can be provided by forming the optional diffusion barrier 30 on all exposed surfaces (including wall surfaces within the opening) of the second dielectric material 24.
• the resultant structure including the optional barrier layer 30 is shown, for example, in FIG. 2.
• the optional diffusion barrier 30 comprises a same or different material as that of barrier layer 22.
• optional diffusion barrier 30 may comprise Ta, TaN, Ti, TiN, Ru, RuN, W, WN or any other material that can serve as a barrier to prevent a conductive material from diffusing there through. Combinations of these materials are also contemplated forming a multilayered stacked diffusion barrier.
• the optional diffusion barrier 30 can be formed utilizing a deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, chemical solution deposition, or plating.
• ALD atomic layer deposition
• CVD chemical vapor deposition
• PECVD plasma enhanced chemical vapor deposition
• PVD physical vapor deposition
• sputtering chemical solution deposition, or plating.
• the thickness of the optional diffusion barrier 30 may vary depending on the number of material layers within the barrier, the technique used in forming the same as well as the material of the diffusion barrier itself. Typically, the optional diffusion barrier 30 has a thickness from 4 nm to 40 nm, with a thickness from 7 nm to 20 nm being even more typical.
• FIG. 3 shows the structure of FIG. 2 after formation of grain growth promotion layer (GGPL) 32 atop the optional diffusion barrier 30.
• the GGPL 32 would be formed on exposed surfaces of the second dielectric material 24 including in each of the openings.
• the GGPL 32 is comprised of any material, typically a metal or metal alloy, which aids in the formation of a conductive material that has an average grain size of larger than 0.05 microns.
• suitable materials for the GGPL 32 include, but are not limited to Ru, Co, Ir, Rh, Mo, Re, Hf, Nb and alloys thereof. In some embodiments, Ru, Ir, Co or Rh are preferably used as the GGPL 32.
• the GGPL 32 can be formed by a conventional deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).
• CVD chemical vapor deposition
• PECVD plasma enhanced chemical vapor deposition
• ALD atomic layer deposition
• PVD physical vapor deposition
• the thickness of the GGPL 32 may vary depending on number of factors including, for example, the
• the GGPL 32 has a thickness from 0.5 nm to 10 nm, with a thickness of less than 6 nm being even more typical.
• FIG. 4 shows the resultant structure formed after forming a plating seed layer 34.
• the plating seed layer 34 aids in the growth of a subsequently formed metal-containing conductive material within the at least one opening.
• the plating seed layer 34 may comprise a conductive metal or metal alloy such as that used in forming the conductive structure 38 to be described in greater detail herein below.
• the plating seed layer 34 comprises Cu, CuAl, Culr, CuTa, CuRh, or other alloys of Cu, i.e., Cu-containing alloys.
• the plating seed layer 34 can be formed by a conventional deposition process including, for example, ALD, CVD, PECVD, PVD, chemical solution deposition and other like deposition processes.
• the thickness of the plating seed layer 34 may vary and it is within ranges that are well known to those skilled in the art. Typically, the plating seed layer 34 has a thickness from 2 nm to 80 nm.
• plating seed layer 34 is formed at a deposition temperature of 30°C or less, with a deposition temperature from 20°C to -30°C being preferred. Such low temperature depositions avoid subsequent conductive material agglomeration within the at least one opening.
• FIG. 5 shows the structure that is formed after subjecting the structure shown in FIG. 4 to a first anneal.
• the first anneal is performed under conditions which cause substantial agglomeration of the plating seed layer 34.
• the agglomerated plating seed layer that is formed by this first anneal is designated as 34'.
• FIG. 5 depicts the agglomerated plating seed layer 34' as a continuous layer, the agglomerated plating seed layer 34' may be discontinuous including breaks within the layer.
• portions of the underlying diffusion barrier or second dielectric material may be exposed. It is observed that much of the agglomeration of the plating seed layer 34 occurs within the at least one opening, not on horizontal surfaces of the interconnect structure.
• the agglomerated plating seed layer 34' has fairly large metallic grains inside the at least one opening. These large metallic grains are the seed crystallites for grain growth of the later-deposited metal-containing conductive material. Since these large metallic grains, e.g., seed crystallite, are already present within the at least one opening, a conductive structure having a large grain size can be obtained during a post conductive material deposition anneal.
• the first anneal that causes the substantial agglomeration of the plating seed layer 34 is typically performed at a temperature from 200°C to 400°C, with a temperature from 250°C to 300°C being more typical.
• the first anneal is performed in a reducing atmosphere such as, for example, H 2 , N 2 or a mixture thereof.
• the first anneal is performed under vacuum.
• the first anneal is performed for a period of time which causes sufficient agglomeration of the plating seed layer 34 within the at least one opening.
• the anneal is performed for a time period of 100 minutes or less, with a time period of 30 minutes or less being more typical.
• another plating seed layer (not shown) can be formed atop the agglomerated plating seed layer 34'.
• the another plating seed layer may comprise the same or different plating seed material as plating seed layer 34.
• the another plating seed layer (not shown) is comprised of the same plating seed material as plating seed layer 34.
• the another plating seed layer can be formed utilizing one of the deposition techniques mentioned above with respect to plating seed layer 34.
• the another plating seed layer can have a thickness within the range mentioned above for plating seed layer 34.
• the another plating seed layer is used to ensure that no portions of the underlying diffusion barrier or second dielectric material are exposed during subsequent formation of the conductive structure.
• FIG. 6 shows the structure after forming a conductive structure 38 within the at least one opening.
• the interconnect structure shown in FIG. 6 represents one possible embodiment of the present invention, while the interconnect structures shown in FIGS. 7 A and 7B represent other possible embodiments of the present invention.
• a closed-via bottom interconnect structure is shown.
• the conductive structure 38 is formed within an open-via bottom structure.
• the open-via interconnect structure is formed by removing the optional diffusion barrier 30 from the bottom of via 28A utilizing ion bombardment or another like directional etching process prior to deposition of the other elements.
• FIG. 7B an anchored-via bottom interconnect structure is shown.
• the anchored-via bottom interconnect structure is formed by first etching a recess into the conductive feature 20 utilizing a selective etching process.
• the optional diffusion barrier 30 is then formed and it is selectively removed from the bottom portion of the via and recess by utilizing one of the above-mentioned techniques.
• the other elements, i.e., GGPL 32, agglomerated plating seed layer 34', and conductive structure 38, are then formed as described herein.
• the conductive structure 38 may comprise the same or different, preferably the same, metal-containing conductive material as that of the conductive feature 20; note that the conductive material used in forming the conductive structure 38 does not include polySi. Preferably, Cu, Al, W or alloys thereof are used as the metal- containing conductive material of conductive structure 38, with Cu or AlCu being most preferred.
• the metal-containing conductive material of conductive structure 38 is formed utilizing the same deposition processing as described above in forming the conductive feature 20. Following the deposition of the metal- containing conductive material within the at least one opening, a second anneal is performed that causes the formation of conductive structure 38.
• the second anneal which is used in forming the conductive structure 38 is typically performed at a temperature from 80°C to 300°C, with a temperature from 100°C to 200°C being more typical.
• the second anneal is typically performed in an inert ambient such as, for example, N 2 , He and/Ar.
• the duration of the second anneal may vary.
• the second anneal is performed for a time period of 60 minutes or less.
• the conductive structure 38 thus formed includes a metal-containing conductive material as mentioned above.
• the conductive structure 38 further has a bamboo microstructure and an average grain size of larger than 0.05 microns.
• the average grain size of the conductive structure 38 is from 0.05 microns to 0.5 microns.
• the average grain size of the conductive structure 38 is from 0.08 microns to 0.2 microns.
• the conductive structure 38 includes conductive grains that have a (111) crystal orientation.
• the term "bamboo microstructure" is used herein to denote that the conductive material of the conductive structure 38 is composed of grains all of which are larger than the cross sectional dimensions of the interconnect.
• a bamboo microstructure is different from a near bamboo microstructure which is a mixture of bamboo and
• the interconnect structure can be subjected to planarization.
• the planarization process which can occur prior to, or after the second anneal, removes the optional diffusion barrier 30, GGPL 32, agglomerated plating seed layer 34' and conductive structure 38 that are present above the upper horizontal surface of the upper interconnect level 16.
• the method of the present application is applicable in forming such a conductive structure as a conductive feature in any one or all of the interconnect levels of an interconnect structure.
• the same basic processing steps can be used to form other semiconductor structures, such as, for example, a field effect transistor, in which the conductive material is a gate electrode that has the inventive microstructure and average grain size.
• the effects of the grain size and morphology of the conductive structure 38 within an interconnect structure include the following: (i) The relatively large grain size of the conductive structure 38 provides a conductive structure 38 that has a low number of grain boundaries as compared to other morphologies, a low electron scattering effect (on the order of 10% ⁇ 30% less than that of the prior art), and a relatively low electrical resistance (on the order of about 10% ⁇ 30% less than that of the prior art. Because of these properties, the interconnect structure of the present invention exhibits better performance than conventional interconnect structure, (ii) The bamboo microstructure provides less electromigration paths inside the conductive structure, high electromigration resistance, and can withstand current density (of greater than 6 mA/ ⁇ 2 ), and thus, better circuit reliability.

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• 2009
  • 2009-09-16 US US12/560,878 patent/US7956463B2/en active Active
• 2010
  • 2010-08-25 GB GB1200519.5A patent/GB2485689B/en not_active Expired - Fee Related
  • 2010-08-25 DE DE112010003659T patent/DE112010003659T5/de not_active Ceased
  • 2010-08-25 CN CN2010800407893A patent/CN102498560A/zh active Pending
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