CN104952786B - 电互连结构及其形成方法 - Google Patents
电互连结构及其形成方法 Download PDFInfo
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- CN104952786B CN104952786B CN201410113767.5A CN201410113767A CN104952786B CN 104952786 B CN104952786 B CN 104952786B CN 201410113767 A CN201410113767 A CN 201410113767A CN 104952786 B CN104952786 B CN 104952786B
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- 238000000034 method Methods 0.000 title claims abstract description 101
- 239000000463 material Substances 0.000 claims abstract description 152
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 230000008569 process Effects 0.000 claims abstract description 50
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 239000012528 membrane Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims description 78
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 46
- 229910052802 copper Inorganic materials 0.000 claims description 46
- 239000010949 copper Substances 0.000 claims description 46
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 24
- 239000013078 crystal Substances 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 239000010408 film Substances 0.000 description 123
- 230000005611 electricity Effects 0.000 description 9
- 230000012010 growth Effects 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 239000012670 alkaline solution Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000008707 rearrangement Effects 0.000 description 3
- 229910021205 NaH2PO2 Inorganic materials 0.000 description 2
- 229910004541 SiN Inorganic materials 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910018565 CuAl Inorganic materials 0.000 description 1
- 229910016344 CuSi Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- KTVIXTQDYHMGHF-UHFFFAOYSA-L cobalt(2+) sulfate Chemical compound [Co+2].[O-]S([O-])(=O)=O KTVIXTQDYHMGHF-UHFFFAOYSA-L 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
一种电互连结构及其形成方法,其中,电互连结构的形成方法包括:表面具有导电膜的衬底,导电膜材料的晶格呈第一晶粒结构排布,单个完整的第一晶粒结构具有第一晶粒尺寸,导电膜具有第一厚度,第一厚度大于第一晶粒尺寸;采用退火工艺使导电膜材料的晶粒尺寸增大,使导电膜材料的晶格呈第二晶粒结构排布,单个完整的第二晶粒结构具有第二晶粒尺寸,第二晶粒尺寸大于第一晶粒尺寸,第一厚度大于或等于第二晶粒尺寸;刻蚀部分导电膜直至暴露出衬底表面为止,形成导电层;刻蚀部分导电层,在导电层内形成凹槽,位于凹槽侧壁的部分导电层形成导电插塞,位于导电插塞底部和凹槽底部的部分导电层形成电互连线。所形成的电互连结构性能良好。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种电互连结构及其形成方法。
背景技术
在半导体制造领域中,为了实现半导体器件之间的电连接,目前已发展出各种金属互连结构以及形成工艺,例如铜互连结构,以及形成铜互连结构的铜电镀工艺(ECP,electro-coppering plating)。然而,随着超大规模集成电路(ULSI)的发展,半导体器件的特征尺寸(CD)不断缩小,形成金属互连结构的工艺也受到了挑战。
图1是现有的一种铜互连结构的剖面结构示意图,如图1所述的铜互连结构的形成方法包括:提供衬底100,所述衬底100表面具有第一介质层101,所述第一介质层101内具有导电层102,所述第一介质层101暴露出导电层102;在所述第一介质层101和导电层102表面形成第二介质层103;在所述第二介质层103内形成暴露出导电层102的开口,所述开口包括位于导电层102表面的第一子开口、以及位于第一子开口顶部的第二子开口,所述第一子开口和第二子开口贯通,且第二子开口的尺寸大于第一子开口,且所述第二子开口底部能够具有一个或多个第一子开口;所述第二介质层103的表面和开口的侧壁和底部表面形成种子层,所述种子层的材料为导电材料;采用电镀工艺在所述种子层表面形成填充满开口的铜材料层;刻蚀去除部分第二介质层103表面的铜材料层,形成铜互连结构105,此外,也可以采用化学机械抛光工艺去除第二介质层103表面的铜材料层。
然而,现有的铜互连结构的电性能不佳。
发明内容
本发明解决的问题是提供一种电互连结构及其形成方法,所形成的电互连结构性能优良、形貌良好。
为解决上述问题,本发明提供一种电互连结构的形成方法,包括:提供衬底,在衬底表面形成导电膜,所述导电膜材料的晶格呈第一晶粒结构排布,单个完整的第一晶粒结构具有第一晶粒尺寸,所述导电膜具有第一厚度,所述第一厚度大于第一晶粒尺寸;采用退火工艺使所述导电膜材料的晶粒尺寸增大,使导电膜材料的晶格呈第二晶粒结构排布,单个完整的第二晶粒结构具有第二晶粒尺寸,所述第二晶粒尺寸大于第一晶粒尺寸,所述第一厚度大于或等于第二晶粒尺寸;刻蚀部分导电膜直至暴露出衬底表面为止,形成导电层;刻蚀部分导电层,在所述导电层内形成凹槽,所述凹槽的深度小于第一厚度,位于所述凹槽侧壁的部分导电层形成导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层形成电互连线,所述电互连线垂直于衬底表面方向的尺寸小于所述第二晶粒尺寸,所述导电插塞平行于衬底表面方向的尺寸小于所述第二晶粒尺寸;在衬底表面、导电层的侧壁表面和凹槽内形成第二介质层。
可选的,所述导电膜的材料为铜,所述导电膜的第一厚度大于2000埃。
可选的,所述退火工艺的参数包括:温度为200摄氏度~450摄氏度,时间为5分钟~30分钟。
可选的,形成所述导电层的刻蚀工艺包括:在所述导电膜表面形成第一掩膜,所述第一掩膜定义了所需形成的电互连线平行于衬底表面方向的图形;以所述第一掩膜为掩膜,采用各向异性的干法刻蚀工艺刻蚀所述导电膜,直至暴露出衬底表面为止,形成导电层;在形成导电层之后,去除所述第一掩膜。
可选的,所述第一掩膜包括:位于导电膜表面的第一抗反射层、位于第一抗反射层表面的第一掩膜层、以及位于第一掩膜层表面的第一光刻胶层。
可选的,所述第一抗反射层的材料为无定形碳或底层抗反射材料,所述第一掩膜层的材料为氧化硅或氮氧化硅。
可选的,形成所述凹槽的刻蚀工艺包括:在导电层部分表面形成第二掩膜,所述第二掩膜定义了所需形成的导电插塞平行于衬底表面方向的图形;以所述第二掩膜为掩膜,采用各向异性的干法刻蚀工艺刻蚀所述导电层,在导电层内形成凹槽;在形成凹槽后,去除所述第二掩膜。
可选的,所述第二掩膜包括:位于导电层表面的第二抗反射层、位于第二抗反射层表面的第二掩膜层、以及位于第二掩膜层表面的第二光刻胶层。
可选的,所述第二抗反射层的材料为无定形碳或底层抗反射材料,所述第二掩膜层的材料为氧化硅或氮氧化硅。
可选的,所述各向异性的干法刻蚀工艺的参数包括:刻蚀气体包括氢气,温度10摄氏度~40摄氏度,气压5毫托~100毫托,偏置功率为100瓦~1000瓦。
可选的,所述导电层由一个铜晶粒构成。
可选的,还包括:在所述退火工艺之后,减薄所述导电膜的部分厚度,使所述导电膜具有第二厚度。
可选的,还包括:在形成所述导电膜之前,在衬底表面形成第一阻挡层,所述导电膜形成于所述第一阻挡层表面。
可选的,所述第一阻挡层的材料为钽和氮化钽的组合、镧、铜锰合金或钴。
可选的,还包括:在形成所述凹槽之后,在所述导电层的侧壁和凹槽侧壁表面形成第二阻挡层。
可选的,所述第二阻挡层包括第一阻挡材料层,所述第一阻挡材料层的形成工艺为选择性沉积工艺在所述导电层的侧壁和底部表面、以及凹槽的侧壁和底部表面,所述第一阻挡材料层的材料为CoWP或Co。
可选的,所述第二阻挡层还包括第二阻挡材料层,所述第二阻挡材料层在形成所述第一阻挡材料层之前或之后形成,所述第二阻挡材料层形成于导电层的侧壁和凹槽侧壁,所述第二阻挡材料层的材料为钽和氮化钽的组合,所述第二阻挡材料层的形成工艺包括:在衬底表面、导电层表面和凹槽的侧壁和底部表面沉积阻挡膜;回刻蚀所述阻挡膜直至暴露出衬底表面为止。
可选的,所述第二介质层的材料为低K介质材料,所述低K介质材料的介电系数低于2.5;所述电互连线之间的第二介质层内具有空隙。
可选的,所述衬底包括:半导体基底、位于半导体基底表面的第一介质层、位于第一介质层内的导电结构,所述导电结构的顶部表面与第一介质层表面齐平,所述电互连线位于所述导电结构的顶部表面。
相应的,本发明还提供一种采用上述任一种方法所形成的电互连结构,包括:衬底;位于部分衬底表面的导电层,所述导电层的具有第一厚度,所述导电层的材料具有第二晶粒尺寸;位于所述导电层内的凹槽,所述凹槽的深度小于第一厚度,位于所述凹槽侧壁的部分导电层作为导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层作为电互连线,所述电互连线垂直于衬底表面方向的尺寸和所述导电插塞平行于衬底表面方向的尺寸小于所述第二晶粒尺寸;位于衬底表面和凹槽内的第二介质层。
与现有技术相比,本发明的技术方案具有以下优点:
本发明的形成方法中,在衬底表面形成具有第一晶粒结构的导电膜,所述第一晶粒结构具有第一晶粒尺寸,而所述导电膜的第一厚度大于第一晶粒尺寸,因此,所述导电膜材料的晶粒具有足够生长的空间,能够在退火工艺之后,使导电膜材料的晶格重排列并呈第二晶粒结构排布,而所述第二晶粒结构具有第二晶粒尺寸,所述第二晶粒尺寸大于第一晶粒尺寸,从而使所形成的导电膜具有较低的电阻,以所述导电膜形成的导电插塞和电互连线具有优良的电性能。其次,刻蚀所述导电膜形成导电层,在所述导电层内形成凹槽,位于所述凹槽侧壁的部分导电层形成导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层形成电互连线,即所述导电插塞和电互联线均由导电膜形成,无需使导电插塞和电互连线的形成工艺分开进行,使得形成所述电互连结构的工艺简单。再次,由于所述导电膜用于形成电互连线、以及位于电互连线表面的导电插塞,而且所述导电插塞的高度和电互连线的厚度和较大,因此即使所述导电膜的第一厚度较大,也无需在形成导电层之前对所述导电膜进行过多减薄,使得形成电互连结构的工艺易于操作,且所形成的电互连结构的形貌良好。
进一步,所述导电膜的材料为铜,所述导电膜的第一厚度大于2000埃。由于所述导电膜的第一厚度较大,给予铜晶粒足够的生长空间,因此在退火工艺后,能够使导电膜具有较大的第二晶粒尺寸,从而使所述导电膜具有较低的电阻,由所述导电膜形成的电互连结构的性能良好。
进一步,所述电互连线之间的第二介质层内具有空隙。由于电互连线的尺寸大于导电插塞的尺寸,使电互连线之间的空间小于导电插塞之间的空间,则第二介质层内的空隙易于形成在电互连线之间,因此,所述空隙易于形成于第二介质层的底部,从而能够避免后续工艺使所述空隙被打开、且后续工艺的材料落入所述空隙的问题。提高了所形成的电互连结构的稳定性。
本发明的结构中,所述导电层内具有凹槽,位于所述凹槽侧壁的部分导电层作为导电插塞,位于所述导电插塞底部和第一凹槽底部的部分导电层作为电互连线。由于所述电互连线垂直于衬底表面方向的尺寸、以及所述导电插塞平行于衬底表面方向的尺寸均小于所述第二晶粒尺寸,即所述导电层材料的第二晶粒尺寸较大,因此所述导电层的电阻较低,使所述电互连结构的性能优良。
附图说明
图1是现有的一种铜互连结构的剖面结构示意图;
图2至图10是本发明实施例的电互连结构的形成过程的剖面结示意图。
具体实施方式
如背景技术所述,现有的铜互连结构的电性能不佳。
经过研究发现,对于金属材料来说,金属材料具有多晶态的晶粒结构,且单个完整的晶粒结构的晶粒尺寸越大,所述金属材料的电阻越低,因此,为了使铜互连结构105(如图1所示)的电阻降低,需要使铜互连结构105具有较大的晶粒尺寸。在形成如图1所示的铜互连结构时,一种提高铜晶粒尺寸的方法是:在形成填充满开口的铜材料层之后,采用热退火使铜材料层的晶粒生长,以形成新的晶粒结构,且所述新的晶粒结构的晶粒尺寸增大。
然而,随着半导体器件的集成度提高,半导体器件的尺寸随之缩小,因此,用于形成铜材料层的开口宽度尺寸也较小,则形成于开口内的铜材料层厚度较小。由于所述铜材料层的厚度较小,使得在热退火的过程中,铜晶粒的生长受到了抑制,即使经过热退火工艺,铜晶粒的尺寸增长也有限,则所述铜互连结构105电阻降低有限。
为了解决上述问题,本发明提出一种电互连结构的形成方法。其中,在衬底表面形成具有第一晶粒结构的导电膜,所述第一晶粒结构具有第一晶粒尺寸,而所述导电膜的第一厚度大于第一晶粒尺寸,因此,所述导电膜材料的晶粒具有足够生长的空间,能够在退火工艺之后,使导电膜材料的晶格重排列并呈第二晶粒结构排布,而所述第二晶粒结构具有第二晶粒尺寸,所述第二晶粒尺寸大于第一晶粒尺寸,从而使所形成的导电膜具有较低的电阻,以所述导电膜形成的导电插塞和电互连线具有优良的电性能。其次,刻蚀所述导电膜形成导电层,在所述导电层内形成凹槽,位于所述凹槽侧壁的部分导电层形成导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层形成电互连线,即所述导电插塞和电互连线均由导电膜形成,无需使导电插塞和电互连线的形成工艺分开进行,使得形成所述电互连结构的工艺简单。再次,由于所述导电膜用于形成电互连线、以及位于电互连线表面的导电插塞,而且所述导电插塞的高度和电互连线的厚度和较大,因此即使所述导电膜的第一厚度较大,也无需在形成导电层之前对所述导电膜进行过多减薄,使得形成电互连结构的工艺易于操作,且所形成的电互连结构的形貌良好。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图2至图10是本发明实施例的电互连结构的形成过程的剖面结示意图。
请参考图2,提供衬底200。
本实施例中,所述衬底200包括:半导体基底210、位于半导体基底210表面的第一介质层211、位于第一介质层211内的导电结构212,所述导电结构212的顶部表面与第一介质层211表面齐平。
所述半导体基底210包括硅衬底、硅锗衬底、碳化硅衬底、绝缘体上硅衬底、绝缘体上锗衬底、玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)。
所述半导体基底210表面能够形成半导体器件,所述导电结构212用于电连接所述半导体器件,以构成半导体器件电路,所述第一介质层211用于电隔离所述半导体器件和导电结构212。
所述导电结构212能够由平行于衬底表面的电互连线、垂直于衬底表面的导电插塞中的一种或多种构成,所述衬底200内的导电结构212的数量至少为1个。本实施例的图3示出了4个相邻且分立的导电结构212,本实施例中,所述衬底200表面暴露出的导电结构212为导电插塞,后续所形成的电互连线用于使各导电结构212相互电连接,并通过后续形成于电互连线表面的导电插塞与其他电路连接。本实施例中,所述第一导电层212的材料为铜;在其他实施例中,所述第一导电层212还能够采用其他导电材料,例如钨或铝。
在另一实施例中,所述衬底为半导体基底,所述半导体基底内形成有导电结构,所述导电结构的表面与半导体基底的表面齐平,所述导电结构为导电插塞,则所述导电结构即硅通孔结构(TSV,Through Silicon Via)。
所述第一介质层211的材料为SiO2、SiN、SiON、SiCOH或低k材料(例如多孔介质材料)。其中,当所述第一介质层211的材料为低k材料时,所述第一介质层211的电隔离性能更佳,且寄生电容、漏电流等不良问题减少。此外,相邻第一导电层212之间的第一介质层211内还能够形成空隙,所述空隙能够进一步提高第一介质层211在第一导电层212之间的电隔离能力。
请参考图3,在衬底200表面形成导电膜201,所述导电膜201材料的晶格呈第一晶粒结构排布,单个完整的第一晶粒结构具有第一晶粒尺寸L1,所述导电膜201具有第一厚度H1,所述第一厚度H1大于第一晶粒尺寸L1。
在本实施例中,在形成所述导电膜201之前,在衬底200表面形成第一阻挡膜202,所述导电膜201形成于所述第一阻挡层202表面。所述第一阻挡膜202能够用于阻挡导电膜201的材料向第一介质层211内扩散,还能够在以电镀工艺形成所述导电膜201时,作为种子层(seed layer)生长所述导电膜201。所述第一阻挡膜202的材料为钽(Ta)和氮化钽(TaN)的组合、镧(Ru)、铜锰合金(CuMn)或钴(Co)。
本实施例中,所述导电膜201的材料为铜,由于铜具有优异的导电能力好,以铜材料能够形成性能良好稳定的电互连线和导电插塞。本实施例中,所述导电膜201的形成工艺为铜电镀工艺(ECP);在所述铜电镀工艺中,由于所述第一阻挡膜202能够导电,因此所述第一阻挡膜202能够作为种子层,所述导电膜201形成于所述第一阻挡膜202表面。
本实施例中,所述导电膜201的第一厚度H1大于2000埃,由于所述导电膜201的第一厚度H1较厚,且大于所述导电膜201材料的第一晶粒尺寸,因此在后续的退火工艺中,所述导电膜201材料的晶粒具有足够的生长空间,从而在退火工艺之后,能够使导电膜201材料的晶粒尺寸增大,且所述晶粒尺寸的增长不会因导电膜201厚度薄而受到抑制。由于导电膜201材料的晶粒尺寸越大,所述导电膜201的电阻越小,以所述导电膜形成的电互连线和导电插塞的电性能越优良。
请参考图4,采用退火工艺使所述导电膜201材料的晶粒尺寸增大,使导电膜201材料的晶格呈第二晶粒结构排布,单个完整的第二晶粒结构具有第二晶粒尺寸L2,所述第一厚度H1大于或等于第二晶粒尺寸L2。
所述退火工艺的参数包括:温度为200摄氏度~450摄氏度,时间为5分钟~30分钟。
本实施例中,所述导电膜201的材料为铜,所述退火工艺能够使所述铜材料的晶粒长大,即铜材料的晶格得到重新排布,以形成第二晶粒结构,而单个完整的第二晶粒结构具有第二晶粒尺寸,以此获得电阻更低的导电膜201。而且,由于所述的导电膜201的厚度较厚,因此所述铜材料的晶粒生长不会受到抑制,从而能够在退火工艺之后,能够使导电膜201材料的晶粒尺寸增长到第二晶粒尺寸,后续以所述导电膜201形成的电互连线和导电插塞电阻较低、性能更佳。
在所述退火工艺之后,所述导电膜201的第二晶粒尺寸仍旧小于或等于导电膜201的第一厚度H1,即所述导电膜201的第一厚度H1具有足够导电膜201的铜材料增长晶粒尺寸的空间,有利于使导电膜201的电阻降低。本实施例中,所述导电膜201的第二晶粒尺寸等于导电膜201的第一厚度H1,后续刻蚀导电膜201以形成导电层之后,单个导电层能够以一个铜材料的晶粒构成,使得以所述导电层形成的电互连线和导电插塞具有最佳的导电性能。
在一实施例中,在所述退火工艺之后,减薄所述导电膜201的部分厚度,使所述导电膜具有第二厚度,而所述第二厚度即后续所形成的导电插塞高度和电互连线厚度的总和,因此所述导电膜201需要减薄的厚度无需过大,使得减薄所述导电膜201的工艺简化、且工艺时间缩短,还能够减少对导电膜201表面均匀性或形貌的破坏。由于在减薄所述导电膜201之后,所述导电膜201材料的晶格依旧呈第二晶粒结构排布,因此即使经过减薄,所述导电膜201的厚度会小于或等于第二晶粒尺寸,然而由于所述导电膜201材料的晶格排布未发生变化,所述导电膜201依旧具有较低的电阻率。
请参考图5和图6,图6是图5沿AA1方向的剖面结示意图,刻蚀部分导电膜201(如图4所示)直至暴露出衬底200表面为止,形成导电层203。
通过刻蚀所述导电膜201,能够在衬底200表面形成若干分立的导电层203;其中,每一导电层203用于形成一条电互连线、以及位于该电互连线顶部表面的导电插塞。本实施例中,经过退火工艺之后,导电膜201材料的晶粒尺寸增大到第二晶粒尺寸,且导电膜201的第一厚度H1大于或等于所述第二晶粒尺寸L2,因此能够使刻蚀形成的导电层203由一个铜晶粒构成,使得由所述导电层203的电阻较低,所形成的电互连线和导电插塞的性能良好。本实施例中,所述导电层203由一个铜晶粒构成,即所述导电层203的厚度等于第二晶粒尺寸L2。
所述导电层203的形成工艺包括:在所述导电膜201表面形成第一掩膜,所述第一掩膜定义了后续所需形成的电互连线平行于衬底200表面方向的图形;以所述第一掩膜为掩膜,采用各向异性的干法刻蚀工艺刻蚀所述导电膜201,直至暴露出衬底200表面为止,形成导电层203;在形成导电层203之后,去除所述第一掩膜。
本实施例中,所述第一掩膜包括:位于导电膜201表面的第一抗反射层、位于第一抗反射层表面的第一掩膜层、以及位于第一掩膜层表面的第一光刻胶层。
所述第一光刻胶层以旋涂、以及旋涂之后的曝光工艺形成。所述第一抗反射层的材料为无定形碳或底层抗反射材料,用于防止曝光光线在导电膜201表面发生漫反射。所述第一掩膜层的材料为氧化硅或氮氧化硅,所述第一掩膜层的材料的硬度和图形稳定性均高于第一光刻胶层,由于所述导电膜201的厚度较大,因此刻蚀所述导电膜201的时间较长,因此需要所述第一掩膜层来维持刻蚀图形的稳定,以避免因第一光刻胶层被刻蚀消除而导致形成的导电层203形貌不佳、尺寸不精确等问题;而且,所述第一掩膜层还能够用于粘合第一光刻胶层和第一抗反射层,避免所述第一光刻胶层发生剥离。
所述刻蚀形成导电层203的各向异性的干法刻蚀工艺的参数包括:刻蚀气体包括氢气,温度10摄氏度~40摄氏度,气压5毫托~100毫托,偏置功率为100瓦~1000瓦。本实施例中,由于导电膜201和衬底200之间还具有第一阻挡膜202,因此在刻蚀所述导电膜201之后,继续刻蚀所述第一阻挡膜202,以形成第一阻挡层202a
所述刻蚀工艺通过在低于室温的环境下,以氢气的等离子体进行轰击来实现刻蚀。由于该刻蚀工艺依靠氢气等离子体进行物理轰击,因此能够削弱刻蚀气体与第一阻挡膜202和导电膜201之间化学反应速率的差异,能够使刻蚀形成的第一阻挡层202a和第一导电层201a的侧壁表面平坦。
请参考图7,刻蚀部分导电层203,在所述导电层203内形成凹槽204,所述凹槽204的深度小于第一厚度H1(如图4所示),构成所述凹槽204侧壁的部分导电层203作为导电插塞203a,位于所述导电插塞203a底部和凹槽204底部的部分导电层203作为电互连线203b,所述电互连线203b垂直于衬底200表面方向的尺寸A1小于所述第二晶粒尺寸L2,所述导电插塞203a平行于衬底200表面方向的尺寸A2小于所述第二晶粒尺寸L2。
所述导电插塞203a和电互连线203b通过刻蚀所述导电层203形成,即所述导电插塞203a和电互连线203b同时形成,因此,形成所述导电插塞203a和电互连线203b的工艺简单。所述电互连线203b用于互连若干位于第一介质层211内的第一导电层212,本实施例中,所述电互连线203b用于互连2个相邻且分立的第一导电层212。所述导电插塞203a用于使所述电互连线203b与后续形成与第二介质层表面的导电结构或半导体器件电互连。
在本实施例中,所述导电层203由一个铜晶粒构成,而所述铜晶粒具有第二晶粒结构,单个完整的第二晶粒结构具有较大的第二晶粒尺寸L2,在形成导电插塞203a和电互连线203b时,由于导电层203材料的晶格排布未发生变化,依旧呈第二晶粒结构排布,因此所述导电层203的材料依旧具有良好的电性能。
而且,由于所述导电插塞203a和电互连线203b通过刻蚀导电层203形成,因此使电互连线203b垂直于衬底200表面方向的尺寸A1、以及导电插塞203a平行于衬底200表面方向的尺寸A2小于所述第二晶粒尺寸L2,即所形成的导电插塞203a和电互连线203b的尺寸较小,有利于半导体器件的集成化和微型化。
所述形成于同一电互连线203b表面的导电插塞203a的数量至少为1个,在所述导电层203内形成的凹槽204数量至少为1个。本实施例中,在导电层203内形成1个凹槽204,所述电互连线203b表面形成2个导电插塞203a,所述电互连线203b与所述导电插塞203a的剖面构成“U”形结构。在其他实施例中,还能够在导电层203内形成若干平行排列的凹槽,而相邻凹槽之间的部分导电层也能够作为导电插塞203a。
形成所述凹槽204的刻蚀工艺包括:在导电层203部分表面形成第二掩膜,所述第二掩膜定义了所需形成的导电插塞203a平行于衬底200表面方向的图形;以所述第二掩膜为掩膜,采用各向异性的干法刻蚀工艺刻蚀所述导电层203,在导电层203内形成凹槽204;在形成凹槽204后,去除所述第二掩膜。
所述第二掩膜包括:位于导电层203表面的第二抗反射层、位于第二抗反射层表面的第二掩膜层、以及位于第二掩膜层表面的第二光刻胶层。所述第二抗反射层的材料为无定形碳或底层抗反射材料,所述第二掩膜层的材料为氧化硅或氮氧化硅。
所述刻蚀形成凹槽204的各向异性的干法刻蚀工艺的参数包括:刻蚀气体包括氢气,温度10摄氏度~40摄氏度,气压5毫托~100毫托,偏置功率为100瓦~1000瓦。
请参考图8,在所述导电层203的侧壁和底部表面、以及凹槽204的侧壁和底部表面形成第一阻挡材料层205a。
本实施例中,所述第一阻挡材料层205a与后续形成的第二阻挡材料层共同构成第二阻挡层,用于防止导电层203内的导电材料向后续形成的第二介质层内扩散。在一实施例中,还能够仅形成所述第一阻挡材料层205a作为第二阻挡层,而不形成后续的第二阻挡材料层。
本实施例中,所述第一阻挡材料层205a的形成工艺为选择性沉积工艺在所述导电层203的侧壁和底部表面、以及凹槽204的侧壁和底部表面,所述第一阻挡材料层205a的材料为CoWP或Co。所述选择性沉积工艺能够仅在导电材料表面形成第一阻挡材料层205a,使所述第一介质层211表面不会形成所述第一阻挡材料层205a,因此在所述选择性沉积工艺之后,无需为了暴露第一介质层211而进行刻蚀。
在一实施例中,所述第一阻挡材料层205a的材料为CoWP,形成所述第一阻挡材料层205a的选择性沉积工艺为选择性化学镀工艺(Selective Electroless Plating)。所述选择性化学镀工艺的参数包括:沉积液包括氧化剂、还原剂和碱性溶液,所述碱性溶液的PH值为8.9~9,温度为20摄氏度~90摄氏度。当所述第一阻挡材料层205a的材料为CoWP时,所述氧化剂包括H3P(W3O10)4和CoSO4·6H2O,所述还原剂包括NaH2PO2,所述NaH2PO2的浓度为0.23摩尔/升~0.25摩尔/升,所述碱性溶液为KOH溶液。
在另一实施例中,当所述第一阻挡材料层205a的材料为CuAl、CuSi、CuAlSi或CuMn时,形成所述第一阻挡材料层205a的工艺为选择性化学气相沉积工艺(Selective CVD)。
请参考图9,在形成所述第一阻挡材料层205a之后,在所述导电层203的侧壁和凹槽204侧壁形成第二阻挡材料层205b,所述第二阻挡材料层205b和第一阻挡材料层205a构成第二阻挡层205。
由于所述第一阻挡材料层205a的阻挡能力有限,在本实施例中,还需要形成第二阻挡材料层205b以进一步防止导电层203的材料向外扩散。
所述第二阻挡材料层205b的材料为钽和氮化钽的组合,所述第二阻挡材料层205b的形成工艺包括:在衬底200表面、导电层203表面和凹槽204的侧壁和底部表面沉积阻挡膜;回刻蚀所述阻挡膜直至暴露出衬底200表面为止。其中,形成阻挡膜的工艺为化学气相沉积工艺;所述回刻蚀工艺为各向异性的干法刻蚀工艺,在去除第一介质层211表面的阻挡膜的同时,位于凹槽204底部表面和导电插塞203a顶部表面的部分阻挡膜也相应被去除,所述第一阻挡材料层205a能够在所述回刻蚀工艺中保护凹槽204底部和导电插塞203a顶部。
在另一实施例中,所述第二阻挡材料层在所述第一阻挡材料层之前形成。在其他实施例中,还能够仅在导电层203侧壁和凹槽204侧壁表面形成第二阻挡材料层,以所述第二阻挡材料层作为第二阻挡层。
请参考图10,在衬底200表面、导电层的侧壁表面和凹槽204(如图8所示)内形成第二介质层206。
所述第二介质层206用于电隔离所述导电插塞203a和电互连线203b;本实施例中,所述第二介质层206的表面与导电插塞203a的顶部表面齐平,后续能够在第二介质层206表面形成导电结构或半导体器件,并且能够使所述导电结构或半导体器件与所述导电插塞203a电连接。
所述第二介质层206的材料包括:SiO2、SiN、SiON、SiCOH或低k材料。在本实施例中,所述第二介质层206的材料为低K介质材料,所述低K介质材料的介电系数低于2.5,当所述第二介质层206材料为低k材料时,有利于电互连线203b之间、以及导电插塞203a之间的电隔离性能。
所述第二介质层206的形成工艺包括:采用沉积工艺在衬底200表面导电层表面和凹槽204面形成第二介质膜;采用化学机械抛光工艺对所述第二介质膜进行抛光,直至暴露出导电插塞203a的顶部表面为止,形成第二介质层206。
本实施例中,所述电互连线203a之间的第二介质层206内具有空隙207,所述空隙有利于降低第二介质层206的介电系数,使所述导电层之间的电隔离能力进一步提高。形成所述第二介质薄膜的沉积工艺为等离子体增强化学气相沉积工艺(PECVD,PlasmaEnhanced CVD)。所述等离子体增强化学气相沉积工艺能够使第二介质薄膜的材料较多的堆积于靠近导电层203顶部的侧壁表面,从而使所形成的第二介质薄膜内产生空隙207。
本实施例中,由于所述电互连线203b平行于衬底表面方向的图形尺寸较大,相邻电互连线203b之间距离较小,而所述导电插塞203a通过在导电层内刻蚀形成凹槽204形成,因此相邻导电插塞203a之间的距离较大,使得相邻电互连线203b之间更容易形成空隙207,而相邻导电插塞203a之间能够被第二介质膜填充满,使得所述空隙207位于所述第二介质层206的底部。当后续在所述第二介质层206表面继续后续的工艺时,位于第二介质层206内的空隙207不易被打开,能够避免后续工艺的材料落入所述空隙207内,提高了所形成的电互连结构的稳定性。
本实施例中,在衬底表面形成具有第一晶粒尺寸的导电膜,且所述导电膜的第一厚度大于第一晶粒尺寸,因此,所述导电膜材料的晶粒具有足够生长的空间,能够在退火工艺之后,使导电膜材料的晶粒尺寸增大到第二晶粒尺寸,从而使所形成的导电膜具有较低的电阻,以所述导电膜形成的导电插塞和电互连线具有优良的电性能。其次,刻蚀所述导电膜形成导电层,在所述导电层内形成凹槽,以构成凹槽侧壁的部分导电层作为导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层作为电互连线,即所述导电插塞和电互连线均由导电膜形成,无需使导电插塞和电互连线的形成工艺分开进行,使得形成所述电互连结构的工艺简单。再次,由于所述导电膜用于形成电互连线、以及位于电互连线表面的导电插塞,而且所述导电插塞的高度和电互连线的厚度和较大,因此即使所述导电膜的第一厚度较大,也无需在形成导电层之前对所述导电膜进行过多减薄,使得形成电互连结构的工艺易于操作,且所形成的电互连结构的形貌良好。
相应的,本发明的实施例还提供一种采用上述方法所形成的电互连结构,请继续参考图9,包括:衬底200;位于部分衬底200表面的导电层,所述导电层的具有第一厚度,所述导电层的材料具有第二晶粒尺寸;位于所述导电层内的凹槽(未示出),所述凹槽的深度小于第一厚度,位于所述凹槽侧壁的部分导电层作为导电插塞203b,位于所述导电插塞203b底部和凹槽底部的部分导电层作为电互连线203b,所述电互连线203a垂直于衬底200表面方向的尺寸和所述导电插塞203a平行于衬底200表面方向的尺寸小于所述第二晶粒尺寸;位于衬底200表面和凹槽内的第二介质层206。
本实施例中,所述导电层内具有凹槽,位于所述凹槽侧壁的部分导电层作为导电插塞,位于所述导电插塞底部和第一凹槽底部的部分导电层作为电互连线。由于所述电互连线垂直于衬底表面方向的尺寸、以及所述导电插塞平行于衬底表面方向的尺寸均小于所述第二晶粒尺寸,即所述导电层材料的第二晶粒尺寸较大,因此所述导电层的电阻较低,使所述电互联结构的性能优良。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (20)
1.一种电互连结构的形成方法,其特征在于,包括:
提供衬底;
在衬底表面形成导电膜,所述导电膜材料的晶格呈第一晶粒结构排布,单个完整的第一晶粒结构具有第一晶粒尺寸,所述导电膜具有第一厚度,所述第一厚度大于第一晶粒尺寸;
采用退火工艺使所述导电膜材料的晶粒尺寸增大,使导电膜材料的晶格呈第二晶粒结构排布,单个完整的第二晶粒结构具有第二晶粒尺寸,所述第二晶粒尺寸大于第一晶粒尺寸,所述第一厚度大于或等于第二晶粒尺寸;
刻蚀部分导电膜直至暴露出衬底表面为止,形成导电层;
刻蚀部分导电层,在所述导电层内形成凹槽,所述凹槽的深度小于第一厚度,位于所述凹槽侧壁的部分导电层形成导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层形成电互连线,所述电互连线垂直于衬底表面方向的尺寸小于所述第二晶粒尺寸,所述导电插塞平行于衬底表面方向的尺寸小于所述第二晶粒尺寸;
在衬底表面、导电层的侧壁表面和凹槽内形成第二介质层。
2.如权利要求1所述的电互连结构的形成方法,其特征在于,所述导电膜的材料为铜,所述导电膜的第一厚度大于2000埃。
3.如权利要求2所述的电互连结构的形成方法,其特征在于,所述退火工艺的参数包括:温度为200摄氏度~450摄氏度,时间为5分钟~30分钟。
4.如权利要求2所述的电互连结构的形成方法,其特征在于,形成所述导电层的刻蚀工艺包括:在所述导电膜表面形成第一掩膜,所述第一掩膜定义了所需形成的电互连线平行于衬底表面方向的图形;以所述第一掩膜为掩膜,采用各向异性的干法刻蚀工艺刻蚀所述导电膜,直至暴露出衬底表面为止,形成导电层;在形成导电层之后,去除所述第一掩膜。
5.如权利要求4所述的电互连结构的形成方法,其特征在于,所述第一掩膜包括:位于导电膜表面的第一抗反射层、位于第一抗反射层表面的第一掩膜层、以及位于第一掩膜层表面的第一光刻胶层。
6.如权利要求5所述的电互连结构的形成方法,其特征在于,所述第一抗反射层的材料为无定形碳或底层抗反射材料,所述第一掩膜层的材料为氧化硅或氮氧化硅。
7.如权利要求2所述的电互连结构的形成方法,其特征在于,形成所述凹槽的刻蚀工艺包括:在导电层部分表面形成第二掩膜,所述第二掩膜定义了所需形成的导电插塞平行于衬底表面方向的图形;以所述第二掩膜为掩膜,采用各向异性的干法刻蚀工艺刻蚀所述导电层,在导电层内形成凹槽;在形成凹槽后,去除所述第二掩膜。
8.如权利要求7所述的电互连结构的形成方法,其特征在于,所述第二掩膜包括:位于导电层表面的第二抗反射层、位于第二抗反射层表面的第二掩膜层、以及位于第二掩膜层表面的第二光刻胶层。
9.如权利要求8所述的电互连结构的形成方法,其特征在于,所述第二抗反射层的材料为无定形碳或底层抗反射材料,所述第二掩膜层的材料为氧化硅或氮氧化硅。
10.如权利要求4所述的电互连结构的形成方法,其特征在于,所述各向异性的干法刻蚀工艺的参数包括:刻蚀气体包括氢气,温度10摄氏度~40摄氏度,气压5毫托~100毫托,偏置功率为100瓦~1000瓦。
11.如权利要求2所述的电互连结构的形成方法,其特征在于,所述导电层由一个铜晶粒构成。
12.如权利要求1所述的电互连结构的形成方法,其特征在于,还包括:在所述退火工艺之后,减薄所述导电膜的部分厚度,使所述导电膜具有第二厚度。
13.如权利要求1所述的电互连结构的形成方法,其特征在于,还包括:在形成所述导电膜之前,在衬底表面形成第一阻挡层,所述导电膜形成于所述第一阻挡层表面。
14.如权利要求13所述的电互连结构的形成方法,其特征在于,所述第一阻挡层的材料为钽和氮化钽的组合、镧、铜锰合金或钴。
15.如权利要求1所述的电互连结构的形成方法,其特征在于,还包括:在形成所述凹槽之后,在所述导电层的侧壁和凹槽侧壁表面形成第二阻挡层。
16.如权利要求15所述的电互连结构的形成方法,其特征在于,所述第二阻挡层包括第一阻挡材料层,所述第一阻挡材料层的形成工艺为选择性沉积工艺在所述导电层的侧壁和底部表面、以及凹槽的侧壁和底部表面,所述第一阻挡材料层的材料为CoWP或Co。
17.如权利要求16所述的电互连结构的形成方法,其特征在于,所述第二阻挡层还包括第二阻挡材料层,所述第二阻挡材料层在形成所述第一阻挡材料层之前或之后形成,所述第二阻挡材料层形成于导电层的侧壁和凹槽侧壁,所述第二阻挡材料层的材料为钽和氮化钽的组合,所述第二阻挡材料层的形成工艺包括:在衬底表面、导电层表面和凹槽的侧壁和底部表面沉积阻挡膜;回刻蚀所述阻挡膜直至暴露出衬底表面为止。
18.如权利要求1所述的电互连结构的形成方法,其特征在于,所述第二介质层的材料为低K介质材料,所述低K介质材料的介电系数低于2.5;所述电互连线之间的第二介质层内具有空隙。
19.如权利要求1所述的电互连结构的形成方法,其特征在于,所述衬底包括:
半导体基底、位于半导体基底表面的第一介质层、位于第一介质层内的导电结构,所述导电结构的顶部表面与第一介质层表面齐平,所述电互连线位于所述导电结构的顶部表面。
20.一种采用如权利要求1的方法所形成的电互连结构,其特征在于,包括:
衬底;
位于部分衬底表面的导电层,所述导电层的具有第一厚度,所述导电层的材料具有第二晶粒尺寸;
位于所述导电层内的凹槽,所述凹槽的深度小于第一厚度,位于所述凹槽侧壁的部分导电层作为导电插塞,位于所述导电插塞底部和凹槽底部的部分导电层作为电互连线,所述电互连线垂直于衬底表面方向的尺寸和所述导电插塞平行于衬底表面方向的尺寸小于所述第二晶粒尺寸;位于衬底表面和凹槽内的第二介质层。
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EP3314643A4 (en) * | 2015-06-26 | 2019-02-27 | Intel Corporation | SELECTIVE DIELECTRIC NETWORKING FROM BELOW UP TO PREVENT CONTACTING SHORTCUTS |
EP3704737A4 (en) * | 2017-11-03 | 2021-07-07 | INTEL Corporation | TECHNIQUES FOR FORMING INTERCONNECTION HOLES AND OTHER INTERCONNECTIONS FOR INTEGRATED CIRCUIT STRUCTURES |
US11139385B2 (en) * | 2018-05-17 | 2021-10-05 | International Business Machines Corporation | Interface-less contacts to source/drain regions and gate electrode over active portion of device |
CN112309958B (zh) * | 2019-07-31 | 2023-04-07 | 长鑫存储技术有限公司 | 导电互连结构及其制备方法 |
US11189561B2 (en) * | 2019-09-18 | 2021-11-30 | International Business Machines Corporation | Placing top vias at line ends by selective growth of via mask from line cut dielectric |
CN113131711A (zh) * | 2021-03-23 | 2021-07-16 | 江西展耀微电子有限公司 | Vcm弹片及其制作方法 |
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US6242349B1 (en) * | 1998-12-09 | 2001-06-05 | Advanced Micro Devices, Inc. | Method of forming copper/copper alloy interconnection with reduced electromigration |
US6352917B1 (en) * | 2000-06-21 | 2002-03-05 | Chartered Semiconductor Manufacturing Ltd. | Reversed damascene process for multiple level metal interconnects |
CN1449015A (zh) * | 2002-04-01 | 2003-10-15 | 海力士半导体有限公司 | 在半导体装置中形成金属互连层的方法 |
CN102498560A (zh) * | 2009-09-16 | 2012-06-13 | 国际商业机器公司 | 用于窄互连开口的导电结构 |
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US9490210B2 (en) | 2016-11-08 |
CN104952786A (zh) | 2015-09-30 |
US20170033051A1 (en) | 2017-02-02 |
US20150279785A1 (en) | 2015-10-01 |
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