CN1449015A - 在半导体装置中形成金属互连层的方法 - Google Patents
在半导体装置中形成金属互连层的方法 Download PDFInfo
- Publication number
- CN1449015A CN1449015A CN02160425A CN02160425A CN1449015A CN 1449015 A CN1449015 A CN 1449015A CN 02160425 A CN02160425 A CN 02160425A CN 02160425 A CN02160425 A CN 02160425A CN 1449015 A CN1449015 A CN 1449015A
- Authority
- CN
- China
- Prior art keywords
- manufacturing process
- seed layer
- laser
- metal
- metal seed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
本发明涉及一种在半导体装置中形成金属互连层的方法,藉由该方法可透过电极电镀法连续地在具极高长宽比的双金属镶嵌图样、通道孔或沟槽中填充无空洞的金属膜。为达此任务,该方法包括下面的步骤:在半导体基板上形成一下方导体层;在该已经形成下方导体层的半导体基板上形成一层间绝缘膜;选择性地蚀刻该层间绝缘膜以形成一特定形状的开孔,透过该开孔可曝露出该下方导体层;沿着已经形成的具特定形状的开孔的梯状构造形成一金属晶种层;藉由一激光制造工艺回流该金属晶种层以形成一厚度均匀的金属晶种层;对该金属晶种层执行氢气还原退火制造工艺;以及藉由电极电镀法在该金属晶种层之上形成一金属膜。
Description
技术领域
本发明一般涉及一种在半导体装置中形成金属互连层的方法。更明确地说,该方法涉及一种在半导体装置中形成金属互连层的方法,而藉此半导体装置,可以激光处理金属晶种层,并且利用电极电镀法形成一金属膜。
背景技术
电镀法包括无电极电镀法及电极电镀法。无电极电镀法的优点为能够取得极佳的隙缝填充特征,而且即使在长宽比极高的线状结构中仍然能够高速成长。不过,由于晶粒非常小,所以此方法具有对于电迁徙(后面将称为EM)的容限度不足的缺点;而且由于复杂的化学反应,所以该项制造工艺亦非常难以控制。相反地,电极电镀法,成长速度更高、化学反应非常简单、容易操控、晶粒大、所取得的薄膜品质极佳,因此对于EM的容限度亦非常好。不过,电极电镀法的缺点则是必须要有晶种层。
利用电极电镀法可以电气能量在金属或非金属装置中形成另一种金属薄膜。经由外部的电气能量,可让电解构件发生物理变化或化学变化。进行电解作用时,电解单元包括由阳极及阴极所构成的两片电极,以及介于该两片电极之间的电解液。换言之,对金属进行电极电镀是利用欲电镀金属的熔融溶液中所含的导体材料表面来进行。该导体材料表面会与外部的电源供应器产生电气连接。因此,电流便会经由该导体材料表面流进该溶液中。如此一来,金属离子便会与电子发生反应变成金属。根据此原理便可进行沉积。
不过,在利用上面的电极电镀法形成铜线的制造工艺中,希望能够非常均匀地沉积该晶种层。近来常用的晶种层沉积方法是采用物理气相沉积法。在利用此方法形成铜线的方法中,会利用物理气相沉积法形成一铜质的反扩散势垒层以及一铜质的晶种层。接着便会利用电极电镀法于其上形成一铜质膜,从而覆盖住通道或沟槽。该项形成铜线的方法的最后一道步骤便是进行化学机械研磨制造工艺。不过,在使用物理气相沉积法以形成铜质晶种层的制造工艺中,可能会因为层覆盖的品质不佳,而在具有非常高的长宽比的通道或沟槽中产生突出部分;而且也可能会因为沉积时产生不连续的点,导致在后面进行铜的电极电镀制造工艺时会在通道或沟槽中形成空洞。为解决该些问题,已经有人着手研究利用化学气相沉积法来形成铜质晶种层。不过,化学气相沉积法则具有黏着力不佳、不稳定、成本高以及其它类似的缺点。
发明内容
本发明是设计以解决上面的问题,而本发明的其中一项任务便是提供一种在半导体装置中形成金属互连层的方法,藉此半导体装置,可透过电极电镀法连续地在具极高长宽比的双金属镶嵌图样、通道孔或沟槽中填充无空洞的金属膜。
为达到上面的任务,根据本发明在半导体装置中形成金属互连层的方法,其特征为,该方法包括下面的步骤:在半导体基板上形成一下方导体层;在该已经形成下方导体层的半导体基板上形成一层间绝缘膜;选择性地蚀刻该层间绝缘膜以形成一特定形状的开孔,透过该开孔可曝露出该下方导体层;沿着已经形成的具特定形状的开孔的梯状构造,形成一金属晶种层;透过激光制造工艺回流该金属晶种层,形成一厚度均匀的金属晶种层;对该金属晶种层进行氢气还原退火制造工艺;以及透过电极电镀法在该金属晶种层之上形成一金属膜。
该激光制造工艺可以氮或氦作为激光光源。
优选地,该激光制造工艺照射激光束时的能量强度介于1至5mJ/cm2之间,而所施加的电压则介于1至20KV之间。
该激光制造工艺包括以下面的方式来照射激光束:移动该半导体基板,以固定的激光光源对其进行扫描;或移动激光光源对固定的半导体基板进行扫描。
该激光制造工艺包括以下面的方式来照射激光束:利用反射镜反射由激光发射装置所发出的激光,并且利用聚焦控制构件对该激光束进行聚焦,以便控制能量强度。
该激光制造工艺包括以下面的方式来照射激光束:在聚焦控制装置及该半导体基板之间放置一狭缝,并且控制该聚焦控制装置所发出的激光束强度。
金属晶种层可由下面的材料所构成:铜(Cu)、镍(Ni)、钼(Mo)、铂(Pt)、钛(Ti)或铝(Al)。
优选地,所形成的金属晶种层厚度介于50至2500之间。
氢气还原退火制造工艺可利用氢气或混合氢气(其中含有特定浓度的氩气(Ar)或氮气(N2)),于室温至350℃之间进行1分钟至3个小时,以便形成相当粗糙的金属晶种层晶粒尺寸,并且移除形成于该金属晶种层表面上的原生氧化物膜。
该方法进一步包括下面的步骤:在该半导体基板上形成一扩散势垒层,在形成该金属晶种层之前会在该半导体基板中形成开孔。
该方法进一步包括在形成该金属膜之后运用电极电镀法进行下面的步骤:对该金属膜进行氢气还原退火制造工艺;以及对其中已经形成该金属膜的半导体基板进行化学机械研磨制造工艺。
该金属膜是铜质(Cu)膜。
该特定形状的开孔是双金属镶嵌图样、通道孔或沟槽。
附图说明
现在将配合附图于下面的说明中解释本发明前述的观点及其它特点,其中:
图1至图6所示的是半导体装置的剖面图,其是用以解释根据本发明的优选具体实施例在该半导体装置中形成一金属互连层的方法;以及
图7及图8所示的是半导体装置的剖面图,其中已经形成分别能够运用在本发明中的双金属镶嵌图样及通道孔。
具体实施方式
现在将透过优选的具体实施例,配合附图,详细地对本发明作说明,其中,相同的组件符号代表相同或相似的部件。
图1至图6所示的是半导体装置的剖面图,其是用以解释根据本发明的优选具体实施例在该半导体装置中形成一金属互连层的方法。
现在参考图1,在半导体基板100之上形成一下方导体层102,本发明将会对该基板进行数种用以形成半导体装置的制造工艺。接着,便会形成一层间绝缘膜104。此时,优选地能够利用低介电常数的绝缘材料来形成该层间绝缘膜104,举例来说,PSG(硅化磷玻璃)、USG(无掺杂的硅化物玻璃)、PE-TEOS(等离子增强-四乙基正硅酸酯)或HDP(高密度等离子)氧化物。接着,便会在该层间绝缘膜104之中形成欲连接至该下方导体层102的双金属镶嵌图样106。本领域的技术人员都非常了解用以形成该双金属镶嵌图样106的方法。因此,此处将不再对该方法作解释。同时,虽然前面所述的是先将双金属镶嵌图样106形成于该层间绝缘膜104之中,然后再进行后面的制造工艺,不过本发明亦可运用于如图7所示的方法,其中会在该下方导体层202之上形成一蚀刻阻止层204、一第一层间绝缘膜206以及一第二层间绝缘膜210;在第一层间绝缘膜206以及第二层间绝缘膜210之间形成一埋植硬掩模层208;然后在该半导体基板200中形成一双金属镶嵌图样214,其中,在此基板中,会于该第二层间绝缘膜210之上形成一上方硬掩模层212。同样地,本发明亦可运用于如图8所示的方法,其中会在层间绝缘膜304之中形成连接至下方导体层302且具有高长宽比的通道孔或沟槽306。因此,当形成该双金属镶嵌图样106之后,便会曝露出该下方导体层102。为移除该下方导体层102表面上的原生氧化物膜或污染物,必须进行清洁制造工艺。此时,视该下方导体层102的类型而定,该项清洁制造工艺可以利用高频(RF)等离子制造工艺或反应式清洁制造工艺。举例来说,如果该下方导体层102是由钨(W)、铝(Al)等材料所构成的话,便可使用HF等离子。如果该下方导体层102是由铜(Cu)所构成的话,则可使用反应式清洁制造工艺。
参考图2,图中已经沿着形成该双金属镶嵌图样106的半导体基板100的梯状构造形成一扩散势垒层108。此时,优选地可以下面各种材料中至少其中一种构成该扩散势垒层108:物理气相沉积(后面将称为PVD)TiN膜、化学气相沉积(后面将称为CVD)TiN膜、金属有机化学气相沉积TiN膜、PVD Ta膜、PVD TaN膜、CVD Ta膜、CVD TaN膜、CVD WN膜、CVD TiAlN膜、CVD TiSiN膜以及CVD TaSiN膜。
其次,会沿着该扩散势垒层108的梯状构造形成一金属晶种层110。此时,该金属晶种层110可以PVD、CVD或原子层沉积(ALD)方法利用下面的材料构成:铜(Cu)、镍(Ni)、钼(Mo)、铂(Pt)、钛(Ti)、铝(Al)。同样地,所形成的金属晶种层110的厚度约介于50至2500之间。不过,沉积该金属晶种层110之后,会在具有非常高的长宽比的深双金属镶嵌图样106的入口部分处产生突出部分(参看图2中的「A」部分),或是产生不连续的沉积点。不论是在具有非常高的长宽比的双金属镶嵌图样106的入口部分处所产生的突出部分或是不连续的沉积点都会损及后面的电极电镀制造工艺的隙缝填充特征。
参考图3,当形成该金属晶种层110之后,为移除该突出部分或不连续的沉积点,并且能够形成厚度均匀的金属晶种层110,必须进行激光制造工艺112。该激光制造工艺112意味着以激光照射该金属晶种层110以回流该金属晶种层110。
本发明所使用的激光包括曝光制造工艺中所使用的短波长KrF或ArF准分子激光。不过,当该准分子激光的能量强度极高、并且是短波长,而且照射于狭幅区域中时,便很难使用该准分子激光回流该金属晶种层110。因此,为使用此短波长激光,必须降低其能量强度,并且必须尽可能地控制该激光束以扩大其所照射的区域。同样地,可使用波长区长于该准分子激光的氮气或氦气作为光源,以该激光对薄膜品质相当差的金属晶种层110进行退火。现在将详细地说明上面的方法。
第一种方法,当使用具短波长的KrF、ArF准分子激光时,先将该激光束的能量强度控制在约1至5mJ/cm2之间,使得其强度低于现有的曝光制造工艺。同样地,可使用约介于1kV至20KV之间的施加电压。
第二种方法,在反射由激光发射装置所发出的激光束之后,以让该聚焦控制装置的焦点呈现模糊的方式,将该激光束照射在晶片之上。
第三种方法,于聚焦控制装置所聚焦的激光所照射的晶片表面的中心插入一狭缝之类的构造,以降低该激光束的强度。
第四种方法,因为该激光束的尺寸很小,所以无法以该激光束照射整个晶片。因此必须以下面的方式来照射该晶片,方能进行退火制造工艺。也就是,移动该晶片,以固定的激光对其进行扫描;或移动该激光对固定的晶片进行扫描。
第五种方法,以氮或氦等作为能量强度相当低的激光光源来进行该项激光制造工艺。即使以氮或氦作为激光光源,仍然可利用第一种至第四种方法来进行该项激光制造工艺。
参考图4,以该激光制造工艺112回流该金属晶种层110。利用回流便可移除于该双金属镶嵌图样106的入口部分处所产生的突出部分或是不连续的沉积点,因而便可获得厚度均匀的金属晶种层110。当金属晶种层110的厚度均匀时,便能够避免在后面的电极电镀制造工艺中造成不均匀的覆盖结构。因此,便能够以不会形成空洞的方式来填充该金属膜。
此时,该金属可以下面的机制进行扩散:体积扩散、表面扩散、蒸发凝结、黏稠流动等。回流温度通常必须配合材料的熔点。如果表面非常干净,原子便能够在该表面自由地移动。因此,类似铝(Al)之类的金属即使在非常低的温度下亦可利用表面扩散的方式进行回流。不过,对熔点极高的铜(Cu)来说,便无法在非常低的制造工艺温度下扩散。不过,如果使用本发明的激光制造工艺112的话,便能够在远低于Cu的熔点的温度下(例如400℃以下)对Cu进行回流。所以,使用本发明的激光制造工艺112便不必担心会损及层间绝缘膜,亦不必担心会在该半导体基板所形成的晶体管装置(未显示)中发生不必要的杂质横向扩散、热电子效应等问题。
之后,为形成相当粗糙的金属晶种层110晶粒尺寸,并且移除形成于该金属晶种层110表面上的原生氧化物层,必须进行氢气还原退火制造工艺。此时,优选地该项氢气还原退火制造工艺可利用氢气或混合氢气(其中含有特定浓度(95%以下)的氩气(Ar)或氮气(N2)),于室温至350℃之间进行1分钟至3个小时。
参考图5,利用电镀法在厚度均匀的金属晶种层110a之上形成一金属膜114,因此可以该金属膜114完全覆盖住该双金属镶嵌图样106。此时,该金属膜114优选地由铜(Cu)膜所构成。接着,为改变该金属膜114的晶粒形状,必须进行氢气还原退火制造工艺。此时,优选地该项氢气还原退火制造工艺可利用氢气或混合氢气(其中含有特定浓度(95%以下)的氩气(Ar)或氮气(N2),于室温至350℃之间进行1分钟至3个小时。
参考图6,可利用化学机械研磨处理对已经利用电极电镀法于其中形成该金属膜114的半导体基板100进行平整处理。此时,优选地能够持续地进行该化学机械研磨处理直到曝露出层间绝缘膜104为止。
如上述,即使用以连接该下方导体层及该上方导体层的双金属镶嵌图样、通道孔或沟槽具极高的长宽比,根据本发明亦能够填充于其中填充无空洞的金属膜。明确地说,在利用物理气相沉积法形成铜质的金属晶种层时,可能会因为层覆盖的品质不佳,而在具有非常高的长宽比的通道孔或沟槽中产生突出部分;而且也可能会因为沉积时产生不连续的点,导致在后面进行铜的电极电镀制造工艺时会在通道孔或沟槽中形成空洞。不过,本发明的优点便在于,即使利用物理气相沉积法形成该铜质的金属晶种层时,其层覆盖的品质不佳,其亦能够连续地形成经过填充的铜线,却又不会出现空洞。
另外,根据本发明,其显着的效果在于可使用激光制造工艺对金属晶种层进行退火制造工艺而不必担心会损及层间绝缘膜,亦不必担心会在该晶体管中发生不必要的杂质横向扩散或热电子效应等问题。
本文所提到的结构是各层相邻排列。不过,应该注意的是,亦可在两层之间插入一第三层。
至此,已经配合特殊的应用,参考特殊的具体实施例对本发明作说明。本领域的技术人员且详阅过本发明的内容的人士将可了解在其范畴内的其它修正及应用。
所以,随附的权利要求范围希望能够涵盖本发明范畴中的所有应用、修正及具体实施例。
Claims (14)
1.一种在半导体装置中形成金属互连层的方法,其包括下面的步骤:
在半导体基板上形成一下方导体层;
在该已经形成下方导体层的半导体基板上形成一层间绝缘膜;
选择性地蚀刻该层间绝缘膜以形成一特定形状的开孔,透过该开孔可曝露出该下方导体层;
沿着已经形成的具有特定形状的开孔的梯状构造形成一金属晶种层;
藉由激光制造工艺回流该金属晶种层形成一厚度均匀的金属晶种层;
对该金属晶种层进行氢气还原退火制造工艺;以及
藉由电镀法在该金属晶种层之上形成一金属膜。
2.如权利要求1所述的方法,其中该激光制造工艺是以氮或氦作为激光光源。
3.如权利要求1所述的方法,其中该激光制造工艺包括:以介于1至5mJ/cm2之间的能量强度以及介于1至20KV之间的施加电压来照射该激光束。
4.如权利要求1所述的方法,其中该激光制造工艺包括以下面的方式来照射该激光束:移动该半导体基板以固定的激光光源对其进行扫描,或移动该激光光源对固定的半导体基板进行扫描。
5.如权利要求1所述的方法,其中该激光制造工艺包括藉由反射镜反射由激光发射装置所发出的激光并且利用聚焦控制构件对该激光束进行聚焦以便控制能量强度来照射该激光束。
6.如权利要求1所述的方法,其中该激光制造工艺包括在聚焦控制装置及该半导体基板之间放置一狭缝并且控制该聚焦控制装置所发出的激光束强度来照射该激光束。
7.如权利要求1所述的方法,其中该激光制造工艺使用短波长的ArF或KrF准分子激光来执行。
8.如权利要求1所述的方法,其中该金属晶种层可由下面的材料所形成:铜(Cu)、镍(Ni)、钼(Mo)、铂(Pt)、钛(Ti)或铝(Al)。
9.如权利要求8所述的方法,其中该金属晶种层厚度介于50至2500之间。
10.如权利要求1所述的方法,其中该氢气还原退火制造工艺可利用氢气或混合氢气(其中含有特定浓度的氩气(Ar)或氮气(N2)),于室温至350℃之间进行1分钟至3个小时,以便形成相当粗糙的金属晶种层晶粒尺寸,并且移除形成于该金属晶种层表面上的原生氧化物膜。
11.如权利要求1所述的方法,进一步包括下面的步骤:在该半导体基板上形成一扩散势垒层,在形成该金属晶种层之前会在该半导体基板中形成开孔。
12.如权利要求1所述的方法,进一步包括在形成该金属膜之后运用电极电镀法进行下面的步骤:
对该金属膜进行氢气还原退火制造工艺;以及
对其中已经形成该金属膜的半导体基板进行化学机械抛光制造工艺。
13.如权利要求1所述的方法,其中该金属膜是铜质(Cu)膜。
14.如权利要求1所述的方法,其中该特定形状的开孔是双金属镶嵌图样、通道孔或沟槽。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR17701/2002 | 2002-04-01 | ||
KR10-2002-0017701A KR100465063B1 (ko) | 2002-04-01 | 2002-04-01 | 반도체 소자의 금속배선 형성방법 |
KR17701/02 | 2002-04-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1449015A true CN1449015A (zh) | 2003-10-15 |
CN1270371C CN1270371C (zh) | 2006-08-16 |
Family
ID=28450113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021604258A Expired - Fee Related CN1270371C (zh) | 2002-04-01 | 2002-12-30 | 在半导体装置中形成金属互连层的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6720248B2 (zh) |
KR (1) | KR100465063B1 (zh) |
CN (1) | CN1270371C (zh) |
TW (1) | TWI302725B (zh) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7582557B2 (en) | 2005-10-06 | 2009-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for low resistance metal cap |
US7777344B2 (en) | 2007-04-11 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transitional interface between metal and dielectric in interconnect structures |
CN102263056A (zh) * | 2010-05-26 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | 一种金属互连方法 |
CN101736375B (zh) * | 2008-11-24 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | 电镀方法 |
CN103311174A (zh) * | 2012-03-07 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | 一种制作铜互连结构的方法 |
CN103700619A (zh) * | 2013-12-17 | 2014-04-02 | 上海交通大学 | 铜互连电镀填充方法 |
CN103855080A (zh) * | 2012-11-30 | 2014-06-11 | 格罗方德半导体公司 | 制造具有低电阻装置接触的集成电路的方法 |
CN104425444A (zh) * | 2013-08-22 | 2015-03-18 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN104952786A (zh) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | 电互连结构及其形成方法 |
CN104979276A (zh) * | 2014-04-09 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN105826244A (zh) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN106033714A (zh) * | 2015-03-10 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN115513135A (zh) * | 2022-11-17 | 2022-12-23 | 广州粤芯半导体技术有限公司 | 半导体工艺方法和半导体蚀刻设备 |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7023090B2 (en) * | 2003-01-29 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding pad and via structure design |
US7129165B2 (en) * | 2003-02-04 | 2006-10-31 | Asm Nutool, Inc. | Method and structure to improve reliability of copper interconnects |
US20050274622A1 (en) * | 2004-06-10 | 2005-12-15 | Zhi-Wen Sun | Plating chemistry and method of single-step electroplating of copper on a barrier metal |
US6958291B2 (en) * | 2003-09-04 | 2005-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect with composite barrier layers and method for fabricating the same |
US20050191858A1 (en) * | 2004-02-27 | 2005-09-01 | Akira Fukunaga | Substrate processing method and apparatus |
US7026175B2 (en) * | 2004-03-29 | 2006-04-11 | Applied Materials, Inc. | High throughput measurement of via defects in interconnects |
US7674706B2 (en) * | 2004-04-13 | 2010-03-09 | Fei Company | System for modifying small structures using localized charge transfer mechanism to remove or deposit material |
JP2005327799A (ja) * | 2004-05-12 | 2005-11-24 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
US7379185B2 (en) * | 2004-11-01 | 2008-05-27 | Applied Materials, Inc. | Evaluation of openings in a dielectric layer |
US20060093730A1 (en) * | 2004-11-03 | 2006-05-04 | Applied Materials, Inc. | Monitoring a flow distribution of an energized gas |
US7312148B2 (en) * | 2005-08-08 | 2007-12-25 | Applied Materials, Inc. | Copper barrier reflow process employing high speed optical annealing |
US20070264816A1 (en) * | 2006-05-12 | 2007-11-15 | Lavoie Adrien R | Copper alloy layer for integrated circuit interconnects |
IL188029A0 (en) * | 2007-12-10 | 2008-11-03 | Nova Measuring Instr Ltd | Optical method and system |
US8764961B2 (en) * | 2008-01-15 | 2014-07-01 | Applied Materials, Inc. | Cu surface plasma treatment to improve gapfill window |
US8278220B2 (en) * | 2008-08-08 | 2012-10-02 | Fei Company | Method to direct pattern metals on a substrate |
US8293647B2 (en) * | 2008-11-24 | 2012-10-23 | Applied Materials, Inc. | Bottom up plating by organic surface passivation and differential plating retardation |
US8310328B2 (en) * | 2010-10-07 | 2012-11-13 | Touch Micro-System Technology Corp. | Planar coil and method of making the same |
US9255339B2 (en) | 2011-09-19 | 2016-02-09 | Fei Company | Localized, in-vacuum modification of small structures |
JPWO2013047323A1 (ja) * | 2011-09-30 | 2015-03-26 | 株式会社アルバック | 半導体装置の製造方法、半導体装置 |
US8946087B2 (en) * | 2012-02-02 | 2015-02-03 | Lam Research Corporation | Electroless copper deposition |
US9865501B2 (en) | 2013-03-06 | 2018-01-09 | Lam Research Corporation | Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer |
US20160276156A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing process thereof |
US9899258B1 (en) * | 2016-09-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal liner overhang reduction and manufacturing method thereof |
US10443146B2 (en) | 2017-03-30 | 2019-10-15 | Lam Research Corporation | Monitoring surface oxide on seed layers during electroplating |
US10867905B2 (en) | 2017-11-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
US11011413B2 (en) | 2017-11-30 | 2021-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
CN109148276A (zh) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | 提高深沟槽填充能力的方法 |
KR102190975B1 (ko) | 2019-02-07 | 2020-12-14 | 용인송담대학교 산학협력단 | 체인형 콘센트 |
JP7374826B2 (ja) * | 2020-03-19 | 2023-11-07 | キオクシア株式会社 | テンプレートの製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6211034B1 (en) * | 1997-04-14 | 2001-04-03 | Texas Instruments Incorporated | Metal patterning with adhesive hardmask layer |
US6130102A (en) * | 1997-11-03 | 2000-10-10 | Motorola Inc. | Method for forming semiconductor device including a dual inlaid structure |
US6436723B1 (en) * | 1998-10-16 | 2002-08-20 | Kabushiki Kaisha Toshiba | Etching method and etching apparatus method for manufacturing semiconductor device and semiconductor device |
KR100493013B1 (ko) * | 1998-11-30 | 2005-08-01 | 삼성전자주식회사 | 반도체소자의 금속 배선층 형성방법_ |
KR100309809B1 (ko) * | 1998-12-28 | 2001-11-15 | 박종섭 | 반도체소자의구리금속배선형성방법 |
KR100283107B1 (ko) * | 1998-12-31 | 2001-04-02 | 김영환 | 반도체 소자의 구리배선 형성방법 |
KR20000056452A (ko) * | 1999-02-22 | 2000-09-15 | 윤종용 | 반도체 소자의 구리 배선 형성방법 |
US6759325B2 (en) * | 2000-05-15 | 2004-07-06 | Asm Microchemistry Oy | Sealing porous structures |
US6777327B2 (en) * | 2001-03-28 | 2004-08-17 | Sharp Laboratories Of America, Inc. | Method of barrier metal surface treatment prior to Cu deposition to improve adhesion and trench filling characteristics |
US6420189B1 (en) * | 2001-04-27 | 2002-07-16 | Advanced Micro Devices, Inc. | Superconducting damascene interconnected for integrated circuit |
US6727176B2 (en) * | 2001-11-08 | 2004-04-27 | Advanced Micro Devices, Inc. | Method of forming reliable Cu interconnects |
US6861354B2 (en) * | 2002-02-04 | 2005-03-01 | Asm Nutool Inc | Method and structure to reduce defects in integrated circuits and substrates |
-
2002
- 2002-04-01 KR KR10-2002-0017701A patent/KR100465063B1/ko not_active IP Right Cessation
- 2002-12-17 TW TW091136428A patent/TWI302725B/zh not_active IP Right Cessation
- 2002-12-23 US US10/325,845 patent/US6720248B2/en not_active Expired - Fee Related
- 2002-12-30 CN CNB021604258A patent/CN1270371C/zh not_active Expired - Fee Related
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7582557B2 (en) | 2005-10-06 | 2009-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for low resistance metal cap |
US7777344B2 (en) | 2007-04-11 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transitional interface between metal and dielectric in interconnect structures |
US8349730B2 (en) | 2007-04-11 | 2013-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transitional interface between metal and dielectric in interconnect structures |
TWI400770B (zh) * | 2007-04-11 | 2013-07-01 | Taiwan Semiconductor Mfg | 積體電路結構及其製作方法 |
CN101736375B (zh) * | 2008-11-24 | 2012-05-23 | 中芯国际集成电路制造(北京)有限公司 | 电镀方法 |
CN102263056A (zh) * | 2010-05-26 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | 一种金属互连方法 |
CN103311174A (zh) * | 2012-03-07 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | 一种制作铜互连结构的方法 |
CN103855080B (zh) * | 2012-11-30 | 2018-03-06 | 格罗方德半导体公司 | 制造具有低电阻装置接触的集成电路的方法 |
CN103855080A (zh) * | 2012-11-30 | 2014-06-11 | 格罗方德半导体公司 | 制造具有低电阻装置接触的集成电路的方法 |
CN104425444A (zh) * | 2013-08-22 | 2015-03-18 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN104425444B (zh) * | 2013-08-22 | 2018-07-20 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN103700619B (zh) * | 2013-12-17 | 2016-05-18 | 上海交通大学 | 铜互连电镀填充方法 |
CN103700619A (zh) * | 2013-12-17 | 2014-04-02 | 上海交通大学 | 铜互连电镀填充方法 |
CN104952786A (zh) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | 电互连结构及其形成方法 |
CN104952786B (zh) * | 2014-03-25 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 电互连结构及其形成方法 |
CN104979276A (zh) * | 2014-04-09 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN104979276B (zh) * | 2014-04-09 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
CN105826244A (zh) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN106033714A (zh) * | 2015-03-10 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
CN115513135A (zh) * | 2022-11-17 | 2022-12-23 | 广州粤芯半导体技术有限公司 | 半导体工艺方法和半导体蚀刻设备 |
Also Published As
Publication number | Publication date |
---|---|
TW200305254A (en) | 2003-10-16 |
KR20030078978A (ko) | 2003-10-10 |
TWI302725B (en) | 2008-11-01 |
CN1270371C (zh) | 2006-08-16 |
US20030186524A1 (en) | 2003-10-02 |
US6720248B2 (en) | 2004-04-13 |
KR100465063B1 (ko) | 2005-01-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1270371C (zh) | 在半导体装置中形成金属互连层的方法 | |
US7262132B2 (en) | Metal plating using seed film | |
US7863597B2 (en) | Resistance variable memory devices with passivating material | |
JP4734467B2 (ja) | 半導体装置の製造方法 | |
US7067348B2 (en) | Method of forming a programmable memory cell and chalcogenide structure | |
US6958296B2 (en) | CVD TiSiN barrier for copper integration | |
US20140106561A1 (en) | Graphene Barrier Layers for Interconnects and Methods for Forming the Same | |
US20020175418A1 (en) | Ultra thin, single phase, diffusion barrier for metal conductors | |
US20070054046A1 (en) | Method of forming a tantalum-containing layer from a metalorganic precursor | |
Boyd et al. | Photo-induced growth of dielectrics with excimer lamps | |
KR20010021312A (ko) | 전기도금 처리용 배리어층 | |
US20100081275A1 (en) | Method for forming cobalt nitride cap layers | |
KR100489920B1 (ko) | 통합된플러그/상호접속금속부를위해선택적cvda1을사용하는인슈트캐핑된알루미늄플러그(캡)형성방법 | |
KR20090093985A (ko) | 전기도금에 의한 콘택 로듐 구조물의 제조 및 전기도금 조성물 | |
JPH11150084A (ja) | 半導体装置および基板上への非晶質窒化硅素チタンの形成方法 | |
US20070054047A1 (en) | Method of forming a tantalum-containing layer from a metalorganic precursor | |
US7129580B1 (en) | Methods and procedures for engineering of composite conductive films by atomic layer deposition | |
EP2034517A1 (en) | Semiconductor device and semiconductor device manufacturing method | |
US20100099251A1 (en) | Method for nitridation pretreatment | |
JP2002231723A (ja) | 集積回路の製造における銅被覆のためのバリア層 | |
US6900127B2 (en) | Multilayer integrated circuit copper plateable barriers | |
KR19990013553A (ko) | 반도체 디바이스 및 반도체 디바이스 제조 공정 | |
EP1340252A2 (en) | Optimized liners for dual damascene metal wiring | |
US6797560B2 (en) | Method of manufacturing a capacitor having tantalum oxide film as an insulating film | |
US7183649B1 (en) | Methods and procedures for engineering of composite conductive films by atomic layer deposition |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060816 Termination date: 20131230 |