CN1516276A - 具有双覆盖层的半导体器件的互连及其制造方法 - Google Patents

具有双覆盖层的半导体器件的互连及其制造方法 Download PDF

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CN1516276A
CN1516276A CNA2003101247376A CN200310124737A CN1516276A CN 1516276 A CN1516276 A CN 1516276A CN A2003101247376 A CNA2003101247376 A CN A2003101247376A CN 200310124737 A CN200310124737 A CN 200310124737A CN 1516276 A CN1516276 A CN 1516276A
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interlayer dielectric
copper
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���
李敬雨
李守根
朴基澈
宋源祥
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种具有双覆盖层的半导体器件的互连及其制造方法。半导体器件的互连是一种铜金属镶嵌互连，在用化学机械抛光(CMP)加工过的铜层上形成覆盖层，该覆盖层是氮化硅层和碳化硅层的双层结构。因此，有可能在提供优良的漏电流抑制作用的同时维持碳化硅层的高刻蚀选择性和低介电常数。该互连结构包括：层间绝缘膜，其具有位于其中的成互连的形状的开口；沿开口的内壁形成的阻挡金属层；填充在阻挡金属层上方的开口的金属层，该金属层具有与层间绝缘膜的顶部表面水平的顶部表面；以及覆盖层间绝缘膜和金属层的顶部表面的覆盖层，该覆盖层是由顺序淀积的氮化硅层和碳化硅层形成的双层结构。

Description

具有双覆盖层的半导体器件的互连及其制造方法
本发明要求于2002年12月30日申请的、符合U.S.C第35条§119规定的、韩国专利文件No.2002-87245的优先权，因此将其全文作参照引用。
技术领域
本发明涉及一种在半导体器件中如线和/或通路这样的互连以及用于形成互连的方法，更具体地说，涉及一种在低介电常数层中形成的并且被覆了覆盖层的单或双金属镶嵌互连(single or dual damascene interconnection)及其形成方法。
背景技术
为了获得高速半导体器件，有必要减少栅极氧化物层的厚度和栅极的长度。然而，与互连的电阻值和层间绝缘膜的电容值成比例的RC(电阻值-电容值)延迟对于半导体器件的速度而言具有负面影响。从而，已经作出各种尝试，通过使用低电阻值的互连和低介电常数的层间绝缘膜来降低RC延迟。
按照常规，广泛地使用铝(Al)作为互连材料。然而，近年来逐渐认为对于集成电路来说铜(Cu)是更有益的。铜(Cu)的电阻系数是铝(Al)的电阻系数的一半，并因此有可能用宽度小的铜(Cu)来增加信号传输的速度。此外，由于铜(Cu)具有高度的抗电迁移能力，所以能提高半导体器件的可靠性。而且，铜(Cu)显示出低功耗并且比铝(Al)便宜。
然而，使用铜(Cu)的一个缺点是铜(Cu)很难被刻蚀和构图而得到所期望的互连。因此，用金属镶嵌工艺形成铜互连。金属镶嵌工艺包括下面常规步骤。在层间绝缘膜中形成具有所期望互连形状的开口。然后，在形成铜层以填充开口之后执行平面化工艺。通常，使用化学机械抛光(chemicalmechanical polishing，CMP)作为平面化工艺。特别是，使用双金属镶嵌工艺来形成铜(Cu)互连。双金属镶嵌工艺包括如下步骤。形成通路沟槽和布线沟槽，使得布线沟槽与通路沟槽的上部分重叠。然后，在形成铜层以填充通路沟槽和布线沟槽之后，执行平面化工艺。如本领域的技术人员所公知地，序被称为单金属镶嵌工艺。
图1示例了常规单金属镶嵌互连的截面图。参考图1，金属镶嵌互连7填充层间绝缘膜1中的开口3并且被阻挡金属层5包围着。例如氮化硅层的覆盖层9覆盖层间绝缘膜1和金属镶嵌互连7。在金属镶嵌工艺期间执行完CMP之后，在金属镶嵌互连7上淀积覆盖层9。覆盖层9应该有效地阻止铜(Cu)扩散到层间绝缘膜1中，并且覆盖层9相对于将要形成在金属镶嵌互连7上的其它层间绝缘膜具有高的刻蚀选择性。由于近年来用低介电常数例如2-4的材料作为层间绝缘膜，所以对于氮化硅的替代品的需求变得明显了。实际上，氮化硅代表性地用作覆盖层，但是它具有例如6-8的高介电常数和具有相对于低介电常数层的低刻蚀选择性。碳化硅具有例如4-5的低介电常数和相对于低介电常数层的高刻蚀选择性。因此，碳化硅是取代氮化硅作为覆盖层的合适替代品。然而，如果碳化硅用作覆盖层，那么在平面化的层间绝缘膜和覆盖层之间的界面中的漏电流变得更加难以抑制。
发明内容
本发明提供一种半导体器件的互连，其中改善了覆盖层的特性，使得覆盖层相对于低介电常数层具有高刻蚀选择性并且显示出改善了的漏电流抑制作用。
本发明还提供一种用于形成半导体器件互连的方法。
提供了金属镶嵌互连的双覆盖层、包括覆盖层的半导体器件的互连以及形成互连的方法，其中双覆盖层是由氮化硅和碳化硅形成的。
根据本发明的一个方案，提供一种半导体器件的互连。互连包括层间绝缘膜、阻挡金属层、金属层和覆盖层。层间绝缘膜具有形成于其内的开口，开口具有互连的形状。沿开口的内壁形成阻挡金属层。金属层填充阻挡金属层上方的开口并且具有与层间绝缘膜的顶部表面水平的顶部表面。覆盖层覆盖层间绝缘膜和金属层的顶部表面并且是通过连续淀积氮化硅层和碳化硅层形成的双层。
根据本发明的另一个方案，提供一种形成半导体器件互连的方法。该方法包括：(a)在衬底上形成层间绝缘膜；(b)通过刻蚀层间绝缘膜形成具有互连形状的开口；(c)在步骤(b)的最终结构上形成阻挡金属层；(d)通过在阻挡金属层上形成金属层填充开口；(e)使步骤(d)的最终结构平面化直到暴露出层间绝缘膜；以及(f)通过在步骤(e)的最终结构上连续地淀积氮化硅层和碳化硅层形成覆盖层。
如上面所描述地，当层间绝缘膜淀积在双覆盖层上并且被刻蚀以形成在双覆盖层上的另一互连的时候，通过连续淀积氮化硅层和碳化硅层形成的双层相对于层间绝缘膜具有高刻蚀选择性。同样，有可能提高在层间绝缘膜和双覆盖层之间的界面中的漏电流抑制作用。
附图说明
本发明的上述和其它目的、特征以及有益效果通过本发明优选实施例的更具体说明将更加明显，在附图中示出了这些优选实施例，所有的附图同一参考字符始终指示同一部分。附图不必按比例绘制，而是着重示例出本发明的原理。
图1是示例出常规单金属镶嵌互连的截面图；
图2至5是示例出根据本发明的一个实施例的互连和用于形成互连的方法的截面图；
图6是示例出根据本发明的另一个实施例的互连和用于形成互连的方法的截面图；
图7是常规互连和根据本发明互连的偏压热应力(bias thermal stress，BTS)特性的实验结果的示图；
图8是常规互连和根据本发明互连的耐电迁移的实验结果的示图。
具体实施方式
图2至5是示例出根据本发明的一个实施例的互连和用于形成互连的方法的截面图。下面的描述主要涉及一种铜互连，但也可以应用于所有低电阻值导电材料，例如铝(Al)、银(Ag)、金(Au)、铜(Cu)以及它们的合金。
参考图2，在衬底100上形成层间绝缘膜105。可以在衬底100和层间绝缘膜105之间插入绝缘层或导电层，例如掺杂硅、钨(W)、铝(Al)或铜(Cu)。层间绝缘膜105由绝缘膜110、115、120和125的叠层组成。绝缘膜115和125是用于形成开口的氧化物膜并且是由低介电常数材料形成的以减少RC(resistance and capacitance，电阻值和电容值)延迟，所述开口具有所期望互连的形状。例如，低介电常数材料可以是黑金刚石、氟硅酸盐玻璃(fluorine silicate glass，FSG)、SiOC、聚酰亚胺或SiLKTM。绝缘膜110和120是由碳化硅形成的并且当刻蚀绝缘膜115和125以形成开口时用作刻蚀终止层。
通过刻蚀一部分层间绝缘膜105，形成具有所期望的互连形状的开口140。图2的开口140用于双金属镶嵌互连，其中布线沟槽135形成在通路沟槽130上。在通过顺序刻蚀绝缘膜125、120、115和110形成通路沟槽130之后，通过刻蚀绝缘膜125和120形成布线沟槽135，以便布线沟槽135重叠在通路沟槽130上。可选择地，在形成通路沟槽130之前可以形成布线沟槽135。
参考图3，在清洗具有开口140的产生结构之后，在产生结构上形成阻挡金属层150。阻挡金属层150阻止用于填充开口140的材料的金属原子扩散进入层间绝缘膜105。阻挡金属层150的厚度是200～1000，优选是450。阻挡金属层150可以是钛(Ti)、钽(Ta)、钨(W)或它们的氮化物。例如，阻挡金属层150可以是TiN、TaN、WN、TaSiN、WSiN或TiSiN。可以用化学气相淀积(chemical vapor deposition，CVD)或例如溅射的物理气相淀积(physical vapor deposition，PVD)淀积阻挡金属层150。
用由铜或铜合金形成的金属层160填充开口140。通过有意或无意地使铜和少量C、Ag、Co、Ta、In、Sn、Zn、Mn、Ti、Mg、Cr、Ge、Sr、Pt、Mg、Al或Zr混合来形成铜合金。有代表性地，通过使用溅射或CVD用铜填充开口140，但可以使用包括电镀(electro plating)和化学镀(electrolessplating)的镀敷技术用铜来填充开口140。当使用镀敷技术时，在进行镀覆之前，最好在阻挡金属层150上形成一种子金属层(未示出)。种子金属层增加镀覆金属层160的均匀性并且用作初始成核位置。种子金属层的厚度可以是500～2500，优选是1500。有代表性地用溅射淀积种子金属层，但有时能用CVD淀积。执行溅射的条件是：衬底100的温度是0℃，溅射功率是2kW，压强是2mTorr，以及从目标靶到衬底100的距离是60mm。根据要镀覆的金属层的种类和镀敷技术的类型，种子金属层可以由铜(Cu)、金(Au)、银(Ag)、铂(Pt)或钯(Pd)形成。由于刚刚镀覆完的铜层是由具有低堆积密度的非常小的晶粒形成的，所以应当对铜层施加退火工艺，以利用铜层的再结晶中的晶粒生长来降低它的电阻率。利用溅射或CVD以及镀敷工艺用铜填充开口140。此外，可以用具有适合于互连的电阻值的金属填充开口140，例如金、铂或银。为了确保用于后续CMP工艺的更大的充足裕度，铜层应该淀积到比开口140大0.2μm的高度。
参考图4，利用CMP对图3所产生的结构进行平面化，直到暴露出绝缘膜125的表面，以形成双金属镶嵌互连170。当形成双金属互连170时，很难彻底地阻挡氧。在使用反应室的例子中这是非常真实的。用于CMP的浆液通常含有氧。从而，例如CuO或Cu2O膜的薄氧化铜膜自然地形成在铜层的表面上。如果不从铜层上除去氧化铜膜，那么铜层对于淀积在其上的膜具有不牢固的粘附力，这就增加了电阻率并且降低了半导体器件的可靠性。
因此，应该通过使用等离子工艺175的还原反应除去氧化铜膜。通过施加RF到含有Ar、He和H2的气体中可以产生等离子，获得一种含氢的等离子体，或通过施加RF到含有Ar、He和NH3的气体中，获得一种含NH3的等离子体。如果含NH3等离子体用于等离子工艺175，那么有可能使双金属镶嵌互连170的表面氮化以及还原双金属镶嵌互连170的表面。
此后，如图5所示，在图4的最终结构上淀积氮化硅层180。在氮化硅层180上淀积碳化硅层185。可以利用CVD或PVD形成氮化硅层180和碳化硅层185，但是优选利用等离子增强CVD(PECVD)。两层的厚度各自可以是10～1000。在等离子工艺175期间，可以原位形成氮化硅180和碳化硅185。从而，有可能使形成双金属镶嵌互连170的工艺简单化，并且防止再次形成氧化铜膜。如前面所描述地，如果将覆盖层190形成为如氮化硅层180和碳化硅层185的双层结构，易受漏电流影响的层间绝缘膜和碳化硅层之间的界面就转变成层间绝缘膜和氮化硅层之间的界面，但保留了相对于其它材料具有刻蚀选择性的一部分碳化硅层。从而，有可能满足高刻蚀选择性和漏电流抑制作用的两个方面。
如图5所示，根据本发明的双金属镶嵌互连包括：层间绝缘膜105，在其中具有开口140，开口140具有双金属镶嵌互连170的形状；在开口140内壁中的阻挡金属层150；双金属镶嵌互连170，其填充阻挡金属层150上方的开口140并且具有与层间绝缘膜105的顶部表面处于同一水平面的顶部表面；以及覆盖层190，覆盖层间绝缘膜105和双金属互连170的顶部表面并且是由氮化硅层180和碳化硅层185的双层形成的。
在该实施例中，开口140包括通路沟槽130和重叠在通路沟槽130上的布线沟槽135，以便形成双金属镶嵌互连170。然而，本发明能应用于单金属镶嵌互连，其中形成简单的布线沟槽或通路沟槽。从而，如图6所示，本发明能应用于形成单金属镶嵌互连178的情况中。在这种情况下，覆盖层190形成为氮化硅层180和碳化硅层185的双层结构。
在多层互连中，在将另一层间绝缘膜淀积在覆盖层190上之后，执行双金属镶嵌工艺或单金属镶嵌工艺。这时，覆盖层190起绝缘膜110的作用并且相对于绝缘膜125和115具有高刻蚀选择性，它可以是低介电常数膜。从而，当刻蚀低介电常数膜时，不刻蚀双金属镶嵌互连170或单金属镶嵌互连178。此外，覆盖层190能防止铜扩散进入层间绝缘膜，使得有可能降低漏电流。
根据现有技术图1示出的单金属镶嵌互连的16个样品中的每个和根据本发明图6示出的单金属镶嵌互连来估算两个邻近互连之间的漏电流。在除图1的覆盖层9和图6的覆盖层190以外的同样条件下制备样品。根据现有技术的覆盖层9形成为碳化硅的单层结构。本发明的覆盖层190形成为氮化硅层180和碳化硅层185的双层结构。分析结果显示出初始漏电流从现有技术的大约300nA减少到本发明的大约10nA，从而本发明的漏电流减少到现有技术的初始漏电流的大约1/10。
在5MV/cm范围200℃下分析两个邻近互连的偏压热应力(bias thermalstress，BTS)特性。当BTS运用到现有技术的单金属镶嵌互连中时，16个样品中的5个样品具有初始失效。然而，在本发明中就不存在初始失效。
当测试BTS特性时，图7的曲线(a)和(b)分别表示用于现有技术和本发明的威布尔标绘图(Weibull plot)。如图7中所示，当累积可靠性是50％时，按照曲线(a)来说达到失效的时间是1.3E6秒，以及按照曲线(b)来说达到失效的时间是1.0E6秒。从而，根据本发明的失效时间减少到根据现有技术的失效时间的大约80％。然而，根据本发明的形状系数(shape factor)比现有技术的形状系数显著提高了。从而，测定出本发明更有助于使用期限的预测。因此，按照本发明，覆盖层能具有极好的漏电流抑制以及相对于低介电常数层的高刻蚀选择性。极好的漏电流抑制是由于氮化硅层对层间绝缘膜的良好粘附力的结果。
当测试抗电迁移性能时，图8的曲线(a)和(b)分别表示用于现有技术和本发明的威布尔标绘图。如图8中所示，当累积可靠性是50％时，按照曲线(a)来说达到失效的时间少于100秒，并且数据点的分布情况非常差。然而，在与曲线(a)相同的条件下，按照曲线(b)来说失效时间多于150秒，并且其标准偏差σ是0.42，从而显示出良好的分布。因此，测定出本发明比现有技术显示出更加被期望的结果。在现有技术中，由于碳化硅层和铜互连之间的界面间表面不稳定，所以在界面间表面中出现孔洞并且引起初始失效。然而，按照本发明，由于提高了界面间表面的界面特性，所以在界面间表面中不会出现孔洞。
如上面所描述地，由氮化硅层和碳化硅层的双层结构形成的覆盖层用于被CMP处理过的金属镶嵌互连。氮化硅层对于层间绝缘膜具有良好的粘附力，这提供了优良的漏电流抑制作用。氮化硅层具有相对高的介电常数，例如6-8，但它能结合具有4-5的介电常数的碳化硅。从而，能降低覆盖层的介电常数。此外，碳化硅容许覆盖层相对于淀积在其上的其它层间绝缘膜具有高刻蚀选择性。
当参考本发明的示范性实施例具体地示出和说明本发明时，本领域的普通技术人员应当清楚地理解，在不背离附加权利要求所限定的本发明的精神和范围时，可以在形式和细节上作出各种改变。

Claims (16)

1、一种半导体器件的互连，包括：
层间绝缘膜，其具有位于其中的、成互连的形状的开口；
沿该开口的内壁形成的阻挡金属层；
填充在该阻挡金属层上方的该开口的金属层，并且该金属层具有与该层间绝缘膜的顶部表面水平的顶部表面；以及
覆盖该层间绝缘膜和该金属层的顶部表面的覆盖层，该覆盖层是由顺序淀积的氮化硅层和碳化硅层形成的双层结构。
2、根据权利要求1的互连，其中该金属层是由铜和铜合金中的一种构成的。
3、根据权利要求1的互连，其中该阻挡金属层是由钛、钽、钨以及它们的氮化物中的一种构成的。
4、根据权利要求1的互连，其中该互连是由通路和布线之一形成的金属镶嵌互连。
5、根据权利要求1的互连，其中该互连是由通路和重叠在该通路上的布线形成的金属镶嵌互连。
6、根据权利要求1的互连，其中该氮化硅层和该碳化硅层均具有10～1000的厚度。
7、一种形成半导体器件的互连的方法，该方法包括：
(a)在衬底上形成层间绝缘膜；
(b)通过刻蚀该层间绝缘膜形成具有互连形状的开口；
(c)在步骤(b)的最终结构上形成阻挡金属层；
(d)通过在该阻挡金属层上形成金属层来填充开口；
(e)使步骤(d)的最终结构平面化直到暴露出该层间绝缘膜；以及
(f)通过在步骤(e)的最终结构上顺序淀积氮化硅层和碳化硅层来形成覆盖层。
8、根据权利要求7的方法，其中该方法还包括：
在步骤(e)和(f)之间，对步骤(e)的最终结构的表面施加等离子工艺。
9、根据权利要求8的方法，其中该等离子工艺使用含氢的等离子体以便还原该金属层。
10、根据权利要求8的方法，其中该等离子工艺使用含有NH3的等离子体以便还原该金属层以及氮化该金属层的表面。
11、根据权利要求7的方法，其中通过施加化学气相淀积(CVD)、溅射或镀铜或镀铜合金来形成该金属层。
12、根据权利要求7的方法，其中该氮化硅层是利用等离子增强化学气相淀积(PECVD)形成的并且具有10～1000的厚度。
13、根据权利要求7的方法，其中该碳化硅层是利用PECVD形成的并且具有10～1000的厚度。
14、根据权利要求7的方法，其中该开口是由通路沟槽和布线沟槽中的一种形成的。
15、根据权利要求7的方法，其中该开口是由通路沟槽和重叠在该通路沟槽上方的布线沟槽形成的。
16、根据权利要求7的方法，其中该方法还包括：
在步骤(e)和(f)之间，对步骤(e)的最终结构的表面施加等离子工艺，通过使用含有NH3的等离子体以便还原该金属层和氮化该金属层的表面，其中在步骤(f)中原位执行施加等离子工艺。
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CN102903665A (zh) * 2011-07-25 2013-01-30 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
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CN112018077A (zh) * 2020-07-29 2020-12-01 复旦大学 一种铜互连结构及其制造方法

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US20060163736A1 (en) 2006-07-27
JP2004214654A (ja) 2004-07-29
KR20040060447A (ko) 2004-07-06
US7605472B2 (en) 2009-10-20
US7037835B2 (en) 2006-05-02
US20040135261A1 (en) 2004-07-15
US20070138642A1 (en) 2007-06-21
US7205666B2 (en) 2007-04-17

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