CN1516276A - Seiconductor interconnection with double-cover and its mfg. method - Google Patents

Seiconductor interconnection with double-cover and its mfg. method Download PDF

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CN1516276A
CN1516276A CNA2003101247376A CN200310124737A CN1516276A CN 1516276 A CN1516276 A CN 1516276A CN A2003101247376 A CNA2003101247376 A CN A2003101247376A CN 200310124737 A CN200310124737 A CN 200310124737A CN 1516276 A CN1516276 A CN 1516276A
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interconnection
layer
metal level
interlayer dielectric
copper
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CN100350604C (en
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���
李敬雨
李守根
朴基澈
宋源祥
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract

Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

Description

Interconnection and manufacture method thereof with two tectal semiconductor device
The present invention require on December 30th, 2002 application, meet the 35th § of U.S.C 119 priority regulation, Korean patent document No.2002-87245, therefore it is done in full with reference to quoting.
Technical field
The present invention relates to a kind of in interconnection as line and/or path in the semiconductor device and the method that is used to form interconnection, more particularly, relate to a kind of that in low-dielectric constant layer, form and be covered tectal list or dual damascene interconnection (single or dual damascene interconnection) and forming method thereof.
Background technology
In order to obtain high-speed semiconductor device, be necessary to reduce the length of the thickness and the grid of gate oxide level.Yet, postpone for the speed of semiconductor device, to have negative effect with the resistance value of interconnection and the proportional RC of capacitance (resistance value-capacitance) of interlayer dielectric.Thereby, made various trials, reduce the RC delay by the interconnection of use low-resistance value and the interlayer dielectric of low-k.
According to routine, use aluminium (Al) widely as interconnection material.Yet, think gradually that in recent years copper for integrated circuit (Cu) is more useful.The resistance coefficient of copper (Cu) is half of resistance coefficient of aluminium (Al), and therefore might increase the signal transmitting speed with the little copper of width (Cu).In addition, because copper (Cu) has the deelectric transferred ability of height, so can improve the reliability of semiconductor device.And copper (Cu) demonstrates low-power consumption and more cheap than aluminium (Al).
Yet a shortcoming using copper (Cu) is that copper (Cu) is difficult to be etched and composition and obtain desired interconnection.Therefore, form copper-connection with damascene process An.Damascene process An comprises following conventional steps.In interlayer dielectric, form and have desired interconnection shaped aperture.Then, after formation copper layer is with filling opening, carry out planarization technology.Usually, (chemicalmechanical polishing is CMP) as planarization technology to use chemico-mechanical polishing.Particularly, use dual damascene process to form copper (Cu) interconnection.Dual damascene process comprises the steps.Form path groove and wire laying slot, make that the top of wire laying slot and path groove is overlapping.Then, after formation copper layer is with filling vias groove and wire laying slot, carry out planarization technology.As known for the skilled artisan, preface is called as single damascene process.
Fig. 1 example the sectional view of conventional monometallic mosaic interlinkage.With reference to figure 1, damascene interconnection 7 is filled the opening 3 in the interlayer dielectric 1 and is blocked metal level 5 and surrounds.For example the cover layer 9 of silicon nitride layer covers interlayer dielectric 1 and damascene interconnection 7.During damascene process An, execute after the CMP deposited capping layer 9 in damascene interconnection 7.Cover layer 9 should stop copper (Cu) to be diffused in the interlayer dielectric 1 effectively, and cover layer 9 has high etching selection with respect to other interlayer dielectric that will be formed in the damascene interconnection 7.Since in recent years with low-k for example the material of 2-4 as interlayer dielectric, so become obviously for the demand of the substitute of silicon nitride.In fact, silicon nitride is typically as cover layer, but it has for example high-k and the low etching selection that has with respect to low-dielectric constant layer of 6-8.Carborundum has the low-k of 4-5 for example and with respect to the high etching selection of low-dielectric constant layer.Therefore, carborundum is to replace silicon nitride as tectal suitable substitute.Yet, be difficult to more suppress if carborundum as cover layer, becomes at the interlayer dielectric of complanation and the leakage current in the interface between the cover layer so.
Summary of the invention
The invention provides a kind of interconnection of semiconductor device, wherein improved tectal characteristic, make the cover layer to have high etching selection and demonstrate the drain current suppressing effect that has improved with respect to low-dielectric constant layer.
The present invention also provides a kind of method that is used to form the semiconductor device interconnection.
The method of two cover layers of damascene interconnection, the interconnection that comprises tectal semiconductor device and formation interconnection is provided, and wherein two cover layers are formed by silicon nitride and carborundum.
According to a scheme of the present invention, provide a kind of interconnection of semiconductor device.Interconnection comprises interlayer dielectric, barrier metal layer, metal level and cover layer.Interlayer dielectric has the opening that is formed in it, and opening has the shape of interconnection.Inwall along opening forms barrier metal layer.Metal level is filled the opening of barrier metal layer top and is had top surface with the top surface level of interlayer dielectric.Cover layer covers the top surface of interlayer dielectric and metal level and is the bilayer that forms by consecutive deposition silicon nitride layer and silicon carbide layer.
According to another aspect of the present invention, provide a kind of method that forms the semiconductor device interconnection.This method comprises: (a) form interlayer dielectric on substrate; (b) has the interconnection shaped aperture by the formation of etching interlayer dielectric; (c) on the final structure of step (b), form barrier metal layer; (d) by on barrier metal layer, forming the metal level filling opening; (e) make the final structure complanation of step (d) up to exposing interlayer dielectric; And (f) by deposit silicon nitride layer and silicon carbide layer form cover layer continuously on the final structure of step (e).
As described above, when interlayer dielectric is deposited on two cover layers and is etched when being formed on two supratectal another interconnection, the bilayer that forms by consecutive deposition silicon nitride layer and silicon carbide layer has high etching selection with respect to interlayer dielectric.Equally, might improve drain current suppressing effect in the interface between interlayer dielectric and two cover layer.
Description of drawings
Above and other objects of the present invention, feature and beneficial effect will be more obvious by the more specifically explanation of the preferred embodiment of the present invention, and these preferred embodiments shown in the drawings, the same reference character of all accompanying drawings are indicated all the time with a part.Accompanying drawing needn't be drawn in proportion, but example goes out principle of the present invention emphatically.
Fig. 1 is the sectional view that example goes out conventional monometallic mosaic interlinkage;
Fig. 2 to 5 is that example goes out interconnection according to an embodiment of the invention and is used to form the sectional view of the method for interconnection;
Fig. 6 is that example goes out interconnection according to another embodiment of the invention and is used to form the sectional view of the method for interconnection;
Fig. 7 is bias voltage thermal stress (bias thermal stress, BTS) diagrammatic sketch of the experimental result of characteristic of conventional interconnection and the interconnection according to the present invention;
Fig. 8 is the diagrammatic sketch of the conventional anti-electromigratory experimental result that interconnects and interconnect according to the present invention.
Embodiment
Fig. 2 to 5 is that example goes out interconnection according to an embodiment of the invention and is used to form the sectional view of the method for interconnection.Following description relates generally to a kind of copper-connection, but also can be applied to all low-resistance value electric conducting materials, for example aluminium (Al), silver (Ag), gold (Au), copper (Cu) and their alloy.
With reference to figure 2, on substrate 100, form interlayer dielectric 105.Can between substrate 100 and interlayer dielectric 105, insert insulating barrier or conductive layer, for example doped silicon, tungsten (W), aluminium (Al) or copper (Cu).Interlayer dielectric 105 is made up of the lamination of dielectric film 110,115,120 and 125. Dielectric film 115 and 125 is to be used to form the oxidation film of opening and is that described opening has the shape of desired interconnection by postponing to reduce RC (resistance and capacitance, resistance value and capacitance) that advanced low-k materials forms.For example, advanced low-k materials can be carbonado, fluorosilicate glass (fluorine silicate glass, FSG), SiOC, polyimides or SiLK TM Dielectric film 110 and 120 be form by carborundum and when etching dielectric film 115 and 125 when forming opening as etch stop layer.
By etching part interlayer dielectric 105, formation has desired interconnection shaped aperture 140.The opening 140 of Fig. 2 is used for dual damascene interconnection, and wherein wire laying slot 135 is formed on the path groove 130.After forming path groove 130, form wire laying slot 135 by etching dielectric film 125 and 120, so that wire laying slot 135 overlaps on the path groove 130 by order etching dielectric film 125,120,115 and 110.Selectively, before forming path groove 130, can form wire laying slot 135.
With reference to figure 3, after cleaning has the generation structure of opening 140, producing formation barrier metal layer 150 on the structure.Barrier metal layer 150 stops the metallic atom of the material that is used for filling opening 140 to diffuse into interlayer dielectric 105.The thickness of barrier metal layer 150 is 200～1000 , preferably 450 .Barrier metal layer 150 can be titanium (Ti), tantalum (Ta), tungsten (W) or their nitride.For example, barrier metal layer 150 can be TiN, TaN, WN, TaSiN, WSiN or TiSiN.Can use chemical vapor deposition (chemical vapor deposition, CVD) or the physical vapor deposition of for example sputter (physical vapor deposition, PVD) the deposition preventing metal level 150.
Use metal level 160 filling openings 140 that form by copper or copper alloy.Form copper alloy by having a mind to or copper and a small amount of C, Ag, Co, Ta, In, Sn, Zn, Mn, Ti, Mg, Cr, Ge, Sr, Pt, Mg, Al or Zr being mixed.Typically, by use sputter or CVD copper filling opening 140, but can use the plating technology that comprises plating (electro plating) and chemical plating (electrolessplating) to come filling opening 140 with copper.When using the plating technology, before carrying out plating, be preferably in and form a seed metal layer (not shown) on the barrier metal layer 150.Seed metal layer increases the uniformity of metal plating layer 160 and is used as initial nucleation site.The thickness of seed metal layer can be 500～2500 , preferably 1500 .Use the sputtering deposit seed metal layer typically, but can use the CVD deposit sometimes.The condition of carrying out sputter is: the temperature of substrate 100 is 0 ℃, and sputtering power is 2kW, and pressure is 2mTorr, and 100 distance is 60mm from the target to the substrate.According to the kind of the metal level of wanting plating and the type of plating technology, seed metal layer can be formed by copper (Cu), gold (Au), silver (Ag), platinum (Pt) or palladium (Pd).Because just the intact copper layer of plating is to be formed by the very little crystal grain with low bulk density, so should apply annealing process to the copper layer, reduces its resistivity with the grain growth in the crystallization again that utilizes the copper layer.Utilize sputter or CVD and shikishima plating process copper filling opening 140.In addition, can be with metal filled opening 140 with the resistance value that is suitable for interconnecting, for example gold, platinum or silver.In order to ensure the bigger sufficient nargin that is used for subsequent CMP technology, the copper layer should be deposited to the height of ratio open 140 big 0.2 μ m.
With reference to figure 4, utilize CMP that the structure that Fig. 3 produced is carried out complanation, up to the surface that exposes dielectric film 125, to form dual damascene interconnection 170.Interconnect 170 the time when forming bimetallic, be difficult to stop up hill and dale oxygen.This is very real in the example that uses reative cell.The slurries that are used for CMP contain aerobic usually.Thereby, for example CuO or Cu 2The thin oxidation copper film of O film is formed naturally on the surface of copper layer.If do not remove the oxidation copper film from the copper layer, the copper layer has unstable adhesion for deposit film thereon so, the reliability that this has just increased resistivity and has reduced semiconductor device.
Therefore, should remove the oxidation copper film by the reduction reaction of using plasma process 175.By applying RF to containing Ar, He and H 2Gas in can produce plasma, obtain a kind of hydrogeneous plasma, or by applying RF to containing Ar, He and NH 3Gas in, obtain a kind of NH that contains 3Plasma.If contain NH 3Plasma is used for plasma process 175, might make the surface of the surfaces nitrided of dual damascene interconnection 170 and reduction dual damascene interconnection 170 so.
After this, as shown in Figure 5, deposit silicon nitride layer 180 on the final structure of Fig. 4.Deposit silicon carbide layer 185 on silicon nitride layer 180.Can utilize CVD or PVD to form silicon nitride layer 180 and silicon carbide layer 185, but preferably utilize plasma-enhanced CVD (PECVD).Two-layer thickness can be 10～1000 separately.During plasma process 175, can original position form silicon nitride 180 and carborundum 185.Thereby, the technology that forms dual damascene interconnection 170 is oversimplified, and prevented to form once more the oxidation copper film.As described previously, if cover layer 190 is formed double-decker as silicon nitride layer 180 and silicon carbide layer 185, be subject to the interlayer dielectric of influence of leakage current and the interface between the silicon carbide layer and just be transformed into interface between interlayer dielectric and the silicon nitride layer, but kept a part of silicon carbide layer that has etching selection with respect to other material.Thereby, might satisfy two aspects of high etching selection and drain current suppressing effect.
As shown in Figure 5, dual damascene interconnection according to the present invention comprises: interlayer dielectric 105, have opening 140 therein, and opening 140 has the shape of dual damascene interconnection 170; Barrier metal layer 150 in opening 140 inwalls; Dual damascene interconnection 170, it is filled the opening 140 of barrier metal layer 150 tops and has the top surface that is in same horizontal plane with the top surface of interlayer dielectric 105; And cover layer 190, cover the top surface of interlayer dielectric 105 and bimetallic interconnection 170 and be that bilayer by silicon nitride layer 180 and silicon carbide layer 185 forms.
In this embodiment, opening 140 comprises path groove 130 and the wire laying slot 135 that overlaps on the path groove 130, so that form dual damascene interconnection 170.Yet the present invention can be applied to the monometallic mosaic interlinkage, wherein forms simple wire laying slot or path groove.Thereby as shown in Figure 6, the present invention can be applied to form in the situation of monometallic mosaic interlinkage 178.In this case, cover layer 190 forms the double-decker of silicon nitride layer 180 and silicon carbide layer 185.
In multilayer interconnection, after being deposited on another interlayer dielectric on the cover layer 190, carry out dual damascene process or single damascene process.At this moment, cover layer 190 plays dielectric film 110 and has high etching selection with respect to dielectric film 125 and 115, and it can be a film having low dielectric constant.Thereby, when etching low dielectric constant films, not etching dual damascene interconnection 170 or monometallic mosaic interlinkage 178.In addition, cover layer 190 can prevent that copper from diffusing into interlayer dielectric, makes to reduce leakage current.
According in 16 samples of the monometallic mosaic interlinkage shown in prior art Fig. 1 each and according to the present invention the monometallic mosaic interlinkage shown in Fig. 6 estimate two leakage currents between the contiguous interconnection.Under the similarity condition except that the cover layer 190 of the cover layer 9 of Fig. 1 and Fig. 6, prepare sample.Form the single layer structure of carborundum according to the cover layer 9 of prior art.Cover layer 190 of the present invention forms the double-decker of silicon nitride layer 180 and silicon carbide layer 185.Analysis result demonstrates initial leakage current and reduces to about 10nA of the present invention from about 300nA of prior art, thus leakage current of the present invention reduce to prior art initial leakage current about 1/10.
In 200 ℃ of bias voltage thermal stress (bias thermalstress, BTS) characteristics of analyzing two contiguous interconnection down of 5MV/cm scope.When BTS applied in the monometallic mosaic interlinkage of prior art, 5 samples in 16 samples had primary failure.Yet, just do not have primary failure in the present invention.
When test b TS characteristic, the curve of Fig. 7 (a) and (b) respectively expression be used for prior art and Weibull plot of the present invention (Weibull plot).As shown in Figure 7, when accumulation reliability when being 50%, the time that reaches inefficacy according to curve (a) is 1.3E6 second, and the time that reaches inefficacy according to curve (b) is 1.0E6 second.Thereby the out-of-service time according to the present invention reduced to according to about 80% of the out-of-service time of prior art.Yet, significantly improved according to the form factor of form factor of the present invention (shape factor) than prior art.Thereby, determine the prediction that the present invention more helps useful life.Therefore, according to the present invention, cover layer can have fabulous drain current suppressing and with respect to the high etching selection of low-dielectric constant layer.Fabulous drain current suppressing is owing to the result of silicon nitride layer to the excellent adhesion of interlayer dielectric.
When test during deelectric transferred performance, the curve of Fig. 8 (a) and (b) represent to be used for prior art and Weibull plot of the present invention respectively.As shown in Figure 8, when the accumulation reliability was 50%, the time that reaches inefficacy according to curve (a) was less than 100 seconds, and the non-constant of distribution of data points situation.Yet under the condition identical with curve (a), and its standard deviation was 0.42 more than 150 seconds the out-of-service time according to curve (b), thereby demonstrated good distribution.Therefore, determine the present invention and demonstrate the result who is supposed to more than prior art.In the prior art, because the surface is unstable between the interface between silicon carbide layer and the copper-connection, so between the interface, occur hole in the surface and cause primary failure.Yet, according to the present invention, owing to improved the interfacial characteristics on surface between the interface, so between the interface, hole can not occur in the surface.
As described above, the cover layer that is formed by the double-decker of silicon nitride layer and silicon carbide layer is used for the damascene interconnection handled by CMP.Silicon nitride layer has good adhesion for interlayer dielectric, and this provides good drain current suppressing effect.Silicon nitride layer has high relatively dielectric constant, 6-8 for example, but its can be in conjunction with the carborundum of the dielectric constant with 4-5.Thereby, can reduce tectal dielectric constant.In addition, carborundum allows that cover layer has high etching selection with respect to deposit other interlayer dielectric thereon.
When illustrating particularly and illustrate when of the present invention with reference to one exemplary embodiment of the present invention, those of ordinary skill in the art it should be clearly understood that, when the spirit and scope of the present invention that do not deviate from accessory claim and limited, can make various changes in form and details.

Claims (16)

1, a kind of interconnection of semiconductor device comprises:
Interlayer dielectric, it has and is positioned at shaped aperture wherein, that become interconnection;
The barrier metal layer that forms along the inwall of this opening;
Be filled in the metal level of this opening of this barrier metal layer top, and this metal level has the top surface with the top surface level of this interlayer dielectric; And
Cover the cover layer of the top surface of this interlayer dielectric and this metal level, this cover layer is the double-decker that is formed by the silicon nitride layer of sequential deposit and silicon carbide layer.
2, according to the interconnection of claim 1, wherein this metal level is to be made of a kind of in the copper and copper alloy.
3, according to the interconnection of claim 1, wherein this barrier metal layer is to be made of a kind of in titanium, tantalum, tungsten and their nitride.
4, according to the interconnection of claim 1, wherein this interconnection is the damascene interconnection that is formed by one of path and wiring.
5, according to the interconnection of claim 1, wherein this interconnection is by path and overlaps the damascene interconnection that the wiring on this path forms.
6, according to the interconnection of claim 1, wherein this silicon nitride layer and this silicon carbide layer all have the thickness of 10～1000 .
7, a kind of method that forms the interconnection of semiconductor device, this method comprises:
(a) on substrate, form interlayer dielectric;
(b) has the interconnection shaped aperture by this interlayer dielectric formation of etching;
(c) on the final structure of step (b), form barrier metal layer;
(d) come filling opening by on this barrier metal layer, forming metal level;
(e) make the final structure complanation of step (d) up to exposing this interlayer dielectric; And
(f) form cover layer by sequential deposit silicon nitride layer and silicon carbide layer on the final structure of step (e).
8, according to the method for claim 7, wherein this method also comprises:
In step (e) with (f), the surface of the final structure of step (e) is applied plasma process.
9, method according to Claim 8, wherein this plasma process uses hydrogeneous plasma so that reduce this metal level.
10, method according to Claim 8, wherein this plasma process uses and contains NH 3Plasma so that reduce the surface of this metal level and this metal level of nitrogenize.
11, according to the method for claim 7, wherein form this metal level by applying chemical vapor deposition (CVD), sputter or copper facing or copper-beryllium.
12, according to the method for claim 7, wherein this silicon nitride layer is to utilize form and the thickness that have 10～1000 of plasma-reinforced chemical vapor deposition (PECVD).
13, according to the method for claim 7, wherein this silicon carbide layer is to utilize form and the thickness that have 10～1000 of PECVD.
14, according to the method for claim 7, wherein this opening is by a kind of formation the in path groove and the wire laying slot.
15, according to the method for claim 7, wherein this opening is to be formed by path groove and the wire laying slot that overlaps this path groove top.
16, according to the method for claim 7, wherein this method also comprises:
In step (e) with (f), the surface of the final structure of step (e) is applied plasma process, contain NH by use 3Plasma so that reduce the surface of this metal level and this metal level of nitrogenize, wherein original position is carried out and is applied plasma process in step (f).
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US7205666B2 (en) 2007-04-17
KR20040060447A (en) 2004-07-06
US20070138642A1 (en) 2007-06-21
US20060163736A1 (en) 2006-07-27
US20100003814A1 (en) 2010-01-07
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US7951712B2 (en) 2011-05-31
US7605472B2 (en) 2009-10-20

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