JP2000150516A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JP2000150516A
JP2000150516A JP10321537A JP32153798A JP2000150516A JP 2000150516 A JP2000150516 A JP 2000150516A JP 10321537 A JP10321537 A JP 10321537A JP 32153798 A JP32153798 A JP 32153798A JP 2000150516 A JP2000150516 A JP 2000150516A
Authority
JP
Japan
Prior art keywords
film
insulating film
via hole
etching
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10321537A
Other languages
Japanese (ja)
Inventor
Takashi Akahori
孝 赤堀
Koichiro Inasawa
剛一郎 稲沢
Koji Senoo
幸治 妹尾
Masaaki Hagiwara
正明 萩原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP10321537A priority Critical patent/JP2000150516A/en
Priority to PCT/JP1999/004741 priority patent/WO2000014786A1/en
Priority to KR10-2001-7002791A priority patent/KR100400907B1/en
Priority to EP99940607A priority patent/EP1120822A4/en
Priority to TW088115109A priority patent/TW464952B/en
Publication of JP2000150516A publication Critical patent/JP2000150516A/en
Priority to US09/665,960 priority patent/US6737350B1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3127—Layers comprising fluoro (hydro)carbon compounds, e.g. polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To fabricate a semiconductor device employing a fluorine added carbon film as an interlayer insulating film using a simple dual Damascene method. SOLUTION: An insulating film, e.g. SiO2 film 3 is deposited on a substrate 2 and a via hole 31 is etched therein and then an upper insulating film, e.g. a CF film 4, is formed on the upper surface of the SiO2 film 3. When the CF film is deposited by generating plasma of a filming material having bad embedding characteristics, e.g. C6F6 gas, the CF film can be deposited on the upper surface of the SiO2 film 3 while suppressing embedding of the CF film into the via hole 31. When a trench 41 is etched subsequently in the CF film 4, a dual Damascene shape integrating the trench 41 and the via hole 31 can be obtained easily.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、デュアルダマシン
法により半導体装置を製造する方法に関する。The present invention relates to a method for manufacturing a semiconductor device by a dual damascene method.

【０００２】[0002]

【従来の技術】半導体デバイスの高集積化を図るため
に、パターンの微細化、回路の多層化といった工夫が進
められており、そのうちの一つとして配線を多層化する
技術がある。多層配線構造をとるためには、ｎ層目の配
線層と（ｎ＋１）番目の配線層の間を導電層で接続する
と共に、導電層以外の領域は層間絶縁膜と呼ばれる薄膜
が形成される。2. Description of the Related Art In order to increase the degree of integration of semiconductor devices, techniques such as miniaturization of patterns and multi-layering of circuits have been devised. One of them is a technique of multi-layer wiring. In order to form a multilayer wiring structure, a conductive layer is connected between the nth wiring layer and the (n + 1) th wiring layer, and a thin film called an interlayer insulating film is formed in a region other than the conductive layer.

【０００３】この層間絶縁膜の代表的なものとしてＳｉ
Ｏ2 膜があるが、近年デバイスの動作についてより一層
の高速化を図るために層間絶縁膜の比誘電率を低くする
ことが要求されており、層間絶縁膜の材質についての検
討がなされている。即ちＳｉＯ2 膜は比誘電率がおよそ
４であり、これよりも小さい材質の発掘に力が注がれて
いる。そのうちの一つとして比誘電率が３．５であるＳ
ｉＯＦ膜の実現化が進められているが、本発明者は比誘
電率が更に小さいフッ素添加カーボン膜（以下「ＣＦ
膜」という）に注目している。A typical example of this interlayer insulating film is Si
Although there is an O 2 film, it has been required in recent years to lower the relative dielectric constant of the interlayer insulating film in order to further increase the operation speed of the device, and the material of the interlayer insulating film has been studied. . That is, the SiO 2 film has a relative dielectric constant of about 4, and efforts are being made to excavate materials smaller than this. One of them is S having a relative dielectric constant of 3.5.
While the realization of iOF films has been promoted, the present inventor has proposed a fluorine-added carbon film (hereinafter referred to as “CF
Film)).

【０００４】ところで溝配線とビアプラグを一度に形成
する手法としてデュアルダマシンプロセスがあり、この
プロセスにより低誘電率層間絶縁膜を用いた半導体デバ
イスを製造する方法については、月刊セミコンダクタ−
ワ−ルド1998年2 月号p.10８〜114 に、溝を先にエッチ
ングする方法や、ビアホ−ルを先にエッチングする方
法、溝とビアホ−ルをセルフアラインで一度にエッチン
グする方法等、想定されるプロセスフロ−が記載されて
いる。There is a dual damascene process as a method of forming a trench wiring and a via plug at one time. A method of manufacturing a semiconductor device using a low dielectric constant interlayer insulating film by this process is described in Monthly Semiconductor.
World, February 1998, pp. 108-114, a method of etching a groove first, a method of etching a via hole first, a method of etching a groove and a via hole at once by self-alignment, etc. The assumed process flow is described.

【０００５】このうちのセルフアラインで一度にエッチ
ングする方法について図１７及び図１８を用いて簡単に
説明する。図１７（ａ）中１０はビアホ−ルが形成され
る第１の低誘電率層間絶縁膜、１１はＳｉ3 Ｎ4 層、１
２はＳｉ3 Ｎ4 層又はＳｉＯ2 膜からなるエッチングス
トッパ層である。先ず図１７（ｂ），（ｃ）に示すよう
にエッチングストッパ層１２をビアホ−ルパタ−ン状に
エッチングする。図中１３はフォトレジストである。次
いでエッチングストッパ層１２の上面に、溝が形成され
る第２の低誘電率層間絶縁膜１４とＳｉＯ2 膜からなる
ハ−ドマスク１５とをこの順序で成膜する（図１７
（ｄ），（ｅ）参照）。The method of etching at a time by self-alignment will be briefly described with reference to FIGS. 17 and 18. FIG. In FIG. 17A, 10 is a first low dielectric constant interlayer insulating film in which a via hole is formed, 11 is a Si 3 N 4 layer, 1
Reference numeral 2 denotes an etching stopper layer made of a Si 3 N 4 layer or a SiO 2 film. First, as shown in FIGS. 17B and 17C, the etching stopper layer 12 is etched in a via hole pattern. In the figure, reference numeral 13 denotes a photoresist. Next, on the upper surface of the etching stopper layer 12, a second low dielectric constant interlayer insulating film 14 in which a groove is formed and a hard mask 15 made of a SiO 2 film are formed in this order (FIG. 17).
(See (d) and (e)).

【０００６】続いて図１８（ａ），（ｂ）に示すように
ハ−ドマスク１５を溝パタ−ン状にエッチングした後、
図１８（ｃ）に示すようにハ−ドマスク１５をマスクと
して第２の低誘電率層間絶縁膜１４に溝１４ａをエッチ
ングする。そしてさらにエッチングストッパ層１２をマ
スクとしてエッチングを続け、第１の低誘電率層間絶縁
膜１０にビアホ−ル１０ａをエッチングする（図１８
（ｄ）参照）。図中１６はフォトレジストである。Subsequently, as shown in FIGS. 18A and 18B, the hard mask 15 is etched into a groove pattern,
As shown in FIG. 18C, the trench 14a is etched in the second low dielectric constant interlayer insulating film 14 using the hard mask 15 as a mask. Then, the etching is continued using the etching stopper layer 12 as a mask, and the via hole 10a is etched in the first low dielectric constant interlayer insulating film 10 (FIG. 18).
(D)). In the figure, reference numeral 16 denotes a photoresist.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら上述の方
法では、エッチングストッパ層１２、ハ−ドマスク１
５、第１及び第２の低誘電率層間絶縁膜１０，１４の合
計４回のエッチングが必要であって工程が多くなる上、
溝のエッチングとビアホ−ルのエッチングとを連続して
行っているので、溝からビアホ−ルへの急激な被エッチ
ング面積の減少による過剰ラジカルの影響等の課題が想
定される。However, in the above method, the etching stopper layer 12, the hard mask 1
5. The first and second low dielectric constant interlayer insulating films 10 and 14 need to be etched a total of four times, which increases the number of processes and
Since the etching of the groove and the etching of the via hole are performed continuously, problems such as the influence of excess radicals due to a sharp decrease in the area to be etched from the groove to the via hole are expected.

【０００８】また溝を形成してからビアホ−ルを形成す
るプロセスフロ−や、ビアホ−ルを形成してから溝を形
成するプロセスフロ−等においても、やはりエッチング
回数が多い上、一度エッチングした場所をさらに加工す
るという従来のエッチングにはないプロセスを行わなけ
ればならないので種々の課題が予想される。このように
デュアルダマシンプロセスは現状では工程が複雑であっ
てスル−プットが悪く、コストアップを招くという大き
な問題がある。Also, in a process flow in which a via hole is formed after forming a groove, and in a process flow in which a groove is formed after forming a via hole, the number of times of etching is large, and etching is performed once. Various problems are anticipated because a process that further processes the place, which is not included in the conventional etching, must be performed. As described above, at present, the dual damascene process has a serious problem that the process is complicated, the throughput is poor, and the cost is increased.

【０００９】本発明はこのような事情の下になされたも
のであり、その目的は、例えば比誘電率の低いフッ素添
加カ−ボン膜を層間絶縁膜として用いた半導体装置を簡
易な手法のデュアルダマシン法により製造する方法を提
供することにある。The present invention has been made under such circumstances, and an object of the present invention is to provide, for example, a semiconductor device using a fluorine-added carbon film having a low relative dielectric constant as an interlayer insulating film by a simple method. An object of the present invention is to provide a method of manufacturing by a damascene method.

【００１０】[0010]

【課題を解決するための手段】このため本発明は、被処
理体上に絶縁膜を形成する工程と、前記絶縁膜にビアホ
−ルをエッチングする工程と、ビアホ−ルが形成された
絶縁膜の表面に、埋め込み特性の悪い成膜材料を用いて
例えばフッ素添加カ−ボン膜からなる上部絶縁膜を形成
する工程と、前記上部絶縁膜に、金属を埋め込み配線を
形成するための溝を前記ビアホ−ルの少なくとも一部に
接触するようにエッチングする工程と、を含むことを特
徴とする。ここで「埋め込み特性が悪い」と記述してい
るが、これは対象物がホールで有り、通常絶縁膜の埋め
込みを論議するのは、溝への埋め込みを論議するが、本
特許では、下地がホールを有しており、そのホールへの
埋め込みが悪いことを「埋め込み特性が悪い」と表記し
ている。例えば前記フッ素添加カ−ボン膜を形成する工
程は、炭素とフッ素との化合物を含み、埋め込み特性の
悪い成膜材料例えばヘキサフルオロベンゼンをプラズマ
化することにより行われる。SUMMARY OF THE INVENTION Accordingly, the present invention provides a process for forming an insulating film on a workpiece, a process for etching a via hole in the insulating film, and a process for forming an insulating film on which a via hole is formed. Forming an upper insulating film made of, for example, a fluorine-added carbon film using a film-forming material having a poor embedding property, and forming a groove for embedding a metal in the upper insulating film to form a wiring. Etching to contact at least a part of the via hole. Here, it is described that “the embedding property is poor”. This is because the object is a hole, and the embedding of the insulating film is usually discussed in terms of embedding in a groove. It has holes and poor embedding in the holes is described as “poor embedding characteristics”. For example, the step of forming the fluorine-added carbon film is performed by converting a film-forming material, such as hexafluorobenzene, containing a compound of carbon and fluorine and having poor embedding characteristics into plasma.

【００１１】また本発明は、被処理体上に絶縁膜を形成
する工程と、前記絶縁膜にビアホ−ルをエッチングする
工程と、ビアホ−ルが形成された絶縁膜の表面に、当該
絶縁膜とはエッチング選択比の異なる上部絶縁膜を形成
する工程と、前記上部絶縁膜に、金属を埋め込むことに
より配線を形成するための溝を前記ビアホ−ルの少なく
とも一部に接触するようにエッチングする工程と、上部
絶縁膜のエッチング終了後所定時間エッチングを行なう
ことにより、ビアホ−ル内に堆積した上部絶縁膜をエッ
チングにより除去する工程と、を含むことを特徴とす
る。この際ビアホ−ルが形成された絶縁膜の表面に、当
該絶縁膜とはエッチング選択比の異なる薄膜を形成し、
前記薄膜の表面に上部絶縁膜を形成するようにしてもよ
い。ここで前記上部絶縁膜としてはフッ素添加カ−ボン
膜や塗布膜が用いられる。Further, the present invention provides a step of forming an insulating film on an object to be processed, a step of etching a via hole in the insulating film, and a step of forming an insulating film on the surface of the insulating film on which the via hole is formed. Forming an upper insulating film having a different etching selectivity, and etching a groove for forming a wiring by embedding a metal in the upper insulating film so as to contact at least a part of the via hole. A step of performing etching for a predetermined time after the etching of the upper insulating film to remove the upper insulating film deposited in the via hole by etching. At this time, a thin film having a different etching selectivity from the insulating film is formed on the surface of the insulating film on which the via hole is formed,
An upper insulating film may be formed on the surface of the thin film. Here, a fluorine-added carbon film or a coating film is used as the upper insulating film.

【００１２】[0012]

【発明の実施の形態】先ず本発明方法の概要について図
１に基づいて説明する。本発明方法は被処理体をなす基
板２に絶縁膜例えばＳｉＯ2 膜３を成膜し、当該ＳｉＯ
2 膜３にビアホ−ル３１をエッチングした後、ＳｉＯ2
膜３の上面に、埋め込み特性の悪い成膜材料を用いて上
部絶縁膜例えばＣＦ膜４を成膜し、次いでＣＦ膜４に溝
４１をエッチングして溝４１とビアホ−ル３１とが一体
となったデュアルダマシン形状を製造するものである。
この方法では埋め込み特性の悪い成膜材料を用いること
により、ビアホ−ル３１内へのＣＦ膜の埋め込みを抑え
ながらＳｉＯ2 膜３の上面にＣＦ膜４が成膜されるの
で、続いて溝４１をエッチングすれば前記デュアルダマ
シン形状を容易に形成することができる。ここで溝４１
とは銅（Ｃｕ）やアルミニウム（Ａｌ）等の配線層を形
成するために当該金属を埋め込むためのものであり、ビ
アホ−ル３１とは上下の配線層を接続するために金属を
埋め込むためのものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of the method of the present invention will be described with reference to FIG. According to the method of the present invention, an insulating film, for example, an SiO 2 film 3 is formed on a substrate 2 as an object to be processed, and the SiO 2 film 3 is formed.
2 After the via hole 31 is etched in the film 3, SiO 2
An upper insulating film, for example, a CF film 4 is formed on the upper surface of the film 3 using a film-forming material having a poor filling property, and then the groove 41 is etched in the CF film 4 so that the groove 41 and the via hole 31 are integrated. To produce a new dual damascene shape.
In this method, the CF film 4 is formed on the upper surface of the SiO 2 film 3 while suppressing the filling of the CF film into the via hole 31 by using a film forming material having poor filling characteristics. By etching, the dual damascene shape can be easily formed. Here the groove 41
Is used to embed the metal to form a wiring layer such as copper (Cu) or aluminum (Al). The via hole 31 is used to embed the metal to connect the upper and lower wiring layers. Things.

【００１３】続いて本発明によりＳｉＯ2 膜とＣＦ膜と
を積層し、ＳｉＯ2 膜にビアホ−ル、ＣＦ膜に溝を夫々
形成した半導体装置を製造する場合を例にして図２〜５
に基づいて具体的に説明する。先ず図２（ａ）に示すよ
うに、基板２の表面に例えば７０００オングストロ−ム
程度の厚さのＳｉＯ2 膜３を形成する。このＳｉＯ2膜
３は例えばＥＣＲ（電子サイクロトロン共鳴）を利用し
たプラズマ処理装置において成膜ガスをプラズマ化する
ことにより形成される。Next, an example of manufacturing a semiconductor device in which a SiO 2 film and a CF film are laminated and a via hole is formed in the SiO 2 film and a groove is formed in the CF film according to the present invention will be described with reference to FIGS.
This will be specifically described based on the following. First, as shown in FIG. 2A, an SiO 2 film 3 having a thickness of, for example, about 7000 Å is formed on the surface of the substrate 2. The SiO 2 film 3 is formed, for example, by turning a film forming gas into plasma in a plasma processing apparatus using ECR (Electron Cyclotron Resonance).

【００１４】ここで前記プラズマ処理装置について図６
により簡単に説明する。この装置では第１の真空室５１
と第２の真空室５２とからなる真空容器５の内部には、
高周波電源部５３から導波管５４及び透過窓５５を介し
て例えば２．４５ＧＨｚの高周波（マイクロ波）が供給
されると共に、第１の真空室５１の周囲と第２の真空室
５２の下部側に夫々設けられた主電磁コイル５６と補助
電磁コイル５７とにより、第１の真空室５１から第２の
真空室５２に向かい、ＥＣＲポイントＰ付近にて磁場の
強さが８７５ガウスとなる磁場が形成される。こうして
磁場とマイクロ波との相互作用により前記ＥＣＲポイン
トＰにて電子サイクロトロン共鳴が生じる。FIG. 6 shows the plasma processing apparatus.
This will be described more simply. In this apparatus, the first vacuum chamber 51
And a second vacuum chamber 52, inside the vacuum vessel 5,
A high frequency (microwave) of, for example, 2.45 GHz is supplied from a high frequency power supply unit 53 via a waveguide 54 and a transmission window 55, and the periphery of the first vacuum chamber 51 and the lower side of the second vacuum chamber 52. A magnetic field having a magnetic field strength of 875 gauss near the ECR point P from the first vacuum chamber 51 to the second vacuum chamber 52 is generated by the main electromagnetic coil 56 and the auxiliary electromagnetic coil 57 provided in It is formed. Thus, electron cyclotron resonance occurs at the ECR point P due to the interaction between the magnetic field and the microwave.

【００１５】この装置にてＳｉＯ2 膜を形成するときに
は、第２の真空室５２に設けられ、上面が静電チャック
として構成された載置台６１に基板２をなす半導体ウエ
ハＷを載置すると共に、当該載置台６１に高周波電源部
６２よりバイアス電圧を印加する。そして真空容器５内
を排気管５８を介して排気しながら、第１の真空室５１
にプラズマガス供給管６３を介してプラズマガス例えば
アルゴン（Ａｒ）ガス及び酸素（Ｏ2 ）ガスを夫々１５
０ｓｃｃｍ，１２０ｓｃｃｍの流量で導入すると共に、
第２の真空室５２に成膜ガス供給部６４を介して成膜ガ
ス例えばＳｉＨ4 ガスを７０ｓｃｃｍの流量で導入し、
当該成膜ガスを前記電子サイクロトロン共鳴によりプラ
ズマ化することにより、ＳｉＯ2 膜３を形成する。When an SiO 2 film is formed by this apparatus, a semiconductor wafer W constituting the substrate 2 is placed on a mounting table 61 provided in a second vacuum chamber 52 and having an upper surface formed as an electrostatic chuck. Then, a bias voltage is applied to the mounting table 61 from the high frequency power supply unit 62. Then, the first vacuum chamber 51 is evacuated from the vacuum chamber 5 through the exhaust pipe 58.
Plasma gas such as argon (Ar) gas and oxygen (O 2 ) gas through the plasma gas supply pipe 63 respectively.
At a flow rate of 0 sccm and 120 sccm,
A film forming gas, for example, a SiH 4 gas is introduced into the second vacuum chamber 52 through a film forming gas supply unit 64 at a flow rate of 70 sccm,
The film forming gas is converted into plasma by the electron cyclotron resonance to form the SiO 2 film 3.

【００１６】次いでＳｉＯ2 膜３にビアホ−ル３１を形
成する処理を行う。つまり先ず図２（ｂ）に示すよう
に、ＳｉＯ2 膜３の上面にレジスト７１を塗布して所定
のビアホ−ルパタ−ン形状を露光し、現像する。続いて
図２（ｃ）に示すように図示しないエッチング装置に
て、炭素（Ｃ）とフッ素（Ｆ）とを含む化合物のガス
（以下「ＣＦ系ガス」という）例えばＣＦ4 ガスやＣ4
Ｆ8 ガス等をエッチングガスとして用いて、ＳｉＯ2 膜
３に例えば直径０．５μｍ程度の円筒状のビアホ−ル３
１をエッチングした後、図２（ｄ）に示すようにＯ2 ガ
スや水素（Ｈ2 ）ガスを用いてレジスト７１を灰化して
除去する。Next, a process for forming a via hole 31 in the SiO 2 film 3 is performed. That is, first, as shown in FIG. 2B, a resist 71 is applied on the upper surface of the SiO 2 film 3, and a predetermined via hole pattern is exposed and developed. Subsequently, as shown in FIG. 2C, a gas of a compound containing carbon (C) and fluorine (F) (hereinafter referred to as a “CF-based gas”) such as CF 4 gas or C 4
By using F 8 gas or the like as an etching gas, a cylindrical via hole 3 having a diameter of, for example, about 0.5 μm is formed on the SiO 2 film 3.
After etching 1, the resist 71 is ashed and removed using an O 2 gas or a hydrogen (H 2 ) gas as shown in FIG.

【００１７】次にビアホ−ル３１が形成されたＳｉＯ2
膜３の表面に密着層を形成する処理を行う（図３
（ａ），（ｂ）参照）。この密着層はＳｉＯ2 膜３と後
述するＣＦ膜４との間の膜剥がれを抑えるためにこれら
の間に介装される層であり、この例では例えば１００オ
ングストロ−ム程度の厚さの窒化シリコン膜（以下「Ｓ
ｉＮ膜」という）８１と炭化ケイ素膜（以下「ＳｉＣ
膜」という）８２とをこの順で積層して形成される。こ
こで前記ＳｉＮ膜８１は窒素（Ｎ2 ）とケイ素（Ｓｉ）
とを含む膜であり、前記ＳｉＣ膜８２はＣとＳｉとを含
む膜であって、この例ではＳｉＮ膜８１はＮの原子数に
対するＳｉの原子数の比が１以上のものを用いることが
望ましい。またここでいうＳｉＮ膜やＳｉＣ膜はＳｉと
Ｎとの比やＳｉとＣとの比が１対１であることを意味す
るものではない。Next, the SiO 2 on which the via hole 31 is formed is formed.
A process for forming an adhesion layer on the surface of the film 3 is performed (FIG. 3).
(See (a) and (b)). This adhesion layer is a layer interposed between the SiO 2 film 3 and a CF film 4 to be described later in order to suppress film peeling. In this example, a nitride film having a thickness of about 100 Å is used. Silicon film (hereinafter "S
iN film) 81 and a silicon carbide film (hereinafter referred to as “SiC film”).
82) are laminated in this order. Here, the SiN film 81 is made of nitrogen (N 2 ) and silicon (Si).
The SiC film 82 is a film containing C and Si, and in this example, the SiN film 81 may have a ratio of the number of Si atoms to the number of N atoms of 1 or more. desirable. Further, the SiN film and the SiC film here do not mean that the ratio of Si to N or the ratio of Si to C is 1: 1.

【００１８】前記ＳｉＮ膜８１やＳｉＣ膜８２は例えば
前記プラズマ処理装置にて成膜され、ＳｉＮ膜８１は、
プラズマガス例えばＡｒガスと、成膜ガス例えばＳｉＨ
4 ガス及びＮ2 ガスとを、夫々２００ｓｃｃｍ，１０ｓ
ｃｃｍ，６．５ｓｃｃｍの流量で導入し、マイクロ波電
力２．４ｋＷ（高周波電源部５３），バイアス電力０ｋ
Ｗ（高周波電源部６２），基板温度３５０℃の下、前記
成膜ガスをプラズマ化することにより形成される（図３
（ａ）参照）。またＳｉＣ膜８２は、プラズマガス例え
ばＡｒガスと、成膜ガス例えばＳｉＨ4 ガス及びＣ2 Ｈ
4 ガスとを、夫々２００ｓｃｃｍ，１０ｓｃｃｍ，１５
ｓｃｃｍの流量で導入し、マイクロ波電力２．４ｋＷ，
バイアス電力０ｋＷ，基板温度３５０℃の下、前記成膜
ガスをプラズマ化することにより形成される（図３
（ｂ）参照）。The SiN film 81 and the SiC film 82 are formed by, for example, the plasma processing apparatus.
Plasma gas such as Ar gas and film forming gas such as SiH
4 gas and N 2 gas, 200 sccm and 10 s, respectively
ccm, 6.5 sccm, microwave power of 2.4 kW (high frequency power supply unit 53), bias power of 0 k
The film is formed by turning the film forming gas into a plasma under the condition of W (high frequency power supply 62) and the substrate temperature of 350 ° C. (FIG. 3)
(See (a)). The SiC film 82 is formed of a plasma gas such as Ar gas, a film forming gas such as SiH 4 gas and C 2 H
4 gas, 200 sccm, 10 sccm, 15 sc
Introduced at a flow rate of sccm, microwave power 2.4 kW,
It is formed by turning the film forming gas into plasma under a bias power of 0 kW and a substrate temperature of 350 ° C. (FIG. 3)
(B)).

【００１９】続いて図３（ｃ）に示すように密着層の上
面にＣＦ膜４を形成する処理を行う。つまり例えば前記
プラズマ処理装置において、成膜ガスとしてＣとＦとの
化合物であって埋め込み特性の悪い成膜材料例えばヘキ
サフルオロベンゼン（Ｃ6 Ｆ6 ）ガスを用いて、当該成
膜ガスをプラズマ化することにより形成される。この時
の成膜条件は、プラズマガス例えばＡｒガスとＣ6 Ｆ6
ガスの流量が夫々９０ｓｃｃｍ，４０ｓｃｃｍ，マイク
ロ波電力が２．４ｋＷ，バイアス電力が０ｋＷ，基板温
度が３００℃〜３５０℃である。Subsequently, as shown in FIG. 3C, a process for forming a CF film 4 on the upper surface of the adhesion layer is performed. That is, for example, in the plasma processing apparatus, a film forming material having a poor filling property, for example, a hexafluorobenzene (C 6 F 6 ) gas, which is a compound of C and F, is used as the film forming gas, It is formed by doing. The film forming conditions at this time are as follows: a plasma gas such as Ar gas and C 6 F 6
The gas flow rates are 90 sccm and 40 sccm, the microwave power is 2.4 kW, the bias power is 0 kW, and the substrate temperature is 300 ° C. to 350 ° C.

【００２０】このようにＣ6 Ｆ6 ガスを用いてＣＦ膜を
成膜すると、Ｃ6 Ｆ6 ガスはベンゼン環を有する化合物
（芳香族化合物）のガスであって分子が大きく、しかも
結合が強いので、成膜時には大きな分子構造を維持した
状態で堆積していくと推察される。このためＣＦ膜４は
図７（ａ）に示すようにビアホ−ル３１の周囲から内側
に迫り出していくように堆積していって徐々にビアホ−
ル３１の間口を狭めていき、結局この間口を塞いでしま
って（図７（ｂ）参照）、ビアホ−ル３１の内部にはＣ
Ｆ膜が埋め込まれない状態となる。この際バイアス電力
を印加していないので、成膜時にプラズマイオンがウエ
ハＷに引き込まれることがなく、さらにＣＦ膜の埋め込
み特性が悪くなり、こうしてビアホ−ル３１への埋め込
みを抑えながら、密着層の上面に例えば７０００オング
ストロ−ムの厚さのＣＦ膜４が形成される。なお前記密
着層の成膜においても、バイアス電力を印加せず、しか
も密着層の厚さは合わせて２００オングストロ−ムとか
なり薄いので、ビアホ−ル３１への密着層の堆積が抑え
られる。[0020] In this way the formation of the CF film using the C 6 F 6 gas, C 6 F 6 gas is a compound having a benzene ring (the aromatic compound) larger molecule a gas, yet strong bond Therefore, it is presumed that the film is deposited while maintaining a large molecular structure during film formation. Therefore, the CF film 4 is deposited so as to protrude inward from the periphery of the via hole 31 as shown in FIG.
The frontage of the vial 31 is narrowed, and eventually the frontage is closed (see FIG. 7B).
The F film is not buried. At this time, since no bias power is applied, plasma ions are not drawn into the wafer W during film formation, and the burying characteristics of the CF film are further deteriorated. A CF film 4 having a thickness of, for example, 7,000 angstroms is formed on the upper surface of the substrate. In the formation of the adhesion layer, no bias power is applied, and the thickness of the adhesion layer is as thin as 200 angstroms. Therefore, the deposition of the adhesion layer on the via hole 31 can be suppressed.

【００２１】次いで図３（ｄ）に示すようにＣＦ膜４の
上面に例えばＳｉＣ膜からなるハ−ドマスク８３を形成
する処理を行う。このハ−ドマスク８３は、ＣＦ膜のエ
ッチングにはＯ2 ガスやＨ2 ガスをエッチングガスとし
て用いるが、通常のレジストは有機物であってこれらの
ガスで灰化されてしまうため、エッチングの際レジスト
の変わりにマスクとして用いられるものであり、ＣＦ膜
とレジストとの間に介装され、Ｏ2 ガスやＨ2 ガスによ
って灰化されない無機系の膜例えばＳｉＮ膜やＳｉＣ膜
により構成される。Next, as shown in FIG. 3D, a process of forming a hard mask 83 made of, for example, a SiC film on the upper surface of the CF film 4 is performed. The hard mask 83 uses an O 2 gas or an H 2 gas as an etching gas for etching the CF film. However, a normal resist is an organic substance and is ashed by these gases. Instead of this, it is used as a mask, and is formed of an inorganic film, such as a SiN film or a SiC film, which is interposed between the CF film and the resist and is not ashed by O 2 gas or H 2 gas.

【００２２】このハ−ドマスク８３は、例えば前記プラ
ズマ処理装置において、プラズマガス例えばＡｒガス
と、成膜ガス例えばＳｉＨ4 ガス及びＣ2 Ｈ4 ガスと
を、夫々２００ｓｃｃｍ，１０ｓｃｃｍ，１５ｓｃｃｍ
の流量で導入し、マイクロ波電力２．４ｋＷ，バイアス
電力０ｋＷ，基板温度３５０℃の下、前記成膜ガスをプ
ラズマ化することにより形成される。The hard mask 83 is formed, for example, by using a plasma gas such as an Ar gas and a film forming gas such as a SiH 4 gas and a C 2 H 4 gas in the above-described plasma processing apparatus at 200 sccm, 10 sccm and 15 sccm, respectively.
And a plasma power of 2.4 kW of microwave power, 0 kW of bias power, and a substrate temperature of 350 ° C.

【００２３】続いてＣＦ膜４に溝４１を形成する処理を
行う。つまり図４（ａ）に示すように、ＣＦ膜４の上面
にレジスト７２を塗布して所定の溝パタ−ン形状を露光
し、現像した後、図４（ｂ）に示すように図示しないエ
ッチング装置にて、ＣＦ系ガス例えばＣＦ4 ガスやＣ4
Ｆ8 ガス等をエッチングガスとして用いてハ−ドマスク
８３に溝８３ａをエッチングする。次いで図４（ｃ）に
示すように図示しないエッチング装置にて、Ｏ2 ガスや
Ｈ2 ガスをエッチングガスとし、ハ−ドマスク８３をマ
スクとして用いて、ＣＦ膜４に、例えば幅が１．０μｍ
程度であって、紙面に対して垂直な方向に延び、一部が
ビアホ−ル３１に接続する溝４１（図１参照）をエッチ
ングする。このときＯ2 ガスによりレジスト７２は灰化
されて除去される。Subsequently, a process for forming a groove 41 in the CF film 4 is performed. That is, as shown in FIG. 4A, a resist 72 is applied on the upper surface of the CF film 4 to expose and develop a predetermined groove pattern shape, and then developed, as shown in FIG. In the apparatus, CF-based gas such as CF 4 gas or C 4
Etching a groove 83a in Domasuku 83 - Ha using F 8 gas or the like as the etching gas. Then, as shown in FIG. 4C, the CF film 4 having a width of, for example, 1.0 μm is formed by an etching apparatus (not shown) using O 2 gas or H 2 gas as an etching gas and a hard mask 83 as a mask.
A groove 41 (see FIG. 1) extending in a direction perpendicular to the plane of the drawing and partially connecting to the via hole 31 is etched. At this time, the resist 72 is ashed and removed by the O 2 gas.

【００２４】この後図５に示すように溝４１とビアホ−
ル３１とに金属例えばＣｕを埋め込む処理を行う。つま
り例えば図５（ａ）に示すようにハ−ドマスク８３の表
面にＣｕ層８４を形成して、溝４１とビアホ−ル３１に
Ｃｕを埋め込む処理を行った後、図５（ｂ）に示すよう
に図示しないＣＭＰ（Ｃｈｅｍｉｃａｌ ｍｅｃｈａｎ
ｉｃａｌ ｐｏｌｉｓｈｉｎｇ）装置においてＣＭＰ
（研磨）処理を行い、不要なＣｕ層８４を研磨して除去
し、こうして溝４１とビアホ−ル３１とにＣｕが埋め込
まれた半導体装置が製造される。Thereafter, as shown in FIG.
A process of embedding a metal, for example, Cu into the metal 31 is performed. That is, for example, as shown in FIG. 5A, a Cu layer 84 is formed on the surface of the hard mask 83, and a process of burying Cu in the groove 41 and the via hole 31 is performed, and then, as shown in FIG. (Not shown) CMP (Chemical mechanic)
CMP in an electrical polishing machine
A (polishing) process is performed to remove unnecessary portions of the Cu layer 84 by polishing. Thus, a semiconductor device in which Cu is embedded in the groove 41 and the via hole 31 is manufactured.

【００２５】この方法では、既述のようにビアホ−ル３
１へのＳｉＮ膜８１やＳｉＣ膜８２の堆積が抑えられる
が、仮にビアホ−ル３１の底部に若干ＳｉＮ膜８１等が
付着したとしても付着量はかなり少ないので、溝４１の
エッチング時にＣＦ膜４から発生するＦによりエッチン
グされる。またビアホ−ル３１のクリ−ニングを別工程
にて行い、付着したＳｉＮ膜８１等を除去するようにし
てもよい。この際クリ−ニングガスとしてはＣ4 Ｆ8 ガ
スやＣＦ4 ガス等のＣＦ系ガスが用いられる。In this method, as described above, the via hole 3 is used.
Although the deposition of the SiN film 81 and the SiC film 82 on the substrate 1 can be suppressed, even if the SiN film 81 or the like slightly adheres to the bottom of the via hole 31, the amount of adhesion is considerably small. Is etched by F generated from. The via hole 31 may be cleaned in a separate step to remove the attached SiN film 81 and the like. At this time, a CF-based gas such as a C 4 F 8 gas or a CF 4 gas is used as a cleaning gas.

【００２６】本発明方法はＣ6 Ｆ6 ガス等の埋め込み特
性の悪い成膜材料に着目して成されたものであり、予め
ＳｉＯ2 膜３にビアホ−ル３１をエッチングしておき、
次いでＣ6 Ｆ6 ガスを成膜ガスとして用いてＣＦ膜４の
成膜を行っているので、既述のようにビアホ−ル３１内
にＣＦ膜を埋め込むことなく、ＣＦ膜４を成膜すること
ができる。このため続いてＣＦ膜４に所定のパタ−ンで
溝４１をエッチングすれば容易にデュアルダマシン形状
を得ることができる。The method of the present invention focuses on a film-forming material such as C 6 F 6 gas having a poor embedding property. The via-hole 31 is etched in the SiO 2 film 3 in advance.
Next, since the CF film 4 is formed by using C 6 F 6 gas as a film forming gas, the CF film 4 is formed without embedding the CF film in the via hole 31 as described above. be able to. Therefore, a dual damascene shape can be easily obtained by subsequently etching the groove 41 in the CF film 4 with a predetermined pattern.

【００２７】このように本発明方法ではエッチング回数
及び金属膜形成回数が少ないので工程数が少なく、Ｓｉ
Ｏ2 膜３のエッチングとＣＦ膜４のエッチングを夫々独
立して行い、しかも従来の方法を用いることができるの
で、安定した操作を行うことができる。従って複雑なデ
ュアルダマシン形状を有する半導体装置を簡易な手法で
製造することができるので、スル−プットを向上させる
ことができ、結果としてコストダウンを図ることができ
る。As described above, in the method of the present invention, the number of steps is small because the number of times of etching and the number of times of forming the metal film are small.
Since the etching of the O 2 film 3 and the etching of the CF film 4 are performed independently and the conventional method can be used, a stable operation can be performed. Therefore, a semiconductor device having a complicated dual damascene shape can be manufactured by a simple method, so that the throughput can be improved, and as a result, the cost can be reduced.

【００２８】以上において上述の例では配線となる溝４
１が形成される上部絶縁膜はＣＦ膜４とし、ビアホ−ル
３１が形成される絶縁膜はＳｉＯ2 膜３としたが、半導
体装置では配線間の絶縁膜が低誘電率であればデバイス
を小さくすることできるので、このような構成も有効で
ある。In the above, in the above-described example, the groove 4 serving as a wiring
Although the upper insulating film on which 1 is formed is the CF film 4 and the insulating film on which the via hole 31 is formed is the SiO 2 film 3, in a semiconductor device, if the insulating film between wirings has a low dielectric constant, the device is not used. Such a configuration is also effective because it can be made smaller.

【００２９】また本発明は、図８に示すように、溝４１
が形成される上部絶縁膜のみならずビアホ−ル９１が形
成される絶縁膜もＣＦ膜とした構成の半導体装置の製造
に適用してもよく、この場合には絶縁膜として比誘電率
の低いＣＦ膜を用いているので半導体装置全体の比誘電
率をさらに低くすることができる。またこのような半導
体装置は同種の絶縁膜を積層しているので両者の間の密
着性が大きく、両者の間の膜剥がれを抑えるための密着
層は無くても良い。The present invention is also applicable to the case where the groove 41 is provided as shown in FIG.
Not only the upper insulating film on which the via hole 91 is formed but also the insulating film on which the via hole 91 is formed may be applied to the manufacture of a semiconductor device having a CF film. In this case, the insulating film has a low relative dielectric constant. Since the CF film is used, the relative dielectric constant of the entire semiconductor device can be further reduced. In addition, since such a semiconductor device is formed by laminating insulating films of the same kind, the adhesion between the two is large, and the adhesion layer for suppressing film peeling between the two may be omitted.

【００３０】以上において本発明では、溝が形成される
上部絶縁膜はＣＦ膜に限定されるものではなく、ビアホ
−ル内を埋め込むことのない埋め込み特性の悪い絶縁膜
であればいかなる絶縁膜も用いることができる。このよ
うな絶縁膜としては、例えば有機ＳＯＧ（Ｓｐｉｎ ｏ
ｎ Ｇｌａｓｓ）膜やＨＳＱ（Ｈｙｄｒｏｇｅｎ Ｓｉ
ｌｓｅｓｑｕｉｏｘａｎｅ）膜、ＢＣＢ（Ｂｉｓｂｅｎ
ｚｏｃｙｃｌｏｂｕｔｅｎｅ）膜、ポリイミド膜、Ｆ添
加ポリイミド膜、フッ化ポリアリルエ−テル、テフロ
ン、サイトップ等の低誘電率の塗布膜やパリレン、メチ
ルシラン系を用いた絶縁膜、例えばＦｌｏｗｆｉｌｌ
（Ｔｒｉｋｏｎ ＴｅｃｈｎｏｌｏｇｉｅｓＬｔｄ．社
製）等を用いても良い。メチルシラン系を用いた絶縁膜
に対しては「１９９８ ＤＵＭＩＣ Ｃｏｎｆｅｒｅｎ
ｃｅ Ｐ３１１」、パリレンについては「ＳＥＭＩＣＯ
ＮＤＵＣＴＯＲ ＩＮＴＥＲＮＡＴＩＯＮＡＬ Ｊｕｎ
ｅ９６ Ｐ２１１」に詳細が記されている。ここで塗布
膜は、ウエハを回転させた状態で、ウエハ表面に前記有
機ＳＯＧ膜等の高分子材料を供給し、回転の遠心力を利
用して前記高分子材料をウエハの表面全体に拡散させて
塗布した後、加熱により固めることにより形成される
が、この場合には高い表面張力を有する溶剤を用いた
り、回転数を上げる等の調節によりビアホ−ル内を埋め
込むことなく塗布膜を形成することができる。As described above, in the present invention, the upper insulating film in which the groove is formed is not limited to the CF film, and any insulating film which does not bury the inside of the via hole and has poor filling characteristics can be used. Can be used. As such an insulating film, for example, an organic SOG (Spin o
n Glass) film or HSQ (Hydrogen Si)
lsesquioxane) membrane, BCB (Bisben)
(Zocyclobutene) film, polyimide film, F-doped polyimide film, low dielectric constant coating film such as polyallyl ether, Teflon, Cytop, etc., or insulating film using parylene or methylsilane, such as Flowfill
(Trikon Technologies Ltd.) or the like may be used. For an insulating film using a methylsilane-based compound, see “1998 DUMIC Conference”.
ce P311 ”and Parylene“ SEMICO
NDUCTOR INTERNATIONAL JUN
e96 P211 ". Here, the coating film supplies the polymer material such as the organic SOG film to the wafer surface in a state where the wafer is rotated, and diffuses the polymer material over the entire surface of the wafer by using the centrifugal force of rotation. It is formed by heating and then hardening by heating. In this case, a coating film is formed without embedding the inside of the via hole by using a solvent having a high surface tension or by adjusting the number of revolutions. be able to.

【００３１】ここで上部絶縁膜として塗布膜を用いる場
合について、ビアホ−ルが形成される絶縁膜（以下「下
部絶縁膜」という）をＳｉＯ2 膜３、溝が形成される上
部絶縁膜をＳｉＬＫ膜（Ｄａｗ Ｃｈｅｍｉｃａｌ社の
登録商標）１００により形成した半導体装置を例にして
図９により具体的に説明する。[0031] For the case of using the coating film where the upper insulating film, the via hole - insulating film Le is formed (hereinafter, "lower insulating film" hereinafter) of the SiO 2 film 3, the upper insulating film having a groove formed SiLK FIG. 9 illustrates a specific example of a semiconductor device formed by a film (registered trademark of Daw Chemical Company) 100.

【００３２】図９（ａ）は基板２の上にＳｉＯ2 膜３を
成膜し、当該ＳｉＯ2 膜３にビアホ−ル３１を形成した
状態を示しており、ＳｉＯ2 膜３やビアホ−ル３１は上
述の実施の形態と同様の方法で形成される。次に図９
（ｂ）に示すようにＳｉＯ2 膜３の表面にＳｉＬＫ膜１
００を形成する工程を行う。ここでこの例のように下部
絶縁膜としてＳｉＯ2 膜３、上部絶縁膜としてＳｉＬＫ
膜１００を用いる場合には、ＳｉＯ2 膜とＳｉＬＫ膜と
は密着性が良いので両者の間に密着層を設けなくてもよ
い。[0032] FIG. 9 (a) forming a SiO 2 film 3 on the substrate 2, via hole in the SiO 2 film 3 - shows a state of forming a Le 31, SiO 2 film 3 and the via hole - Le 31 is formed in the same manner as in the above-described embodiment. Next, FIG.
As shown in (b), the SiLK film 1 is formed on the surface of the SiO 2 film 3.
00 is performed. Here, as in this example, a SiO 2 film 3 as a lower insulating film and SiLK as an upper insulating film.
When the film 100 is used, the adhesion between the SiO 2 film and the SiLK film is good, so that there is no need to provide an adhesion layer between the two.

【００３３】ＳｉＬＫ膜の成膜について図１０により説
明すると、先ず例えば図１０（ａ）に示すように、ウエ
ハＷを水平方向に回転可能な保持部材１１０に保持させ
た状態で、当該ウエハＷの表面にＳｉＬＫ膜の成膜材料
と当該成膜材料の溶剤とを含む塗布材料１１１を供給
し、次いで図１０（ｂ）に示すように、ウエハＷを水平
方向に回転させることにより、回転の遠心力で前記塗布
材料１１１をウエハＷ表面全体に拡散させる。続いてウ
エハＷを、処理容器１１２の内部に加熱プレ−ト１１３
を備えたベ−ク装置に搬送して前記加熱プレ−ト１１３
の上に載置し、例えば１４０℃の温度にて所定時間ベ−
ク処理を行い、この処理により溶剤を蒸発させて除去す
る。この後ウエハＷを処理容器１１４の内部に加熱プレ
−ト１１５を備えた加熱装置に搬送して前記加熱プレ−
ト１１５の上に載置し、例えば４００℃の温度にて所定
時間キュア処理を行い、この処理により重合反応を起こ
させて塗布材料を固化させ、こうしてＳｉＬＫ膜１００
の成膜が行われる。この際キュア処理は熱処理炉にて行
うようにしてもよい。The formation of the SiLK film will be described with reference to FIG. 10. First, for example, as shown in FIG. 10A, the wafer W is held by a holding member 110 rotatable in the horizontal direction. A coating material 111 containing a film forming material for the SiLK film and a solvent for the film forming material is supplied to the surface, and then the wafer W is rotated in a horizontal direction as shown in FIG. The coating material 111 is spread over the entire surface of the wafer W by force. Subsequently, the wafer W is placed inside the processing vessel 112 by a heating plate 113.
The heating plate 113 is transported to a baking device provided with
And placed at a temperature of, for example, 140 ° C. for a predetermined time.
The solvent is evaporated to remove the solvent. Thereafter, the wafer W is transferred to a heating device provided with a heating plate 115 inside the processing vessel 114, and the heating plate is heated.
Is placed on the substrate 115 and subjected to a curing process at a temperature of, for example, 400 ° C. for a predetermined time, thereby causing a polymerization reaction to solidify the coating material, and thus to cure the SiLK film 100.
Is formed. At this time, the curing process may be performed in a heat treatment furnace.

【００３４】次いで図９（ｃ）に示すように、ＳｉＬＫ
膜１００の上面に例えばＳｉＯ2 膜膜からなるハ−ドマ
スク１０１を形成する処理を行った後、上述の実施の形
態と同様の方法にてＳｉＬＫ膜１００に溝を形成する処
理を行う。つまりＳｉＬＫ膜１００の上面にレジストを
塗布して所定の溝パタ−ン形状を露光し、現像した後、
Ｏ2 ガスやＨ2 ガスを等をエッチングガスとして用いて
ＳｉＬＫ膜１００に溝をエッチングする。そして溝とビ
アホ−ル３１とに金属例えばＣｕを埋め込む処理及びＣ
ＭＰ処理を行うことにより半導体装置が製造される。Next, as shown in FIG.
After performing a process of forming a hard mask 101 made of, for example, a SiO 2 film on the upper surface of the film 100, a process of forming a groove in the SiLK film 100 is performed in the same manner as in the above-described embodiment. That is, after applying a resist on the upper surface of the SiLK film 100 and exposing and developing a predetermined groove pattern shape,
The groove is etched in the SiLK film 100 by using O 2 gas, H 2 gas or the like as an etching gas. Then, a process of embedding a metal such as Cu into the groove and the via hole 31 and C
A semiconductor device is manufactured by performing the MP process.

【００３５】このようにＳｉＬＫ膜１００は塗布材料１
１１をウエハＷ上に塗布することにより形成されるが、
溶剤の表面張力を高くしたり、ウエハＷを高速で回転さ
せたり等といった塗布条件を選択することにより、例え
ば図１１（ａ）に示すように、塗布材料１１１をビアホ
−ル３１の間口を塞ぐように拡散させ、ビアホ−ル３１
に塗布材料１１１をほとんど埋め込ませない状態（図１
１（ｂ））でＳｉＬＫ膜１００を塗布することができ
る。このようにビアホ−ル３１内へのＳｉＬＫ膜１００
の付着量がかなり少ない場合には、ＳｉＬＫ膜１００の
エッチング工程にビアホ−ル３１内のＳｉＬＫ膜も除去
することができる。As described above, the SiLK film 100 is made of the coating material 1
11 is applied on the wafer W,
By selecting application conditions such as increasing the surface tension of the solvent or rotating the wafer W at a high speed, for example, as shown in FIG. 11A, the application material 111 closes the opening of the via hole 31. And diffused via hole 31
In which the coating material 111 is hardly embedded (FIG. 1)
1 (b)), the SiLK film 100 can be applied. Thus, the SiLK film 100 is inserted into the via hole 31.
In the case where the adhesion amount of SiLK is considerably small, the SiLK film in the via hole 31 can also be removed in the etching process of the SiLK film 100.

【００３６】この例のように塗布膜としてＳｉＬＫ膜を
用いる場合には、ハ−ドマスクとしては、図１２の一覧
表に示すように、ＳｉＯ2 膜の他、ＳｉＯＦ膜やＳｉＮ
膜、ＴｉＮ膜や、ＨＳＱ膜やＭＳＱ膜、有機ＳＯＧ膜、
ポ−ラスシリカ等の塗布膜を用いることができる。また
下部絶縁膜としては、ＳｉＯ2 膜の他、ＳｉＯＦ膜やＳ
ｉＮ膜等のＳｉを含む絶縁膜や、ＨＳＱ膜やＭＳＱ膜、
有機ＳＯＧ膜、ポ−ラスシリカ等の塗布膜を用いること
ができる。When an SiLK film is used as a coating film as in this example, as a hard mask, as shown in the table of FIG. 12, in addition to a SiO 2 film, a SiOF film or a SiN film is used.
Film, TiN film, HSQ film, MSQ film, organic SOG film,
A coating film of porous silica or the like can be used. As the lower insulating film, in addition to the SiO 2 film, a SiOF film or S
an insulating film containing Si such as an iN film, an HSQ film, an MSQ film,
An organic SOG film, a coating film of porous silica or the like can be used.

【００３７】また上部絶縁膜として用いられる塗布膜と
しては、上述のＳｉＬＫ膜の他に、既述のようにＢＣＢ
膜（Ｄａｗ Ｃｈｅｍｉｃａｌ社の登録商標）や有機Ｓ
ＯＧ膜、ＨＳＱ膜やＭＳＱ膜（いずれもＤａｗ Ｃｈｅ
ｍｉｃａｌ社の登録商標）、ＦＬＡＲＥ膜（Ａｌｌｉｅ
ｄ Ｓｉｇｎａｌ社の登録商標）やポ−ラスシリカ等が
あり、これらのうちＢＣＢ膜、有機ＳＯＧ膜、ＨＳＱ
膜、ＭＳＱ膜、ＦＬＡＲＥ膜は、ＳｉＬＫ膜と同様に、
塗布材料をスピン塗布した後、ベ−ク処理及びキュア処
理を行うことにより成膜される。またポ−ラスシリカは
塗布材料をスピン塗布した後、エ−ジング処理により塗
布材料をゲル化させた後、溶媒を除去することにより成
膜される。As the coating film used as the upper insulating film, in addition to the SiLK film described above, BCB as described above is used.
Film (registered trademark of Daw Chemical Company) or organic S
OG film, HSQ film and MSQ film (Daw Che
trademark, a FLARE film (Allie)
d Signal (registered trademark) and porous silica, among which BCB film, organic SOG film, HSQ
The film, the MSQ film, and the FLARE film are similar to the SiLK film,
After spin-coating the coating material, a film is formed by performing a baking process and a curing process. Porous silica is formed by spin-coating the coating material, gelling the coating material by aging, and removing the solvent.

【００３８】これらの膜のハ−ドマスクやエッチングガ
ス、下部絶縁膜については図１２に夫々示す。つまりハ
−ドマスクについては、ＢＣＢ膜及びＦＬＡＲＥ膜にあ
っては、ＳｉＯ2 膜やＳｉＯＦ膜、ＳｉＮ膜、ＴｉＮ
膜、ＨＳＱ膜やＭＳＱ膜、有機ＳＯＧ膜、ポ−ラスシリ
カ等であり、ＨＳＱ膜やＭＳＱ膜にあってはフォトレジ
ストである。また有機ＳＯＧ膜やポ−ラスシリカにあっ
ては、これらの膜とフォトレジストとは反応してしまう
ため、ＳｉＯ2 膜の上面にフォトレジストを形成したも
のである。FIG. 12 shows a hard mask, an etching gas, and a lower insulating film of these films. That is, as for the hard mask, in the case of the BCB film and the FLARE film, the SiO 2 film, the SiOF film, the SiN film, and the TiN film are used.
Film, HSQ film or MSQ film, organic SOG film, porous silica, etc., and in the case of HSQ film or MSQ film, it is a photoresist. Further, in the case of an organic SOG film or porous silica, a photoresist is formed on the upper surface of the SiO 2 film because these films react with the photoresist.

【００３９】またエッチングガスについては、ＢＣＢ膜
及びＦＬＡＲＥ膜にあっては、Ｏ2ガスやＨ2 ガスであ
り、有機ＳＯＧ膜やＨＳＱ膜、ＭＳＱ膜、ポ−ラスシリ
カにあってはＣＦ系ガスである。さらに下部絶縁膜とし
ては、ＢＣＢ膜及びＦＬＡＲＥ膜にあっては、ＳｉＯ2
膜やＳｉＯＦ膜、ＳｉＮ膜等のＳｉを含む絶縁膜、ＨＳ
Ｑ膜やＭＳＱ膜、有機ＳＯＧ膜、ポ−ラスシリカ等であ
り、有機ＳＯＧ膜やＨＳＱ膜、ＭＳＱ膜、ポ−ラスシリ
カにあっては、ＳｉＬＫ膜、ＢＣＢ膜、ＦＬＡＲＥ膜、
ＣＦ膜、ＳｉＯ2 膜やＳｉＮ膜等である。また上部絶縁
膜として塗布膜を用いる場合においても、下部絶縁膜と
上部絶縁膜との組み合わせにより両者の間の密着性が小
さい場合には、下部絶縁膜と上部絶縁膜との間に密着層
を介装するようにしてもよい。The etching gas is O 2 gas or H 2 gas for the BCB film and FLARE film, and is CF gas for the organic SOG film, HSQ film, MSQ film and porous silica. is there. Further, as the lower insulating film, in the BCB film and the FLARE film, SiO 2 is used.
Film, SiOF film, insulating film containing Si such as SiN film, HS
Q film, MSQ film, organic SOG film, porous silica, etc. For organic SOG film, HSQ film, MSQ film, and porous silica, SiLK film, BCB film, FLARE film,
It is a CF film, a SiO 2 film, a SiN film, or the like. Further, even when a coating film is used as the upper insulating film, if the adhesion between the lower insulating film and the upper insulating film is small due to the combination of the lower insulating film and the upper insulating film, an adhesive layer is formed between the lower insulating film and the upper insulating film. You may make it interpose.

【００４０】ここで実際に下部絶縁膜が５０００オング
ストロ−ムの厚さのＳｉＯ2 膜、上部絶縁膜が５０００
オングストロ−ムの厚さのＳｉＬＫ膜であって、ビアホ
−ルが直径０．５μｍ、溝の幅が０．４μｍの半導体装
置を上述のプロセスで製造し、ＳＥＭ（走査電子顕微
鏡）によりビアホ−ルと溝の断面を観察したところ、ビ
アホ−ルへのＳｉＬＫ膜の埋め込みは見られず、デュア
ルダマシン形状が形成されていることが確認された。ま
た上部絶縁膜をＢＣＢ膜，ＦＬＡＲＥ膜、有機ＳＯＧ
膜、ＨＳＱ膜、ＭＳＱ膜、ポ−ラスシリカに変えて同様
に半導体装置を製造したところ、デュアルダマシン形状
が形成されていることが確認された。Here, the lower insulating film is actually an SiO 2 film having a thickness of 5000 Å, and the upper insulating film is
A semiconductor device having a thickness of Angstrom and having a via hole of 0.5 μm in diameter and a groove width of 0.4 μm, which is a SiLK film having a thickness of Å, is manufactured by the above-described process, and the via hole is formed by SEM (scanning electron microscope). When the cross section of the groove was observed, no embedding of the SiLK film in the via hole was observed, and it was confirmed that a dual damascene shape was formed. The upper insulating film is made of BCB film, FLARE film, organic SOG.
When a semiconductor device was similarly manufactured in place of the film, the HSQ film, the MSQ film, and the porous silica, it was confirmed that a dual damascene shape was formed.

【００４１】このように上部絶縁膜として塗布膜を用い
る場合においても、本発明方法により複雑なデュアルダ
マシン形状を有する半導体装置を簡易な手法で製造する
ことができる。As described above, even when the coating film is used as the upper insulating film, a semiconductor device having a complicated dual damascene shape can be manufactured by a simple method by the method of the present invention.

【００４２】続いて本発明の他の実施の形態について説
明する。本実施の形態は、下部絶縁膜と上部絶縁膜とが
異なる種類の絶縁膜であって、両者のエッチング選択比
が異なる場合には、上部絶縁膜を形成する際にビアホ−
ルの一部若しくは全部に上部絶縁膜が成膜されても、上
部絶縁膜のエッチングの際にエッチング時間をある程度
長くすれば、ビアホ−ル内の上部絶縁膜も除去できるこ
とを見出だしたことにより成されたものである。Next, another embodiment of the present invention will be described. In this embodiment mode, when the lower insulating film and the upper insulating film are different types of insulating films and the etching selectivity of both is different, a via hole is formed when forming the upper insulating film.
It has been found that even if the upper insulating film is formed on part or all of the hole, the upper insulating film in the via hole can be removed if the etching time is lengthened to a certain extent when etching the upper insulating film. It was made.

【００４３】この実施の形態について、下部絶縁膜をＳ
ｉＯ2 膜３、上部絶縁膜をＣＦ膜４により形成した半導
体装置を例にして図１３により具体的に説明する。図１
３（ａ）は上述の実施の形態と同様の方法により、基板
２の上にＳｉＯ2 膜３を成膜し、当該ＳｉＯ2 膜３にビ
アホ−ル３１を形成した後、ＳｉＯ2 膜３の上面に密着
層であるＳｉＮ膜８１とＳｉＣ膜８２を形成した状態を
示している。In this embodiment, the lower insulating film is made of S
A specific description will be given with reference to FIG. 13 using a semiconductor device in which the iO 2 film 3 and the upper insulating film are formed of the CF film 4 as an example. FIG.
3 by the same method as the form of (a) the above embodiment, the SiO 2 film 3 is formed on the substrate 2, via hole in the SiO 2 film 3 - after the formation of the Le 31, the SiO 2 film 3 The state where the SiN film 81 and the SiC film 82 which are the adhesion layers are formed on the upper surface is shown.

【００４４】そして密着層の上面にＣＦ膜４を成膜する
が、このＣＦ膜４は例えば前記プラズマ処理装置におい
て、プラズマガス例えばＡｒガスと、成膜ガス例えばＣ
4 Ｆ8 ガスとＣ2 Ｈ4 ガスを用いて、当該成膜ガスをプ
ラズマ化することにより形成される。この時の成膜条件
は、例えばＡｒガスとＣ4 Ｆ8 ガスとＣ2 Ｈ4 ガスの流
量が夫々１５０ｓｃｃｍ，４０ｓｃｃｍ，３０ｓｃｃ
ｍ，マイクロ波電力が２．７ｋＷ，バイアス電力が０ｋ
Ｗ，基板温度が３００℃〜３５０℃である。Then, a CF film 4 is formed on the upper surface of the adhesion layer, and the CF film 4 is formed by, for example, a plasma gas such as Ar gas and a film forming gas such as C
4 with reference to F 8 gas and C 2 H 4 gas, is formed by plasma the deposition gas. The film formation conditions at this time are, for example, that the flow rates of Ar gas, C 4 F 8 gas and C 2 H 4 gas are 150 sccm, 40 sccm, and 30 sccc, respectively.
m, microwave power 2.7 kW, bias power 0 k
W, the substrate temperature is 300 ° C. to 350 ° C.

【００４５】このようにＣＦ膜の成膜を行うと、Ｃ4 Ｆ
8 ガスはＣ6 Ｆ6 ガスよりも分子が小さいので、Ｃ6 Ｆ
6 ガスよりもビアホ−ル３１内に成膜されやすく、例え
ばビアホ−ル３１の底部や側壁の一部に付着してしま
い、ビアホ−ル３１の一部にＣＦ膜４が堆積した状態と
なる。When the CF film is formed as described above, C 4 F
Since 8 gas has smaller molecules than C 6 F 6 gas, C 6 F
The film is more easily formed in the via hole 31 than the six gases, and adheres to, for example, the bottom or a part of the side wall of the via hole 31, and the CF film 4 is deposited on a part of the via hole 31. .

【００４６】次いで図１３（ｂ）に示すように、上述の
実施の形態と同様に、ＣＦ膜４の上面への例えばＳｉＣ
膜からなるハ−ドマスク８３の形成と、レジスト７２の
塗布、露光、現像とを行った後、図１３（ｃ）に示すよ
うに、ＣＦ系ガスをエッチングガスとして用いてハ−ド
マスク８３をエッチングし、続いて図１３（ｄ）に示す
ようにＣＦ膜４のエッチングを行う。このＣＦ膜４のエ
ッチングは、図示しないエッチング装置にて、Ｏ2 ガス
やＨ2 ガスをエッチングガスとし、ハ−ドマスク８３を
マスクとして用いて行うが、この際エッチング時間はＣ
Ｆ膜４のエッチングに要する時間よりも所定時間長く設
定する。ここでＣＦ膜４のエッチングに要する時間は、
エッチングの終点を例えばＦやＣＦ系の発光分析により
確認して決定される。Next, as shown in FIG. 13B, similarly to the above-described embodiment, the upper surface of the CF
After forming a hard mask 83 made of a film and applying, exposing, and developing a resist 72, the hard mask 83 is etched using a CF-based gas as an etching gas, as shown in FIG. Then, the CF film 4 is etched as shown in FIG. The etching of the CF film 4 is performed by an etching apparatus (not shown) using O 2 gas or H 2 gas as an etching gas and a hard mask 83 as a mask.
The time is set to be longer than the time required for etching the F film 4 by a predetermined time. Here, the time required for etching the CF film 4 is as follows.
The end point of the etching is determined by confirming, for example, F or CF based emission analysis.

【００４７】このようにＣＦ膜４のエッチングが終了し
てからも所定時間続けてエッチングを行なうと、このい
わゆるオ−バ−エッチングによりビアホ−ル３１内に存
在するＣＦ膜４もエッチングされて除去される。この際
ビアホ−ル３１が形成されるＳｉＯ2 膜３とＣＦ膜４と
はエッチング選択比が異なるので、Ｏ2 ガスやＨ2 ガス
によりＳｉＯ2 膜３がエッチングされることはなく、こ
のオ−バ−エッチングによりビアホ−ル３１の側壁がエ
ッチングされ、ビアホ−ル形状が変化してしまうおそれ
はない。従ってＣＦ膜４のエッチング時間を調整するこ
とにより、ビアホ−ル３１内に付着したＣＦ膜の除去量
を調整することができる。このためＣＦ膜４の成膜時に
ビアホ−ル３１内の一部あるいは全部にＣＦ膜が堆積し
たとしても、デュアルダマシン形状を形成することがで
きる。When the etching is continued for a predetermined time after the etching of the CF film 4 is completed, the CF film 4 existing in the via hole 31 is also etched and removed by this so-called over-etching. Is done. At this time, since the SiO 2 film 3 on which the via hole 31 is formed and the CF film 4 have different etching selectivity, the SiO 2 film 3 is not etched by O 2 gas or H 2 gas. The side wall of the via hole 31 is etched by the bar etching, and there is no possibility that the via hole shape is changed. Therefore, by adjusting the etching time of the CF film 4, the removal amount of the CF film adhered in the via hole 31 can be adjusted. Therefore, a dual damascene shape can be formed even when the CF film is deposited on a part or all of the via hole 31 when the CF film 4 is formed.

【００４８】また本実施の形態は、上部絶縁膜が例えば
ＳｉＬＫ膜、ＢＣＢ膜、ＦＬＡＲＥ膜、有機ＳＯＧ膜、
ＨＳＱ膜、ＭＳＱ膜、ポ−ラスシリカ等の塗布膜や、パ
リレン、メチルシラン系の膜であって、下部絶縁膜が上
部絶縁膜とはエッチング選択比が異なる場合にも適用で
きる。In this embodiment, the upper insulating film is made of, for example, a SiLK film, a BCB film, a FLARE film, an organic SOG film,
The present invention can be applied to a coating film of HSQ film, MSQ film, porous silica, or the like, or a film of parylene or methylsilane, in which the lower insulating film has an etching selectivity different from that of the upper insulating film.

【００４９】ここで実際に絶縁膜が５０００オングスト
ロ−ムの厚さのＳｉＯ2 膜、上部絶縁膜が５０００オン
グストロ−ムの厚さのＣＦ膜であって、ビアホ−ルが直
径０．５μｍ、溝の幅が０．４μｍの半導体装置を、Ｃ
Ｆ膜のエッチング時間を通常の１．３倍にして上述のプ
ロセスにて製造し、ＳＥＭ（走査電子顕微鏡）により、
エッチング前のビアホ−ルと、エッチング後のビアホ−
ルと溝の断面を観察したところ、エッチング前にはビア
ホ−ルの底部と側壁にＣＦ膜が付着していたが、エッチ
ング後にはビアホ−ル内へのＣＦ膜の埋め込みやビアホ
−ルの変形は見られず、デュアルダマシン形状が形成さ
れていることが確認された。Here, the insulating film is actually a SiO 2 film having a thickness of 5000 angstroms, the upper insulating film is a CF film having a thickness of 5000 angstroms, and the via hole has a diameter of 0.5 μm and a groove. Semiconductor device having a width of 0.4 μm
The F film is manufactured by the above-described process with the etching time being 1.3 times the normal time, and is subjected to SEM (scanning electron microscope).
Via hole before etching and via hole after etching
Observation of the cross section of the hole and the groove revealed that the CF film had adhered to the bottom and side walls of the via hole before etching, but after etching, the CF film was buried in the via hole and the via hole was deformed. Was not observed, and it was confirmed that a dual damascene shape was formed.

【００５０】また上部絶縁膜をＳｉＬＫ膜、ＢＣＢ膜、
ＦＬＡＲＥ膜、有機ＳＯＧ膜、ＨＳＱ膜、ＭＳＱ膜、ポ
−ラスシリカに変えて同様に半導体装置を製造したとこ
ろ、溶剤やウエハＷの回転数を変えることにより、上部
絶縁膜のビアホ−ルへの埋め込み量が異なるものの、Ｓ
ｉＬＫ膜等は、ＳｉＯ2 膜とのエッチング時の選択比が
異なるので、ビアホ−ルの大部分に上部絶縁膜が堆積し
ている場合であっても、上部絶縁膜のエッチング時間を
長くすることにより、ビアホ−ルの形状の変化を抑えな
がらビアホ−ル内の上部絶縁膜を除去することができ、
デュアルダマシン形状が形成できることが確認された。The upper insulating film is made of a SiLK film, a BCB film,
When a semiconductor device was manufactured in the same manner as in the case of changing the FLARE film, the organic SOG film, the HSQ film, the MSQ film, and the porous silica, the upper insulating film was buried in the via hole by changing the solvent and the rotation speed of the wafer W. Although the amount is different, S
Since the selectivity of the iLK film and the like at the time of etching with the SiO 2 film is different, it is necessary to lengthen the etching time of the upper insulating film even when the upper insulating film is deposited on most of the via holes. Thereby, the upper insulating film in the via hole can be removed while suppressing the change in the shape of the via hole,
It was confirmed that a dual damascene shape could be formed.

【００５１】続いて本発明のさらに他の実施の形態につ
いて説明する。本実施の形態は、下部絶縁膜と上部絶縁
膜とのエッチング選択比がほとんど同じ場合であって
も、これらの絶縁膜とはエッチング選択比が異なる薄膜
を、下部絶縁膜と上部絶縁膜との界面に設ければ、ビア
ホ−ルの一部若しくは全部に上部絶縁膜が堆積していて
も、上部絶縁膜のエッチングの際にエッチング時間をあ
る程度長くすることにより、ビアホ−ルの形状を変化さ
せずに、ビアホ−ル内の上部絶縁膜も除去できることを
見出だしたことにより成されたものである。Next, still another embodiment of the present invention will be described. In this embodiment mode, even when the etching selectivity between the lower insulating film and the upper insulating film is almost the same, a thin film having a different etching selectivity from these insulating films is used for forming the thin film between the lower insulating film and the upper insulating film. If it is provided at the interface, even if the upper insulating film is deposited on part or all of the via hole, the shape of the via hole can be changed by extending the etching time to some extent when etching the upper insulating film. Without removing the upper insulating film in the via hole.

【００５２】この実施の形態について、下部絶縁膜をＣ
Ｆ膜９、上部絶縁膜をＣＦ膜４により形成した半導体装
置を例にして図１４及び図１５により具体的に説明す
る。図１４（ａ）は上述の実施の形態と同様の方法によ
り、基板２の上にＣＦ膜９を成膜した状態を示してお
り、このＣＦ膜９は例えば前記プラズマ処理装置におい
て、成膜ガス例えばＣ4 Ｆ8 ガスとＣ2 Ｈ4 ガスとをプ
ラズマ化することにより形成される。In this embodiment, the lower insulating film is made of C
A specific description will be given with reference to FIGS. 14 and 15 by taking a semiconductor device in which the F film 9 and the upper insulating film are formed by the CF film 4 as an example. FIG. 14A shows a state in which a CF film 9 is formed on the substrate 2 by a method similar to that of the above-described embodiment. For example, it is formed by turning C 4 F 8 gas and C 2 H 4 gas into plasma.

【００５３】次いで図１４（ｂ）に示すように、ＣＦ膜
９の上面への例えばＳｉＣ膜からなるハ−ドマスク８５
の形成と、レジスト７３の塗布、露光、現像とを行な
う。ここでハ−ドマスク８５は例えば前記プラズマ処理
装置において、成膜ガス例えばＳｉＨ4 ガス及びＣ2 Ｈ
4 ガスをプラズマ化することにより形成される。この後
図１４（ｃ）に示すように、ＣＦ系ガスをエッチングガ
スとして用いてハ−ドマスク８５をエッチングし、続い
てＯ2 ガスやＨ2 ガスをエッチングガスとして用いてＣ
Ｆ膜９にビアホ−ル９１をエッチングする。Next, as shown in FIG. 14B, a hard mask 85 made of, for example, a SiC film is formed on the upper surface of the CF film 9.
And the application, exposure, and development of a resist 73 are performed. Here, the hard mask 85 is formed by, for example, a film forming gas such as SiH 4 gas and C 2 H in the plasma processing apparatus.
It is formed by turning 4 gases into plasma. Thereafter, as shown in FIG. 14 (c), the hard mask 85 is etched using a CF-based gas as an etching gas, and then C 2 gas is etched using an O 2 gas or H 2 gas as an etching gas.
The via hole 91 is etched in the F film 9.

【００５４】次に図１５（ａ）に示すように、ハ−ドマ
スク８５の上面にＣＦ膜４を成膜するが、このＣＦ膜４
は上述の実施の形態と同様に、例えば前記プラズマ処理
装置において、プラズマガス例えばＡｒガスと、成膜ガ
ス例えばＣ4 Ｆ8 ガスとＣ2Ｈ4 ガスとを夫々１５０ｓ
ｃｃｍ，４０ｓｃｃｍ，３０ｓｃｃｍの流量で導入し、
マイクロ波電力２．７ｋＷ，バイアス電力０ｋＷ，基板
温度３００℃〜３５０℃の下で、成膜ガスをプラズマ化
することにより形成される。この成膜により既述のよう
に、例えばビアホ−ル９１の底部や側壁の一部にＣＦ膜
４が堆積した状態となる。Next, as shown in FIG. 15A, a CF film 4 is formed on the upper surface of the hard mask 85.
In the same manner as in the above-described embodiment, for example, in the above-described plasma processing apparatus, a plasma gas such as an Ar gas and a film forming gas such as a C 4 F 8 gas and a C 2 H 4 gas are each used for 150 seconds.
Introduced at a flow rate of ccm, 40sccm, 30sccm,
It is formed by turning a film forming gas into plasma under a microwave power of 2.7 kW, a bias power of 0 kW, and a substrate temperature of 300 ° C. to 350 ° C. By this film formation, as described above, for example, the CF film 4 is deposited on the bottom and a part of the side wall of the via hole 91.

【００５５】次いで図１５（ｂ）に示すように、上述の
実施の形態と同様に、ＣＦ膜４の上面への例えばＳｉＣ
膜からなるハ−ドマスク８３の形成と、レジスト７２の
塗布、露光、現像とを行なった後、ＣＦ系ガスによるハ
−ドマスク８３のエッチングと、Ｏ2 ガスやＨ2 ガスに
よるＣＦ膜４のエッチングとを行い、溝４１を形成する
（図１５（ｃ）参照）。この際ＣＦ膜４のエッチング時
間はＣＦ膜４のエッチングに要する時間よりも所定時間
長く設定する。Next, as shown in FIG. 15B, similarly to the above-described embodiment, the upper surface of the CF
After forming a hard mask 83 made of a film, applying, exposing, and developing a resist 72, etching of the hard mask 83 with a CF-based gas and etching of the CF film 4 with an O 2 gas or an H 2 gas. To form the groove 41 (see FIG. 15C). At this time, the etching time of the CF film 4 is set to be longer than the time required for etching the CF film 4 by a predetermined time.

【００５６】このようなオ−バ−エッチングを行うと、
ビアホ−ル９１内に存在するＣＦ膜４もエッチングされ
て除去される。この際下部絶縁膜と上部絶縁膜とは共に
ＣＦ膜により形成されているので両者のエッチング選択
比は同じであるが、両者の界面にＳｉＣ膜よりなるハ−
ドマスク８５が設けられており、このハ−ドマスク８５
とＣＦ膜とはエッチング選択比が異なるので、このハ−
ドマスク８５により下方側のＣＦ膜９のエッチングが妨
げられる。またＣＦ膜４は垂直性のよいエッチングが行
われるので、ビアホ−ル９１内のＣＦ膜４のエッチング
のみが進行し、ビアホ−ル９１の側壁が削られるおそれ
はない。さらにビアホ−ル９１の底部はＣＦ膜とはエッ
チング選択比が異なる基板２であるため、当該ビアホ−
ル９１の底部がエッチングにより削られるおそれもな
い。When such over-etching is performed,
The CF film 4 existing in the via hole 91 is also removed by etching. At this time, since both the lower insulating film and the upper insulating film are formed of CF films, their etching selectivity is the same.
A hard mask 85 is provided.
Since the etching selectivity differs between the CF film and the CF film,
The mask 85 prevents etching of the lower CF film 9. Further, since the CF film 4 is etched with good verticality, only the etching of the CF film 4 in the via hole 91 proceeds, and there is no possibility that the side wall of the via hole 91 is cut. Further, the bottom of the via hole 91 is the substrate 2 having an etching selectivity different from that of the CF film.
There is no danger that the bottom of the screw 91 will be scraped off by etching.

【００５７】従ってこのオ−バ−エッチングによりビア
ホ−ル形状が変化させることなく、ビアホ−ル９１内に
存在するＣＦ膜４のみを除去することができ、ＣＦ膜４
のエッチング時間を調整することにより、ビアホ−ル９
１内に付着したＣＦ膜の除去量を調整することができ
る。このため下部絶縁膜と上部絶縁膜とが同じ種類の絶
縁膜である場合に、上部絶縁膜の成膜時にビアホ−ル内
に上部絶縁膜が埋め込まれたとしても、デュアルダマシ
ン形状を形成することができる。Therefore, only the CF film 4 existing in the via hole 91 can be removed without changing the via hole shape by this over-etching.
By adjusting the etching time of the via hole 9,
It is possible to adjust the removal amount of the CF film adhered to the inside 1. Therefore, when the lower insulating film and the upper insulating film are the same type of insulating film, a dual damascene shape should be formed even if the upper insulating film is embedded in the via hole when the upper insulating film is formed. Can be.

【００５８】ここで上述の例では、下部絶縁膜と上部絶
縁膜との界面に設けられる、これらの絶縁膜とはエッチ
ング選択比が異なる絶縁膜として、絶縁膜のハ−ドマス
クを利用したので、前記エッチング選択比が異なる絶縁
膜を新たに形成しなくてもよいという利点があるが、こ
の実施の形態では前記エッチング選択比が異なる絶縁膜
をカバ−膜としてハ−ドマスクと別個に形成するように
してもよい。Here, in the above-described example, a hard mask of the insulating film is used as an insulating film provided at the interface between the lower insulating film and the upper insulating film and having an etching selectivity different from these insulating films. Although there is an advantage that it is not necessary to newly form an insulating film having a different etching selectivity, in this embodiment, an insulating film having a different etching selectivity is formed separately from a hard mask as a cover film. It may be.

【００５９】またカバ−膜は、例えば図１６（ａ）に示
すように、下部絶縁膜であるＣＦ膜９の表面全体つまり
ビアホ−ル９１の側壁や底部の表面全体を覆うように形
成するようにしてもよい。ここでカバ−膜２００は例え
ば下部絶縁膜であるＣＦ膜とはエッチング選択比の異な
るＳｉＮ膜やＳｉＣ膜などにより形成され、例えば上述
のプラズマ成膜装置において所定の成膜ガスをプラズマ
化することにより形成される。この際所定のバイアス電
力を印加することにより、ビアホ−ル９１の側壁や底部
へカバ−膜２００を成膜することができる。The cover film is formed so as to cover the entire surface of the CF film 9 as the lower insulating film, that is, the entire surface of the side wall and the bottom of the via hole 91 as shown in FIG. It may be. Here, the cover film 200 is formed of, for example, a SiN film or a SiC film having an etching selectivity different from that of the CF film as the lower insulating film. Formed by At this time, by applying a predetermined bias power, the cover film 200 can be formed on the side wall and the bottom of the via hole 91.

【００６０】この場合には、引き続いて図１６（ｂ），
（ｃ）に示すように、上述の実施の形態と同様に、上部
絶縁膜であるＣＦ膜４をカバ−膜２００の表面に成膜
し、次いでＣＦ膜４のオ−バ−エッチングを行って、溝
４１の形成とＣＦ膜４の成膜時にビアホ−ル９１の内部
に堆積したＣＦ膜４の除去を行なった後、図１６（ｄ）
に示すように、エッチングガス例えばＣＦ4 やＣ4 Ｆ8
ガスを用いてカバ−膜２００の除去を行う。In this case, subsequently, as shown in FIG.
As shown in (c), similarly to the above-described embodiment, the CF film 4 as the upper insulating film is formed on the surface of the cover film 200, and then the CF film 4 is over-etched. After the formation of the groove 41 and the removal of the CF film 4 deposited inside the via hole 91 during the formation of the CF film 4, FIG.
As shown in FIG. 3, an etching gas such as CF 4 or C 4 F 8
The cover film 200 is removed using a gas.

【００６１】本実施の形態は、上部絶縁膜が例えばＳｉ
ＬＫ膜、ＢＣＢ膜、ＦＬＡＲＥ膜、有機ＳＯＧ膜、ＨＳ
Ｑ膜、ＭＳＱ膜、ポ−ラスシリカ等の塗布膜や、パリレ
ン、メチルシラン系の膜であって、下部絶縁膜が上部絶
縁膜とはエッチング選択比が同じ場合にも適用できる。
また上部絶縁膜と下部絶縁膜との種類が異なる場合にも
適用してもよい。In this embodiment, the upper insulating film is made of, for example, Si.
LK film, BCB film, FLARE film, organic SOG film, HS
The present invention can be applied to a coating film of a Q film, an MSQ film, porous silica, or the like, or a film of a parylene or methylsilane type, in which the lower insulating film has the same etching selectivity as the upper insulating film.
Further, the present invention may be applied to a case where the types of the upper insulating film and the lower insulating film are different.

【００６２】ここで実際に下部絶縁膜が５０００オング
ストロ−ムの厚さのＣＦ膜、上部絶縁膜が５０００オン
グストロ−ムの厚さのＣＦ膜、両者の間に５００オング
ストロームの厚さの下部絶縁膜のハ−ドマスクが設けら
れていると共に、ビアホ−ルが直径０．５μｍ、溝の幅
が０．４μｍの半導体装置を、ＣＦ膜のエッチング時間
を通常の１．３倍にして上述のプロセスにて製造し、Ｓ
ＥＭにより、エッチング前のビアホ−ルと、エッチング
後のビアホ−ルと溝の断面を観察したところ、エッチン
グ前にはビアホ−ルの底部と側壁にＣＦ膜が付着してい
たが、エッチング後にはビアホ−ル内へのＣＦ膜の埋め
込みやビアホ−ルの変形は見られず、デュアルダマシン
形状が形成されていることが確認された。Here, the lower insulating film is actually a CF film having a thickness of 5000 angstroms, the upper insulating film is a CF film having a thickness of 5000 angstroms, and the lower insulating film having a thickness of 500 angstroms is provided between the two. Of a semiconductor device having a diameter of 0.5 .mu.m and a width of 0.4 .mu.m for a trench, the etching time of a CF film is 1.3 times the normal time, and the above process is performed. Manufactured and S
When the cross section of the via hole before etching and the via hole and the groove after etching were observed by EM, the CF film was adhered to the bottom and the side wall of the via hole before etching. No embedding of the CF film in the via hole and no deformation of the via hole were observed, and it was confirmed that a dual damascene shape was formed.

【００６３】また上部絶縁膜と下部絶縁膜とをＳｉＬＫ
膜、ＢＣＢ膜、ＦＬＡＲＥ膜、有機ＳＯＧ膜、ＨＳＱ
膜、ＭＳＱ膜、ポ−ラスシリカに変えて同様に半導体装
置を製造したところ、塗布条件を変えることにより上部
絶縁膜のビアホ−ルへの堆積量が異なるものの、ビアホ
−ルの大部分に上部絶縁膜が埋め込まれている場合であ
っても、上部絶縁膜のエッチング時間を長くすることに
より、ビアホ−ルの形状の変化を抑えながらビアホ−ル
内の上部絶縁膜を除去することができ、デュアルダマシ
ン形状が形成できることが確認された。The upper insulating film and the lower insulating film are made of SiLK.
Film, BCB film, FLARE film, organic SOG film, HSQ
When a semiconductor device was manufactured in the same manner as above except that the film, the MSQ film, and the porous silica were used, the deposition amount of the upper insulating film on the via hole was changed by changing the coating conditions. Even if the film is buried, by extending the etching time of the upper insulating film, the upper insulating film in the via hole can be removed while suppressing the change in the shape of the via hole, and the dual insulating film can be removed. It was confirmed that a damascene shape could be formed.

【００６４】以上において本発明では、埋め込み特性の
悪いＣＦ膜の成膜ガスとしては上述のＣ6 Ｆ6 ガス以外
に、Ｃ4 Ｆ8 ガス，Ｃ5 Ｆ8 ガス，Ｃ6 Ｆ10ガス，Ｃ6
Ｈ5ＣＦ3 ガス等を用いることができる。またこのＣＦ
膜はＥＣＲによりプラズマを生成することに限られず、
例えばＩＣＰ（Ｉｎｄｕｃｔｉｖｅ ＣｏｕｐｌｅｄＰ
ｌａｓｍａ）などと呼ばれている、ドーム状の容器に巻
かれたコイルから電界及び磁界を処理ガスに与える方法
などによりプラズマを生成する装置を用いても形成でき
る。As described above, in the present invention, in addition to the above-mentioned C 6 F 6 gas, C 4 F 8 gas, C 5 F 8 gas, C 6 F 10 gas, C 6
H 5 CF 3 gas or the like can be used. Also this CF
The film is not limited to generating plasma by ECR,
For example, ICP (Inductive CoupledP)
lasma) or the like, a method of generating plasma by a method of applying an electric field and a magnetic field to a processing gas from a coil wound around a dome-shaped container.

【００６５】さらにヘリコン波プラズマなどと呼ばれて
いる例えば１３．５６ＭＨｚのヘリコン波と磁気コイル
により印加された磁場との相互作用によりプラズマを生
成する装置や、マグネトロンプラズマなどと呼ばれてい
る２枚の平行なカソ−ドにほぼ平行をなすように磁界を
印加することによってプラズマを生成する装置、平行平
板などと呼ばれている互いに対向する電極間に高周波電
力を印加してプラズマを生成する装置を用いても形成す
ることができる。Further, an apparatus for generating plasma by the interaction of a 13.56 MHz helicon wave called a helicon wave plasma and a magnetic field applied by a magnetic coil, or a two-piece called a magnetron plasma etc. A device that generates a plasma by applying a magnetic field so as to be substantially parallel to a parallel cathode, and a device that generates a plasma by applying high-frequency power between mutually facing electrodes called a parallel plate or the like Can also be used.

【００６６】さらにまたビアホ−ルが形成されるＳｉＯ
2 膜は、上述のようにプラズマＣＶＤにより形成する
他、熱酸化法やゾル−ゲル法等により形成することがで
きる。ここでゾル−ゲル法とは、ＴＥＯＳ（テトラエト
キシシラン；Ｓｉ（Ｃ2 Ｈ5 Ｏ）4 ）のコロイドをエタ
ノ−ル溶液等の有機溶媒に分散させた塗布液を半導体ウ
エハＷの表面に塗布し、その塗布膜をゲル化した後乾燥
させてＳｉＯ2 膜を得る手法である。またＳｉＯ2 膜と
ＣＦ膜との間に形成される密着層としては、ＳｉＮ膜は
ＳｉＯ2 膜との密着性が大きく、ＳｉＣ膜はＣＦ膜との
密着性が大きいのでこれらの膜を積層したものを用いる
ことは有効であるが、これらの膜の一方を用いるように
してもよい。Further, a SiO for forming a via hole is formed.
The two films can be formed by a thermal oxidation method, a sol-gel method, or the like, in addition to being formed by plasma CVD as described above. Here, the sol-gel method means that a coating liquid in which a colloid of TEOS (tetraethoxysilane; Si (C 2 H 5 O) 4 ) is dispersed in an organic solvent such as an ethanol solution is applied to the surface of the semiconductor wafer W. In this method, the coating film is gelled and then dried to obtain a SiO 2 film. As the adhesion layer formed between the SiO 2 film and the CF film, the SiN film has a large adhesion with the SiO 2 film, and the SiC film has a large adhesion with the CF film. Although it is effective to use one of these films, one of these films may be used.

【００６７】またビアホ−ルが形成される膜としては、
このようなＳｉＯ2 膜の他、ＳｉＯＦ膜や有機ＳＯＧ
膜、ＨＳＱ膜、ＢＣＢ膜、ポリイミド膜、Ｆ添加ポリイ
ミド膜、フッ化ポリアリルエ−テル、テフロン、サイト
ップ等の塗布膜を用いることができる。As a film on which a via hole is formed,
In addition to such SiO 2 film, SiOF film and organic SOG
A coating film such as a film, an HSQ film, a BCB film, a polyimide film, an F-added polyimide film, polyallyl fluoride ether, Teflon, or Cytop can be used.

【００６８】さらにまた埋め込み特性の悪い成膜材料を
用いて上部絶縁膜の形成を行った場合であっても、上部
絶縁膜に溝を形成するエッチングを行う際にいわゆるオ
−バ−エッチングを行うようにしてもよい。Furthermore, even when the upper insulating film is formed using a film forming material having poor filling characteristics, so-called over etching is performed when etching for forming a groove in the upper insulating film. You may do so.

【００６９】[0069]

【発明の効果】以上のように本発明によれば、半導体装
置を簡易な手法のデュアルダマシン法で製造することが
できる。As described above, according to the present invention, a semiconductor device can be manufactured by a simple dual damascene method.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明方法の概要を説明するための工程図であ
る。FIG. 1 is a process chart for explaining the outline of the method of the present invention.

【図２】本発明方法の具体的な一例を示す工程図であ
る。FIG. 2 is a process chart showing a specific example of the method of the present invention.

【図３】本発明方法の具体的な一例を示す工程図であ
る。FIG. 3 is a process chart showing a specific example of the method of the present invention.

【図４】本発明方法の具体的な一例を示す工程図であ
る。FIG. 4 is a process chart showing a specific example of the method of the present invention.

【図５】本発明方法の具体的な一例を示す工程図であ
る。FIG. 5 is a process chart showing a specific example of the method of the present invention.

【図６】本発明方法を実施するためのプラズマ処理装置
の一例を示す縦断側面図である。FIG. 6 is a vertical sectional side view showing an example of a plasma processing apparatus for carrying out the method of the present invention.

【図７】本発明の作用を説明するための工程図である。FIG. 7 is a process chart for explaining the operation of the present invention.

【図８】本発明方法で製造される半導体装置の他の例を
示す断面図である。FIG. 8 is a sectional view showing another example of a semiconductor device manufactured by the method of the present invention.

【図９】本発明方法の他の例を示す工程図である。FIG. 9 is a process chart showing another example of the method of the present invention.

【図１０】塗布膜の形成方法を説明するための工程図で
ある。FIG. 10 is a process chart for describing a method of forming a coating film.

【図１１】本発明の他の例の作用を説明するための説明
図である。FIG. 11 is an explanatory diagram for explaining an operation of another example of the present invention.

【図１２】塗布膜とハ−ドマスク，エッチングガス，絶
縁膜との関係を示す特性図である。FIG. 12 is a characteristic diagram showing a relationship among a coating film, a hard mask, an etching gas, and an insulating film.

【図１３】本発明方法のさらに他の例を示す工程図であ
る。FIG. 13 is a process chart showing still another example of the method of the present invention.

【図１４】本発明方法のさらに他の例を示す工程図であ
る。FIG. 14 is a process chart showing still another example of the method of the present invention.

【図１５】本発明方法のさらに他の例を示す工程図であ
る。FIG. 15 is a process chart showing still another example of the method of the present invention.

【図１６】本発明方法のさらに他の例を示す工程図であ
る。FIG. 16 is a process chart showing still another example of the method of the present invention.

【図１７】従来のデュアルダマシン法の一例を示す工程
図である。FIG. 17 is a process chart showing an example of a conventional dual damascene method.

【図１８】従来のデュアルダマシン法の一例を示す工程
図である。FIG. 18 is a process chart showing an example of a conventional dual damascene method.

【符号の説明】[Explanation of symbols]

Ｗ 半導体ウエハ ２ 基板 ３ ＳｉＯ2 膜 ３１，９１ ビアホ−ル ４，９ ＣＦ膜 ４１ 溝W Semiconductor wafer 2 Substrate 3 SiO 2 film 31, 91 Via hole 4, 9 CF film 41 Groove

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成１０年１２月２５日（１９９８．１２．
２５）[Submission date] December 25, 1998 (1998.12.
25)

【手続補正１】[Procedure amendment 1]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図９[Correction target item name] Fig. 9

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図９】 FIG. 9

【手続補正２】[Procedure amendment 2]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１０[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１０】 FIG. 10

【手続補正３】[Procedure amendment 3]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１１[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１１】 FIG. 11

【手続補正４】[Procedure amendment 4]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１２[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１２】 FIG.

【手続補正５】[Procedure amendment 5]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１３[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１３】 FIG. 13

【手続補正６】[Procedure amendment 6]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１４[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１４】 FIG. 14

【手続補正７】[Procedure amendment 7]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１５[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１５】 FIG.

【手続補正８】[Procedure amendment 8]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１６[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１６】 FIG. 16

【手続補正９】[Procedure amendment 9]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図１８[Correction target item name] FIG.

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図１８】 FIG.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 妹尾 幸治 東京都港区赤坂五丁目３番６号 東京エレ クトロン株式会社内 (72)発明者 萩原 正明 山梨県韮崎市藤井町北下条2381−１ 東京 エレクトロン山梨株式会社内 Ｆターム(参考） 5F004 AA11 BA14 DA00 DA01 DA24 DA26 DB03 DB07 DB08 DB23 DB25 DB26 EA03 EA07 EA26 EB01 EB02 EB03 5F033 HH11 JJ11 MM02 QQ09 QQ11 QQ27 QQ28 QQ37 QQ48 QQ76 QQ92 QQ93 RR01 RR04 RR06 RR09 RR11 RR21 RR22 RR23 RR24 RR25 RR26 SS01 SS02 SS15 SS22 TT02 TT04 XX12 XX24 XX33 5F045 AA10 AB06 AB33 AB39 AC01 AC07 AD07 DC51 DC61 DC63 HA03 HA13 5F058 AC03 AC04 AC05 AF04 AG04 AH02 BA20 BC02 BC08 BD02 BD03 BD10 BD18 BF09 BF23 BH12 BJ01 BJ02  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Koji Senoo, Inventor Tokyo Electron Co., Ltd., 5-3-6 Akasaka, Minato-ku, Tokyo Electron Yamanashi Co., Ltd. F-term (reference) RR24 RR25 RR26 SS01 SS02 SS15 SS22 TT02 TT04 XX12 XX24 XX33 5F045 AA10 AB06 AB33 AB39 AC01 AC07 AD07 DC51 DC61 DC63 HA03 HA13 5F058 AC03 AC04 AC05 AF04 AG04 AH02 BA20 BC02 BC08 BD02 BD03 BD10 BD18 B02B01B23

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性
の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形
成するための溝を前記ビアホ−ルの少なくとも一部に接
触するようにエッチングする工程と、を含むことを特徴
とする半導体装置の製造方法。A step of forming an insulating film on an object to be processed; a step of etching a via hole in the insulating film; and forming a film having poor filling characteristics on the surface of the insulating film on which the via hole is formed. Forming an upper insulating film using a material, and etching a groove for forming a wiring by embedding a metal in the upper insulating film so as to contact at least a part of the via hole. A method for manufacturing a semiconductor device, comprising: 【請求項２】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、炭素とフッ素
との化合物であって埋め込み特性の悪い成膜材料を用い
てフッ素添加カ−ボン膜を形成する工程と、 前記フッ素添加カ−ボン膜に、金属を埋め込むことによ
り配線を形成するための溝を前記ビアホ−ルの少なくと
も一部に接触するようにエッチングする工程と、を含む
ことを特徴とする半導体装置の製造方法。A step of forming an insulating film on the object to be processed; a step of etching a via hole in the insulating film; and a step of forming a compound of carbon and fluorine on the surface of the insulating film on which the via hole is formed. Forming a fluorine-added carbon film using a film-forming material having poor filling characteristics; and forming a groove for forming a wiring by embedding a metal in the fluorine-added carbon film in the via hole. Etching the semiconductor device so as to contact at least a part of the semiconductor device. 【請求項３】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 炭素とフッ素との化合物であって埋め込み特性の悪い成
膜材料をプラズマ化し、そのプラズマによりビアホ−ル
が形成された絶縁膜の表面にフッ素添加カ−ボン膜を形
成する工程と、 前記フッ素添加カ−ボン膜に、金属を埋め込むことによ
り配線を形成するための溝を前記ビアホ−ルの少なくと
も一部に接触するようにエッチングする工程と、を含む
ことを特徴とする半導体装置の製造方法。3. A step of forming an insulating film on an object to be processed, a step of etching a via hole in the insulating film, and forming a film-forming material which is a compound of carbon and fluorine and has a poor filling property into plasma. Forming a fluorine-added carbon film on the surface of the insulating film on which the via hole is formed by the plasma; and forming a groove for forming a wiring by embedding a metal in the fluorine-added carbon film. Etching the semiconductor device so as to contact at least a part of the via hole. 【請求項４】 前記炭素とフッ素との化合物であって埋
め込み特性の悪い成膜材料はヘキサフルオロベンゼンで
あることを特徴とする請求項２又は３記載の半導体装置
の製造方法4. The method for manufacturing a semiconductor device according to claim 2, wherein said film-forming material which is a compound of carbon and fluorine and has a poor embedding property is hexafluorobenzene. 【請求項５】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、当該絶縁膜と
はエッチング選択比の異なる上部絶縁膜を形成する工程
と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形
成するための溝を前記ビアホ−ルの少なくとも一部に接
触するようにエッチングする工程と、 上部絶縁膜のエッチング終了後所定時間エッチングを行
なうことにより、ビアホ−ル内に堆積した上部絶縁膜を
エッチングにより除去する工程と、を含むことを特徴と
する半導体装置の製造方法。5. A step of forming an insulating film on an object to be processed, a step of etching a via hole in the insulating film, and etching the insulating film on the surface of the insulating film on which the via hole is formed. Forming an upper insulating film having a different selectivity; and etching a groove for forming a wiring by embedding a metal in the upper insulating film so as to contact at least a part of the via hole. Etching the upper insulating film to remove the upper insulating film deposited in the via hole by performing etching for a predetermined time after the etching of the upper insulating film. 【請求項６】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、当該絶縁膜と
はエッチング選択比の異なる薄膜を形成する工程と、 前記薄膜の表面に上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形
成するための溝を前記ビアホ−ルの少なくとも一部に接
触するようにエッチングする工程と、 上部絶縁膜のエッチング終了後所定時間エッチングを行
なうことにより、ビアホ−ル内に堆積した上部絶縁膜を
エッチングにより除去する工程と、を含むことを特徴と
する半導体装置の製造方法。6. A step of forming an insulating film on an object to be processed, a step of etching a via hole in the insulating film, and etching the insulating film on the surface of the insulating film on which the via hole is formed. Forming a thin film having a different selectivity, forming an upper insulating film on the surface of the thin film, and forming a groove for forming a wiring by embedding a metal in the upper insulating film at least in the via hole. A step of etching so as to make contact with a part of the upper insulating film, and a step of performing etching for a predetermined time after the etching of the upper insulating film to remove the upper insulating film deposited in the via hole by etching. Manufacturing method of a semiconductor device. 【請求項７】 前記上部絶縁膜はフッ素添加カ−ボン膜
であることを特徴とする請求項１，５又は６記載の半導
体装置の製造方法。7. A method according to claim 1, wherein said upper insulating film is a fluorine-added carbon film. 【請求項８】 前記上部絶縁膜は塗布膜であることを特
徴とする請求項１，５又は６記載の半導体装置の製造方
法。8. The method according to claim 1, wherein the upper insulating film is a coating film.
JP10321537A 1998-09-02 1998-10-27 Fabrication of semiconductor device Pending JP2000150516A (en)

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KR10-2001-7002791A KR100400907B1 (en) 1998-09-02 1999-09-01 Method of manufacturing semiconductor device
EP99940607A EP1120822A4 (en) 1998-09-02 1999-09-01 Method of manufacturing semiconductor device
TW088115109A TW464952B (en) 1998-09-02 1999-09-02 Process for producing semiconductor device
US09/665,960 US6737350B1 (en) 1998-09-02 2000-09-21 Method of manufacturing semiconductor device

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