JP2000349151A - Semiconductor device and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable semiconductor device to be lessened in inter-wiring and inter-wiring layer effective dielectric constant and inter-wiring and inter-wiring layer capacitance. SOLUTION: An insulating film (ILD film 13) which is interposed between wiring layers and provided with a connection hole, an insulating film (IMD film 16) which is interposed between wiring layers and provided with a wiring groove, and an etching stopper layer 14 interposed between the insulating films 13 and 16 are provided, where an opening 15 used for forming a connection hole 22 is provided in the etching stopper layer 14, and the etching stopper layer 14 is formed only under and around regions where wiring grooves 21 are each formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a wiring structure formed by a dual damascene method and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to increase the operating speed of semiconductor devices and reduce power consumption, in order to put copper wiring to practical use,
A dual damascene process is being developed. Further, it is necessary to reduce the wiring capacitance by practically using a low dielectric constant insulating material. Low dielectric constant materials include fluorine-containing silicate glass (FSG), organic films, and porous silica.

In the dual damascene process, it is important to accurately control the depth of the wiring groove in order to form wiring with good uniformity. Therefore, an insulating film (hereinafter referred to as an IMD film, IMD is an Inter Metal
Dielectrics) and an insulating film between wiring layers (hereafter, ILD)
A so-called first via (FV) method, in which a wiring groove is formed by using a material different from that of a film (ILD is an abbreviation of Inter Level Dielectrics) and using etching with good selectivity between the IMD film and the ILD film, is generally used. is there. In this method, the etching selectivity between the IMD film and the ILD film must be obtained, so that the selection of materials is limited, and
A material having a high dielectric constant must be used for the film. For example, an organic material is used for the IMD film, and a silicon oxide-based material is used for the ILD film.

Further, an etching stopper is formed between the IMD film and the IMD film.
The self-aligned dual damascene (SADD) method, which is disposed between the LD film and the LD film, is used in the VMIC Conference Abstract,
(1997) Y. Morand et al., Pp. 75-80. The main steps of the SADD method will be described below with reference to the manufacturing process diagram of FIG.

As shown in FIG. 7A, a first insulating film 111 covering elements, wirings, etc. is formed on a semiconductor substrate (not shown) on which elements such as transistors and wirings are formed. This first insulating film 111 has a first wiring 11 having a trench wiring structure.
2 are formed. On the first insulating film 111, a first
ILD film 121 is formed of an organic film covering wiring 112 of FIG. Further, the etching stopper layer 1 is formed on the ILD film 121.
22 is formed.

Subsequently, as shown in FIG. 7B, an opening 123 for opening a connection hole is formed in the etching stopper layer 122 by lithography and etching.

Next, as shown in FIG. 7 (3), an IMD covering the opening 123 is formed on the etching stopper layer 122.
The film 124 is formed using an organic film. Then, the IMD film 124
A hard mask 125 is formed thereon with an oxide silicate glass film.

Next, as shown in FIG. 7D, after forming a resist film 131 for forming a wiring groove, a wiring groove pattern 132 is formed in the resist film 131 by lithography.

Subsequently, as shown in FIG. 7 (5), using the resist film 131 as an etching mask, the hard mask 125 and the IMD film 124 are etched to form the wiring groove 1.
After forming 26, the ILD film 121 is etched using the etching stopper layer 122 as an etching mask to form a connection hole 127.

Next, as shown in FIG. 7 (6), a barrier metal layer 128 is formed in the wiring groove 126 and the connection hole 127.
Is formed, copper is buried through the barrier metal layer 128. Thereafter, chemical mechanical polishing (hereinafter referred to as CMP)
CMP is an abbreviation of Chemical Mechanical Polishing) to remove excess copper and a barrier metal layer (not shown) on the hard mask 125 to form a wiring 129 in the wiring groove 126 via a barrier metal layer 128. , Plug 1 in connection hole 127 via barrier metal layer 128.
Form 30.

[0011]

However, in the conventional FV method, an ILD film formed of an oxide film is formed on the entire surface. Therefore, even if a low dielectric constant film is used as the IMD film, the effective dielectric constant can be sufficiently increased. It cannot be reduced.

Further, the SADD method requires etching selectivity between the IMD film and the etching stopper. Therefore, an organic film is used for the IMD film and the ILD film, and an oxide film is used for the etching stopper. Thus, an oxide film, which is a material having a high dielectric constant, must be used for the etching stopper. The SADD method can reduce the effective dielectric constant as compared with the FV method. However, in the conventional technique, since the etching stopper is formed on the entire surface, the IMD film,
Even if a low dielectric constant film is used as the LD film, the effective dielectric constant has not been sufficiently reduced.

[0013]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

The first semiconductor device comprises an insulating film between wiring layers in which connection holes are formed, an insulating film between wirings in which wiring grooves are formed, and an etching stopper layer formed between the two insulating films. The etching stopper layer is formed only below and around the region where the wiring groove is formed, and has an opening for forming a connection hole.

In the first semiconductor device having the above structure, the etching stopper layer is formed only below and around the region where the wiring groove is formed, and the opening for forming a connection hole in the etching stopper layer is formed. Since the portion is formed, the amount of the etching stopper layer formed between the two insulating films is smaller than that of the conventional etching stopper layer. Usually, the etching stopper layer is formed of a material having a high dielectric constant, such as a silicon-based oxide film or a nitride film, and thus, by reducing the amount of the etching stopper layer, the dielectric constant between the wirings and between the wiring layers is reduced. Is reduced, and the capacitance between wirings and the capacitance between wirings are reduced.

The first method for manufacturing a semiconductor device includes a step of forming an insulating film between wiring layers in which connection holes are formed, a step of forming an etching stopper layer on the insulating film between wiring layers, and a step of forming the etching stopper layer. Forming an insulating film between wirings in which a wiring groove is formed on the insulating film between wiring layers by coating the etching stopper layer only under and around the region where the wiring groove is formed. And an opening for forming a connection hole is formed in the etching stopper layer.

In the first method of manufacturing a semiconductor device, since the etching stopper layer is formed only below and around the region where the wiring groove is formed, the amount of the etching stopper layer is smaller than that of the conventional etching stopper layer. Less. Usually, the etching stopper layer has a high dielectric constant because it is formed of a silicon-based oxide film or a nitride film. However, since the amount of the etching stopper layer is reduced in this manner, the distance between the wirings and between the wiring layers is reduced. The dielectric constant is kept lower than that of the conventional configuration. Therefore, the capacitance between wirings and the capacitance between wirings are reduced.

In addition, since the etching stopper layer is formed only below and around the region where the wiring groove is formed, and the opening for forming the connection hole is formed in the etching stopper layer, the etching stopper layer is formed by wiring. It can be used as an etching mask when forming a connection hole in an interlayer insulating film. Further, since the etching stopper layer is formed only below and around the region where the wiring groove is formed, when the wiring groove is formed in the insulating film between the wirings, the wiring groove is etched without protruding from the etching stopper layer. It will be formed on the stopper layer. Therefore, a wiring groove is formed at a predetermined depth. In addition, even when a mask misalignment occurs in the exposure step of the lithography step when forming the wiring groove, the etching stopper layer is also formed around the area below the area where the wiring groove is formed, so that the etching stopper layer protrudes. Therefore, no wiring groove is formed. Therefore, it does not occur that the wiring groove is formed too deeply to cause a short circuit with the lower wiring.

In the second semiconductor device, an insulating film between wiring layers where connection holes are formed and an insulating film between wiring layers where wiring grooves are formed and an insulating film between wirings having etching selectivity are formed. In the device provided, the insulating film between the wiring layers is formed only below and around the region where the wiring groove is formed.

In the second semiconductor device having the above-mentioned structure, the insulating film between the wiring layers is formed only under and around the region where the wiring groove is formed, and is therefore formed of a conventional silicon oxide film. The volume is smaller than the insulating film between the wiring layers. Normally, since a silicon oxide film has a high dielectric constant of about 4.2, the dielectric constant between wiring layers is reduced by reducing the number of insulating films formed between layers having such a high dielectric constant. The interlayer capacitance is reduced.

According to a second method of manufacturing a semiconductor device, an insulating film is formed between wiring layers in which connection holes are formed, and an insulating film is formed between wirings in which wiring grooves are formed on the insulating film between wiring layers. And forming an insulating film between the wiring layers only under and around the region where the wiring groove is formed, and forming a connection hole in the insulating film between the wirings.

In the second method of manufacturing a semiconductor device, the insulating film between the wiring layers is formed only below and around the region where the wiring groove is formed. The amount of insulating film between wiring layers formed of a material having a high dielectric constant is reduced. By reducing the insulating film between the wiring layers as described above, the dielectric constant between the wiring layers can be reduced. Therefore, the capacitance between wirings is reduced.

Further, since the insulating film between the wiring layers is formed only below and around the region where the wiring groove is formed, when the wiring groove is formed in the insulating film between the wirings, the wiring groove becomes insulative between the wiring layers. It is not formed off the film. Therefore, a wiring groove is formed at a predetermined depth. Further, even when a mask misalignment occurs in the exposure step of the lithography step when forming the wiring groove, a layer having an etching selectivity is also formed around the area below the area where the wiring groove is formed, so that the etching stopper The wiring groove is not formed outside the layer. Therefore, it does not occur that the wiring groove is formed too deeply to cause a short circuit with the lower wiring.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment relating to a first semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG. FIG. 1 shows an example of a semiconductor device formed by the method of the present invention based on the SADD method.

As shown in FIG. 1, an insulating film 1 for covering a transistor, a capacitor and the like (not shown) formed on a semiconductor substrate (not shown) such as a silicon substrate.
1 is formed. A first wiring 12 having a trench wiring structure is formed on the insulating film 11. Further, on the insulating film 11, an ILD (Inter Level) covering the first wiring 12 and serving as an insulating film between wiring layers in which connection holes are formed.
l Dielectrics) The film 13 is formed to a thickness of, for example, 300 nm. This ILD film 13 is formed of, for example, polyaryl ether. Alternatively, it may be formed of a low dielectric constant organic film such as a BCB film, a polyimide film, and an amorphous carbon film.

Next, on the ILD film 13, an etching stopper layer 14 is formed of, for example, a silicon oxide film having a thickness of 150 nm. The etching stopper layer 14 is formed only below and around the region where the trench wiring is to be formed, and has an opening 1 for forming a connection hole.
5 are formed. The periphery below the region in which the wiring groove is formed is, for example, a range in which the wiring groove is formed on the etching stopper layer 14 even when a mask misalignment occurs in an exposure step in forming the wiring groove. The etching stopper layer 14 may be formed of a silicon oxynitride film or a silicon nitride film.

On the ILD film 13, an IMD (Inter Metal Dielectrics) film 16 which covers the etching stopper layer 14 and serves as an insulating film between wirings in which wiring grooves are formed is formed to a thickness of, for example, 300 nm. Have been. The IMD film 16 may be formed of an insulating film made of a material similar to that of the ILD film 13 or may be formed of a low dielectric constant organic film such as a BCB film, a polyimide film, and an amorphous carbon film. .

On the IMD film 16, a hard mask layer 17 is formed by depositing, for example, silicon oxide to a thickness of 200 nm. In the hard mask layer 17, an opening 18 serving as a wiring groove pattern is formed. ing. Further, a wiring groove 21 is formed in the ILD film 16 below the opening 18,
Opening 15 formed in etching stopper layer 14
A connection hole 22 is formed in the lower ILD film 13.

When a diffusion preventing layer such as a silicon nitride film is formed on the first wiring 12, the connection hole 22 penetrates the diffusion preventing layer and reaches the surface of the first wiring 12. It is formed as follows.

Further, a barrier metal layer 23 is formed on each inner surface of the wiring groove 21 and the connection hole 22.
, A second wiring 24 made of, for example, copper or a copper alloy is formed through the barrier metal layer 23,
A plug 25 made of, for example, copper or a copper alloy is formed inside the connection hole 22 via the barrier metal layer 23.

Further, on the IMD film 16 and the second wiring 24, the same ILD film 13 as described above,
IMD film 16, connection hole 22, wiring groove 21, second wiring 2
4. It is also possible to form the plugs 25 and the like and stack the above wiring structure.

In the semiconductor device described in the first embodiment, the etching stopper layer 14 is formed only below and around the region where the wiring groove 21 is formed, and is connected to the etching stopper layer 14. Since the opening 15 for forming the hole 22 is formed, the amount of the two insulating films, that is, the etching stopper layer 14 formed between the ILD film 13 and the IMD film 16 is reduced by the conventional SADD method. The number is smaller than that of the formed etching stopper layer. Usually, the etching stopper layer 14 is formed of the organic material IMD film 16 as described above.
Since it is formed using a silicon-based oxide film, nitride film, or the like that is not easily etched, the dielectric constant is high. As in the above embodiment, the amount of the etching stopper layer 14 is reduced, so that the distance between the wirings (between the second wirings 24, 24) and between the wirings (between the first wiring 12 and the second wiring 24) are reduced. The effective dielectric constant of the insulating film formed in (1) is reduced, and the capacitance between wirings and the capacitance between wirings are reduced.

Next, a modification of the above-described embodiment will be described with reference to the schematic sectional view of FIG. FIG.
The same reference numerals are given to the same components as those shown in FIG.

The configuration shown in FIG. 2 is the first type shown in FIG.
In the embodiment, the wiring groove 21 is formed so as to penetrate the etching stopper layer 14 and reach the ILD film 13, and the second wiring is formed inside the wiring groove 21 via the barrier metal layer 23. 24 are formed. Therefore, the lower portion of the wiring groove 21 is also formed in the etching stopper layer 14. Other components such as the insulating film 11, the first wiring 12, the ILD film 13, the opening 15, the IMD film 16, the hard mask layer 17, and the opening 1
8, connection hole 22, barrier metal layer 23, second wiring 2
4. The plug 25 and the like are the same as those described in the first embodiment.

In the structure shown in FIG. 2, since the wiring groove 21 is formed in the etching stopper layer 14, the volume is smaller than that of the etching stopper layer 14 shown in FIG. Therefore, the effective dielectric constant between the wirings and between the wiring layers is reduced by the wiring groove 21 formed in the etching stopper layer 14.

Next, an embodiment relating to the first method of manufacturing a semiconductor device will be described with reference to the manufacturing process diagram of FIG.
FIG. 1 shows an example of a semiconductor device formed by the method of the present invention based on the SADD method, and the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

Although not shown, a transistor, a capacitor and the like (not shown) are formed on a semiconductor substrate (for example, a silicon substrate), and then an insulating film 11 is formed as shown in FIG. Next, the first wiring 1 is formed on the insulating film 11.
2 is formed by, for example, a generally known trench wiring technique. An ILD (Inter Level Dielectr) which covers the first wiring 12 on the insulating film 11 and serves as an insulating film between wiring layers.
ics) The film 13 is formed to a thickness of, for example, 300 nm. The ILD film 13 is made of, for example, polyaryl ether, and is formed by applying a polyaryl ether precursor by a spin coating method and then performing a heat treatment at 300 ° C. to 450 ° C. (here, 400 ° C. as an example). The ILD film 13 may be made of, for example, BC
It is also possible to use a low dielectric constant organic film such as a B film, a polyimide film, and an amorphous carbon film.

Next, an etching stopper layer 14 is formed on the ILD film 13 by, for example, a silicon oxide film having a thickness of 150 nm. The etching stopper layer 14 is formed by, for example, a plasma CVD method using a silane-based gas such as monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) as a process gas. For example, monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O) are used as source gases, the substrate temperature is 350 ° C., and the pressure of the film formation atmosphere is 1 k.
The film was formed by setting to Pa. The etching stopper layer 14 can be formed of a silicon oxynitride film or a silicon nitride film.

Next, as shown in FIG. 3B, the etching stopper layer 14 is patterned by using a usual lithography technique and an etching technique. In this patterning, an opening 15 for forming a connection hole reaching the first wiring 12, for example, is formed in the etching stopper layer 14 by etching using a resist film (not shown) as an etching mask. The etching stopper layer 14 is formed halfway through the layer 14, and the remaining portion is removed partway through the etching stopper layer 14 while leaving the etching stopper layer 14 below and around the region where the trench wiring is to be formed. The area under the region where the groove wiring is formed is such that even if a mask misalignment occurs in the exposure step when forming the wiring groove, the wiring groove is not etched by the etching stopper layer 14.
It is a range formed above.

The depth at which the etching stopper layer 14 is partially removed is, for example, 100 nm. In this etching, for example, a general plasma etching apparatus is used, and tetrafluoromethane (CF ₄ ) is used as an etching gas.
The etching conditions were set to, for example, RF power of 1.5 kW and etching atmosphere pressure of 10 Pa using argon and argon (Ar). In the etching of the etching stopper layer 14, the etching depth was controlled by controlling the etching time. At this time, the etching depth needs to be determined so that the ILD film 13 is not exposed over the entire surface of the wafer in consideration of the uniformity of the etching rate within the wafer surface.

Thereafter, the resist film (not shown) used for the etching is removed by a normal ashing process. In this case, the ILD film 1 is formed on the etching stopper layer 14.
3 is covered, the IL
The D film 13 is not etched, and the ILD film 13 is not etched.

Next, the etching stopper layer 14 is etched back by the whole surface etch back process,
Opening 15 for forming a connection hole reaching wiring 12
Is formed, and the etching stopper layer 14 in other portions is removed while leaving the etching stopper layer 14 under and around the region where the trench wiring is to be formed. The region where the trench wiring is formed and the periphery thereof are, for example, in a range in which a mask misalignment in lithography performed when patterning the trench wiring can be compensated. In the above etch-back, a general plasma etching apparatus is used, and octafluorobutene (C ₄ F) is used as an etching gas.
₈ ) Using argon (Ar) and carbon monoxide (CO), the etching conditions were such that the pressure of the etching atmosphere was 6P.
a, RF power is set to 1.5 kW. As described above, the etching stopper layer 14 is patterned by two-stage etching.

Next, as shown in FIG. 3C, an IMD film 16 which covers the etching stopper layer 14 and serves as an insulating film between wirings is formed on the ILD film 13.
The IMD film 16 is formed of, for example, polyaryl ether by the same forming method as the ILD film 13. The film thickness was, for example, 300 nm.

Further, a hard mask layer 17 is formed on the IMD film 16. The hard mask layer 17 is formed, for example, by adding silicon oxide to a plasma CVD method.
It is formed by depositing to a thickness of 00 nm.

Next, as shown in FIG. 3D, the hard mask layer 17 is patterned using ordinary lithography and etching techniques. First, after forming a resist film 31 on the hard mask 17, an opening 3 for forming a wiring groove is formed by lithography technology.
Form 2

Subsequently, as shown in FIG. 3 (5), the hard mask layer 17 is etched using the resist film 31 as an etching mask to form an opening 18 for forming a wiring groove. . In these etchings, as an example, a magnetron etching apparatus is used, and octafluorobutene (C ₄ F ₈ ) (supply flow rate is set to, for example, 10 sccm) and argon (Ar) are used as etching gases.
[Supply flow rate is set to, for example, 200 sccm] and oxygen (O
₂ ) [The supply flow rate is set to ₂ sccm, for example]
The substrate temperature was set at 20 ° C., the power was set at 2 kW, and the pressure of the etching atmosphere was set at 8 Pa.

Further, using the hard mask layer 17 as an etching mask, the IMD film 16 is etched to form the wiring groove 2.
Form one. In this etching, the etching stopper layer 14 serves as the bottom of the wiring groove 21 and
Stop etching. Subsequently, the opening 15 is formed by using the etching stopper layer 14 as an etching mask.
The ILD film 13 is etched further, and the first wiring 12
Is formed. In these etchings, as an example, a helicon wave plasma etching apparatus is used, ammonia (NH ₃ ) is used as an etching gas (a supply flow rate is set to 100 sccm, for example), a substrate temperature is 100 ° C., a source power is 1.5 kW, The bias power was set to 100 W, and the pressure of the etching atmosphere was set to 1 Pa. Alternatively, using a general ECR plasma etching apparatus, using nitrogen (N ₂ ) and helium (He) as an etching gas, the etching conditions are a pressure of an etching atmosphere of 1 Pa, a microwave power of 1 kW, a bias RF power. Is set to 300W.

The resist film 31 is formed of the IMD film 1
6. It is removed when the ILD film 13 is etched. In the case where a diffusion preventing layer such as a silicon nitride film is formed on the first wiring 12, after the connection hole 22 is formed, the diffusion preventing layer is removed to remove the surface of the first wiring 12. The exposed anisotropic etching is performed.

The etching stopper layer 14 exposed at the bottom of the wiring groove 21 may be removed by anisotropic etching. This will be described later.

Thereafter, as shown in FIG. 3 (6), the barrier metal layer 2 is formed on the inner surfaces of the wiring grooves 21 and the connection holes 22 by sputtering, vapor deposition or CVD.
3 and a copper film is further formed. At that time, the barrier metal layer 23 and the copper film are also formed on the hard mask layer 17. The barrier metal layer 23 is formed by depositing, for example, tantalum nitride or tantalum to a thickness of 50 nm. Note that, prior to the formation of the barrier metal layer 23, it is preferable to perform sputter etching in order to remove a natural oxide film or the like formed on the surface of the first wiring 12. After the sputter etching, the barrier metal layer 23 is preferably formed without being exposed to an oxidizing atmosphere (for example, the atmosphere). For example, so-called in situ processing is performed.

Thereafter, the connection holes 22 are formed by electrolytic plating.
And the wiring groove 21 is buried with copper. At this time, a copper film is also formed on the hard mask layer 17. Then, the excess copper film and the barrier metal layer 23 on the hard mask layer 17 are removed by CMP to form the second wiring 24 inside the wiring groove 21 and the first wiring 12 inside the connection hole 22. Is formed to be electrically connected to the plug. The above C
During the MP, the hard mask layer 17 serves as a polishing stopper, but the hard mask layer 17 may be completely removed depending on the thickness of the hard mask layer 17. Although copper is buried in the above example, another metal material such as aluminum, which is a wiring material, may be buried.

Although not shown, the ILD film 13
By repeating the steps from the step of forming the wiring 24 to the step of forming the wiring 24 and the plug 25, a multilayer wiring can be formed.

In the first embodiment, the etching stopper layer may be formed as follows.

That is, the etching stopper layer 14 is formed in the same manner as described above. After that, the etching stopper layer 14 is etched using a normal lithography technique and an etching technique. In this etching, an opening 15 for forming, for example, a connection hole reaching the first wiring 12 is formed in the etching stopper layer 14 by using a resist mask, and a region under the groove wiring is formed and the opening 15 is formed. Other portions are removed by etching while leaving the peripheral etching stopper layer 14.
The region where the trench wiring is formed and the periphery thereof are, for example, in a range in which a mask misalignment in lithography performed when patterning the trench wiring can be compensated.

In the etching of the etching stopper layer 14 made of the silicon oxide film, for example, a general plasma etching apparatus is used. As an example, tetrafluoromethane (CF ₄ ), argon (Ar), and carbon monoxide (CO) are used as etching gases. ), The RF power was set to 1.5 kW and the pressure of the etching atmosphere was set to 6 Pa as an example.

Next, the resist mask is removed by anisotropic etching. At this time, the ILD film 13 is also anisotropically etched. In this etching, for example, a general ECR (Electron Cycrotron Resonance) is used.
Using a plasma etching apparatus, nitrogen (N ₂ ) and helium (He) are used as etching gases, and the etching conditions are set such that the pressure of the etching atmosphere is 1 Pa, the microwave power is 1 kW, and the bias RF power is 300 W.
Since the insulating film 11 is provided below the ILD film 13,
This etching is stopped at least on the insulating film 11.

Thereafter, an IMD film 16 which fills the ILD film removed by the etching and covers the etching stopper layer 14 and serves as an insulating film between wirings is formed on the ILD film 13. This IMD film 1
6 is formed of, for example, polyaryl ether by the same forming method as that of the ILD film 13. The film thickness was, for example, 300 nm. The subsequent steps are the same as those described above.

In the method of manufacturing a semiconductor device described in the first embodiment, the etching stopper layer 14 is formed only under and around the region where the wiring groove 21 is formed, and the connection hole 22 is formed. Is formed in the etching stopper layer 14, the amount of the etching stopper layer 14 is smaller than that of the etching stopper layer formed by the conventional SADD method. Normally, the etching stopper layer has a high dielectric constant because it is formed of a silicon-based oxide film or a nitride film. However, since the amount of the etching stopper layer 14 is reduced, the distance between the wirings (the second The effective permittivity between the wirings 24, 24) and between the wiring layers (between the first wiring 12 and the second wiring 24) is suppressed to be lower than that of the structure formed by the conventional SADD method. Therefore, the capacitance between wirings and the capacitance between wirings are reduced.

Further, since the etching stopper layer 14 is formed only under and around the region where the wiring groove 21 is formed, when the wiring groove 21 is formed in the IMD film 16,
The wiring groove 21 is formed on the etching stopper layer 14 without protruding from the etching stopper layer 14. Therefore, the wiring groove 21 is formed at a predetermined depth.
Further, even if a mask misalignment occurs in the exposure step of the lithography step when forming the wiring groove 21, the etching stopper layer 14 is also formed around the area below the area where the wiring groove 21 is formed. The wiring groove 21 is not formed outside the layer 14. Therefore, there is no possibility that the wiring groove 21 is formed too deeply to cause a short circuit with the first wiring 12.

Next, a modification of the above-described first embodiment will be described with reference to the manufacturing process diagram of FIG. In FIG. 4, the same components as those shown in FIG. 3 are denoted by the same reference numerals.

As shown in FIG. 4A, in the step shown in FIG. 3A, the wiring groove 21 is formed so as to penetrate the etching stopper layer 14 and reach the ILD film 13.

Thereafter, as shown in FIG. 4B, the second wiring 24 is formed inside the wiring groove 21 via the barrier metal layer 23 in the same manner as in the step shown in FIG. At the same time, the barrier metal layer 23 is formed inside the connection hole 22.
The plug 25 is formed through the process.

In the manufacturing method shown in FIG. 4, since the wiring groove 21 is also formed in the etching stopper layer 14, the structure shown in FIG.
The volume of the etching stopper layer 14 is smaller than that of the etching stopper layer 14 of the semiconductor device formed by the manufacturing method shown in FIG. Therefore, the effective dielectric constant between the wirings and between the wiring layers is reduced by the reduced volume of the etching stopper layer 14.

In the manufacturing process shown in FIG.
Since the wiring groove 21 is also formed in the etching stopper layer 14 when forming the etching stopper layer 1, the wiring groove 21 formed in the etching stopper layer 14 is smaller than the etching stopper layer formed by the manufacturing method shown in FIG. Also has a reduced volume. Therefore, the effective dielectric constant between the wirings and between the wiring layers is reduced.

Next, an embodiment relating to the second semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG. FIG. 5 shows an example of a semiconductor device formed by the method of the present invention based on the first via (FV) method.

As shown in FIG. 5, an insulating film 5 covering a transistor, a capacitor and the like (not shown) formed on a semiconductor substrate (not shown) such as a silicon substrate.
1 is formed. On the insulating film 51, a first wiring 52 having a trench wiring structure is formed. Further, on the insulating film 51 and below and around the region where the wiring groove is formed,
An ILD (Inter Lead) that serves as an etching stopper layer and covers the first wiring 52 and serves as an insulating film between wiring layers.
vel Dielectrics) film 53 is formed to a thickness of, for example, 300 nm. The wiring groove is formed in the etching stopper layer 1 even if a mask misalignment occurs in an exposure step when forming the wiring groove.
4 is a range formed on The ILD film 53 is formed of, for example, silicon oxide. Alternatively, it may be formed using silicon oxynitride, silicon nitride, or the like.

Further, on the insulating film 51, the ILD
An IMD (Inter Metal Dielectrics) film 54 which covers the film 53 and serves as an insulating film between wirings and some wiring layers.
Is formed to a thickness of 300 nm on the ILD film 53, for example. This IMD film 54 may be formed of an insulating film made of the same material as the ILD film 53, or
It may be formed of a low dielectric constant organic film such as a CB film, a polyimide film, and an amorphous carbon film.

On the IMD film 54, a hard mask layer 55 formed by depositing, for example, silicon oxide to a thickness of 200 nm is formed. The hard mask layer 55 has an opening 56 serving as a wiring groove pattern. Further, a wiring groove 61 is formed in the ILD film 54 below the opening 56, and a connection hole 62 is formed in the ILD film 54.

When a diffusion preventing layer such as a silicon nitride film is formed on first wiring 52, connection hole 62 penetrates the diffusion preventing layer and reaches the surface of first wiring 52. It is formed as follows.

Further, a barrier metal layer 63 is formed on each inner surface of the wiring groove 61 and the connection hole 62.
, A second wiring 64 made of, for example, copper or a copper alloy is formed through the barrier metal layer 63,
A plug 65 made of, for example, copper or a copper alloy is formed inside the connection hole 62 via the barrier metal layer 63.

Further, on the IMD film 54 and the second wiring 64, an ILD film 53 similar to that described above,
IMD film 54, connection hole 62, wiring groove 61, second wiring 6
4. It is also possible to form the plugs 65 and the like and stack the wiring structure.

In the second semiconductor device, the ILD film 53 as an insulating film between the wiring layers is formed only below and around the region where the wiring groove 61 is formed.
The volume of the silicon oxide film formed by the method is smaller than that of the insulating film between the wiring layers. Normally, the silicon oxide film has a high dielectric constant of about 4.2. Therefore, by reducing the ILD film 53 formed of a film having such a high dielectric constant, the distance between the wirings (between the second wirings 64 and 64) is reduced. while)
Or between wiring layers (between the first wiring 52 and the second wiring 64)
Is reduced, and the capacitance between wiring layers is reduced.

Next, an embodiment relating to the second method of manufacturing a semiconductor device will be described with reference to the manufacturing process diagram of FIG.
FIG. 6 shows an example of a semiconductor device formed by the method of the present invention based on the FV method, and the same components as those described with reference to FIG. 5 are denoted by the same reference numerals.

Although not shown, after forming a transistor, a capacitor and the like (not shown) on a semiconductor substrate (for example, a silicon substrate), an insulating film 51 is formed as shown in FIG. Next, the first wiring 5 is formed on the insulating film 51.
2 is formed by, for example, a generally known trench wiring technique. An ILD film 53 which covers the first wiring 52 and serves as an insulating film between wiring layers is formed on the insulating film 51 by depositing silicon oxide to a thickness of 300 nm by, for example, a plasma CVD method. In this plasma CVD method, monosilane (SiH ₄ ) or disilane (S
A silane-based gas such as i ₂ H ₆ ) is used. For example, monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂
O), the film was formed by setting the substrate temperature to 350 ° C. and the pressure of the film formation atmosphere to 1 kPa. The ILD film 1
3 can be formed of a material such as silicon oxynitride or silicon nitride.

Next, as shown in FIG. 6B, the ILD film 53 is patterned by using a usual lithography technique and an etching technique. First, the ILD film 53
After a resist film 71 is formed thereon, an opening 72 for forming, for example, a connection hole reaching the first wiring 52 is formed in the resist film 71 by a lithography technique, and a region for forming a wiring groove is formed. And the resist film 71 is left on the peripheral region thereof. Thereafter, by etching using the resist film 71 as an etching mask, the ILD film 53 is etched to form a connection hole 62 reaching the first wiring 52, and to form a connection groove under and around a region where a wiring groove is to be formed. The ILD film 53 is removed from other portions except for the ILD film 53. The periphery of the region below the region in which the wiring groove is formed is such that the wiring groove is not
The range is formed on the film 53. After that, the resist film 71 used as the etching mask is removed by a normal ashing process. In the drawings, the resist film 71 is used.
The state before ashing was shown.

Next, as shown in FIG. 6C, the IMD film 54 which covers the ILD film 53 on the insulating film 51 and serves as an insulating film between wirings, and also serves as an insulating film between some wiring layers. Form. The IMD film 54 is formed by, for example, the above-described IL.
It is formed of polyaryl ether by the same forming method as that for forming the D film 53. The film thickness is, for example, 30 on the ILD film 53.
It was set to 0 nm.

Further, a hard mask layer 55 is formed on the IMD film 54. The hard mask layer 55 is formed, for example, by adding silicon oxide to a plasma CVD method.
It is formed by depositing to a thickness of 00 nm.

Next, the hard mask layer 55 is patterned by using a usual lithography technique and an etching technique. First, after forming a resist film 73 on the hard mask 55, an opening 74 for forming a wiring groove is formed by lithography.

Subsequently, as shown in FIG. 6D, the hard mask layer 55 is etched using the resist film 73 as an etching mask to form an opening 56 for forming a wiring groove. . In these etchings, as an example, a magnetron etching apparatus is used, and octafluorobutene (C ₄ F ₈ ) (supply flow rate is set to, for example, 10 sccm) and argon (Ar) are used as etching gases.
[Supply flow rate is set to, for example, 200 sccm] and oxygen (O
₂ ) [The supply flow rate is set to ₂ sccm, for example]
The substrate temperature was set at 20 ° C., the power was set at 2 kW, and the pressure of the etching atmosphere was set at 8 Pa.

Using the hard mask layer 55 as an etching mask, the IMD film 54 is etched to
Form one. In this etching, the ILD film 53 is used.
Becomes the bottom of the wiring groove 61 and stops the etching for forming the wiring groove 61. Subsequently, using the ILD film 53 as an etching mask, the connection hole 62 in which the IMD film 54 is embedded is opened again. In these etchings,
As an example, a helicon wave plasma etching apparatus is used, ammonia (NH ₃ ) is used as an etching gas (a supply flow rate is set to, for example, 100 sccm), and a substrate temperature is set to 1.
00 ° C, source power 1.5 kW, bias power 10
0 W and the pressure of the etching atmosphere were set to 1 Pa. Alternatively, using a general ECR plasma etching apparatus, nitrogen (N ₂ ) and helium (H
e), the etching conditions are as follows: the pressure of the etching atmosphere is 1 Pa, the microwave power is 1 kW, the bias RF
Set the power to 300W.

The resist film 73 is formed of the IMD film 5
4 is removed when etching. Also, the first wiring 5
In the case where a diffusion preventing layer such as a silicon nitride film is formed on the second wiring 2, after forming the connection hole 62, the diffusion preventing layer is removed to expose the surface of the first wiring 52. Perform etching.

Thereafter, as shown in FIG. 3 (5), the barrier metal layer 6 is formed on the inner surfaces of the wiring grooves 61 and the connection holes 62 by sputtering, vapor deposition or CVD.
3 and a copper film is further formed. At this time, the barrier metal layer 63 and the copper film are also formed on the hard mask layer 55. The barrier metal layer 63 is formed by depositing, for example, tantalum nitride or tantalum to a thickness of 50 nm. Note that, prior to the formation of the barrier metal layer 63, it is preferable to perform sputter etching in order to remove a natural oxide film or the like formed on the surface of the first wiring 52. After the sputter etching, the barrier metal layer 63 is preferably formed without being exposed to an oxidizing atmosphere (for example, the atmosphere). For example, so-called in situ processing is performed.

Thereafter, the connection holes 62 are formed by electrolytic plating.
And the wiring groove 61 is buried with copper. At this time, a copper film is also formed on the hard mask layer 55. Next, the excess copper film and the barrier metal layer 63 on the hard mask layer 55 are removed by CMP to form the second wiring 64 inside the wiring groove 61 and the first wiring 52 inside the connection hole 62. Is formed to be electrically connected to the plug 65. The above C
During the MP, the hard mask layer 55 serves as a polishing stopper, but the hard mask layer 55 may be completely removed depending on the thickness of the hard mask layer 55. Although copper is buried in the above example, another metal material such as aluminum, which is a wiring material, may be buried.

Although not shown, the ILD film 13
By repeating the steps from the step of forming the second wiring 64 to the step of forming the second wiring 64 and the plug 65, a multilayer wiring can be formed.

In the method of manufacturing a semiconductor device described in the second embodiment, the IMD film 5 serving as an insulating film between wiring layers is provided.
4 is formed only below and around the region where the wiring groove 61 is formed, and the connection hole 62 is formed in the ILD film 53 which is an insulating film between the wirings. As a result, the amount of the insulating film between the wiring layers formed of a material having a high dielectric constant such as a silicon-based oxide film is reduced. Thus, the IL made of the silicon oxide film
By reducing the D film 53, the dielectric constant between the wiring layers (between the first wiring 53 and the second wiring 64) can be kept low. Therefore, the capacitance between wirings is reduced.

Also, the ILD serving as an etching stopper layer
Since the film 53 is formed only below and around the region where the wiring groove is formed, when the wiring groove 61 is formed in the IMD film 54 which is an insulating film between the wirings, the wiring groove 61 becomes an insulating film between the wiring layers. Is not formed outside the ILD film 53. Therefore, the wiring groove 61 is formed at a predetermined depth.
In addition, when the wiring groove 61 is formed, even if a mask misalignment occurs in the exposure step of the lithography step, a layer having etching selectivity is also formed around the area below the area where the wiring groove 61 is formed. The wiring groove 61 is not formed outside the ILD film 53. Therefore, it does not occur that the wiring groove 61 is formed too deeply to cause a short circuit with the first wiring 52 as the lower wiring.

The ILD film 13, IMD film 16,
In addition, the IMD film 54 can be formed of a fluororesin or xerogel. Examples of the fluororesin include fluorocarbon films (for example, cyclic fluororesin, Teflon (PTFE), etc.), amorphous Teflon (for example, manufactured by DuPont: Teflon AF (trade name), etc.),
Fluorinated aryl ethers or fluorinated polyimides can be used. An example of the xerogel is porous silica.

In order to form a film of the fluororesin, a precursor of the fluororesin is applied by a spin coater, and thereafter,
Cure at 300-450 ° C. Materials such as fluorinated amorphous carbon are acetylene (C ₂ H ₂ ),
Plasma CVD using fluorocarbon gas [for example, octafluorobutene (C ₄ F ₈ )] as a process gas
It is possible to form a film by a method. Also in this case, curing is performed at 300 ° C. to 450 ° C. after film formation. The amorphous Teflon is not limited to Teflon AF, but may be any as long as it has a structure represented by the following chemical formula (1).

[0089]

Embedded image

As the ILD film 13 and the IMD film 16, it is possible to use a cyclopolymerized fluorinated polymer resin [for example, Cytop (trade name)]. Cyclopolymerized fluorinated polymer resin is not limited to the above Cytop,
Any material having a structure represented by the following chemical formula (2) may be used.

[0091]

Embedded image

The ILD film 13 and the IMD film 16 are made of a fluorinated polyallyl ether-based resin [for example, FLAR
E (trade name)]. The fluorinated polyallyl ether-based resin is not limited to FLARE, and may be any resin having a structure represented by the following chemical formula (3).

[0093]

Embedded image

When the xerogel is used for the ILD film 13 and the IMD film 16, for example, Nanoporous Silica developed by Nanograss is used.
Was formed using a spin coating apparatus. The above Nano
porous silica is a kind of porous silica, and the xerogel that can be used in the present invention is the above-mentioned N
It is not limited to ananoporous Silica. That is, a resin formed by applying a silanol resin having a relatively high molecular weight alkyl group such as aromatic on a substrate, gelling it, and performing a hydrophobic treatment using a silane coupling agent or hydrogenation treatment. Therefore, any xerogel can be applied.

[0095]

As described above, according to the first semiconductor device of the present invention, the etching stopper layer is formed only below and around the region where the wiring groove is formed, and the etching stopper layer is formed. Since the opening for forming the connection hole is formed in the layer, the amount of the etching stopper layer formed between the two insulating films is smaller than that of the conventional etching stopper layer. As described above, since the amount of the etching stopper layer usually formed of a material having a high dielectric constant is reduced, the effective dielectric constant between wirings and between wiring layers is reduced, and the capacitance between wirings and the capacitance between wiring layers are reduced. Reduction can be achieved.

According to the first method for manufacturing a semiconductor device, since the etching stopper layer is formed only below and around the region where the wiring groove is formed, the amount of the etching stopper layer formed of a material having a high dielectric constant is reduced. Can be formed less than the conventional etching stopper layer. Therefore,
Since the effective dielectric constant between wirings and between wiring layers can be suppressed lower than that of the conventional configuration, the capacitance between wirings,
The capacitance between wirings can be reduced.

According to the second semiconductor device, since the insulating film between the wiring layers is formed only under and around the region where the wiring groove is formed, the insulating film between the wiring layers formed by the conventional silicon oxide film is formed. The volume is smaller than that of the insulating film. Normally, a silicon oxide film has a dielectric constant of about 4.2, which is higher than that of an organic insulating material. And the capacitance between wiring layers can be reduced.

According to the second method for manufacturing a semiconductor device, the insulating film between the wiring layers is formed only below and around the region where the wiring groove is formed, so that the insulating film between the wirings formed of a material having a high dielectric constant The amount of the insulating film can be formed smaller than that of the conventional one. Therefore, the effective dielectric constant of the insulating film between the wiring layers can be suppressed to be lower than that of the conventional structure, so that the capacitance between the wiring layers can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating an embodiment according to a first semiconductor device of the present invention.

FIG. 2 is a schematic configuration cross-sectional view illustrating a modification of the embodiment relating to the first semiconductor device.

FIG. 3 is a manufacturing process diagram illustrating an embodiment relating to a first method for manufacturing a semiconductor device.

FIG. 4 is a manufacturing process diagram illustrating a modification of the embodiment relating to the first method of manufacturing a semiconductor device.

FIG. 5 is a schematic cross-sectional view illustrating an embodiment according to a second semiconductor device of the present invention.

FIG. 6 is a manufacturing process diagram illustrating an embodiment relating to a second method for manufacturing a semiconductor device.

FIG. 7 is a manufacturing process diagram illustrating a conventional SACC method.

[Explanation of symbols]

13 ... ILD film, 14 ... etching stopper layer, 15 ...
Opening, 16: IMD film, 21: Wiring groove, 22: Connection hole

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H01L 21/3205 H01L 21/88 B 21/90 V SF term (reference) 4M104 BB04 DD08 DD20 DD52 DD65 DD67 EE14 EE17 EE18 FF13 FF16 FF22 HH20 5F004 BA13 BA14 BA20 DA00 DA01 DA22 DA23 DA25 DA26 DB03 DB07 DB23 EA23 EA28 EB01 EB02 EB03 5F033 HH08 HH11 HH12 JJ01 JJ08 JJ11 JJ12 MM02 Q04 Q25 Q08 Q27 Q08 Q27 Q08 Q27 Q08 Q27 Q28 RR24 SS15 SS22 TT04 XX25

Claims (6)

[Claims] 1. A semiconductor comprising: an insulating film between wiring layers in which connection holes are formed; an insulating film between wirings in which wiring grooves are formed; and an etching stopper layer formed between the two insulating films. In the device, the etching stopper layer has an opening for forming a connection hole, and is formed only below and around a region where the wiring groove is formed. . 2. The semiconductor device according to claim 1, wherein said wiring groove is formed from an insulating film between said wirings to said etching stopper layer. 3. A step of forming an insulating film between wiring layers in which connection holes are formed; a step of forming an etching stopper layer on the insulating film between the wiring layers; and an insulating film between wirings in which wiring grooves are formed. Forming the etching stopper layer only below and around a region where the wiring groove is formed, and etching an opening for forming a connection hole. A method for manufacturing a semiconductor device, wherein the method is formed on a stopper layer. 4. The semiconductor according to claim 3, wherein when forming the wiring groove in the insulating film between the wirings, the wiring groove is formed from the insulating film between the wirings to the etching stopper layer. Device manufacturing method. 5. A semiconductor device comprising: an insulating film between wiring layers in which connection holes are formed; and an insulating film between wirings in which wiring grooves are formed and which has etching selectivity. 2. The semiconductor device according to claim 1, wherein the insulating film between the wiring layers is formed only below and around a region where the wiring groove is formed. 6. A semiconductor comprising: a step of forming an insulating film between wiring layers in which connection holes are formed; and a step of forming an insulating film between wirings in which wiring grooves are formed on the insulating film between the wiring layers. A semiconductor device, wherein an insulating film between the wiring layers is formed only below and around a region where the wiring groove is formed, and the connection hole is formed in the insulating film between the wirings. Device manufacturing method.