CN101359618B - Thru hole filling method, thru hole filling construction and thru hole manufacturing method - Google Patents
Thru hole filling method, thru hole filling construction and thru hole manufacturing method Download PDFInfo
- Publication number
- CN101359618B CN101359618B CN2007100446347A CN200710044634A CN101359618B CN 101359618 B CN101359618 B CN 101359618B CN 2007100446347 A CN2007100446347 A CN 2007100446347A CN 200710044634 A CN200710044634 A CN 200710044634A CN 101359618 B CN101359618 B CN 101359618B
- Authority
- CN
- China
- Prior art keywords
- hole
- dusts
- dry film
- filling
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a through hole filling method, including the following steps: providing a substrate which has a through hole on the surface; developing a dry film on the surface of the substrate; exposing and developing the dry film so as to form an opening on the dry film; and filling the through hole from the opening of the dry film. The invention further discloses a through hole filling structure and a through hole formation method. The invention solves the problem that currently filling light-sensitive lacquer into a through hole with big height-depth ratio is difficult and consumes a big amount of energy during the exposition process, thus improving through hole filling efficiency.
Description
Technical field
The present invention relates to encapsulation procedure, relate in particular to method for filling through hole, through hole interstitital texture and through hole manufacture method in the encapsulation procedure.
Background technology
As everyone knows, encapsulation technology is exactly a kind of technology with the chip packing in fact, and this packing is necessary for chip.Because chip must be isolated from the outside, to prevent owing to airborne impurity causes electric property to descend to the corrosion of chip circuit.On the other hand, the chip after the encapsulation also is more convenient for installing and transportation.Because the quality of encapsulation technology also directly has influence on design and the manufacturing of the performance of chip self performance and the PCB that is attached thereto (printed circuit board), so it is vital.Encapsulation also can be described as installs the shell that semiconductor integrated circuit chip is used, and it not only plays a part to lay, fix, seal, protect chip and increased thermal conductivity energy, but also is the bridge of linking up the chip internal world and external circuit.In simple terms, encapsulation is wired to the contact on the chip on the pin of package casing exactly, and these pins connect by the lead on the printed circuit board (PCB) and other devices again.Therefore, encapsulation technology is unusual the key link in the IC industry.
At present, through years of development, encapsulation technology experienced from the real packing technique of initial stitch plug-in type to surface mounting technology again to ball grid array terminal BGA (ball grid array) type encapsulation technology again to up-to-date three-dimensional packaging technology (3D Package).Wherein, three-dimensional packaging technology can be divided into three types of the three-dimension packaging of the three-dimension packaging of the three-dimension packaging that encapsulates lamination, chip-stack and wafer lamination again.The advantage of three-dimension packaging is to improve the density of interconnection line, reduces the overall height of device profile.Since might be together with dissimilar chip laminates, and have higher interconnection line density, so three-dimensional packaging technology has good application prospects.In the three-dimensional systematic encapsulation technology, (TSV, Through-Silicon-Via) access path of electrode can foreshorten to the thickness that has only a chip to the silicon through hole, so can the shortest and the highest interconnection of integrated level of realizing route.By the system-level Integrated Solution of silicon through hole realization interconnection, can when reducing chip area, alleviate the interconnect delay problem.If the short interconnection line with vertical direction replaces long interconnection lines a large amount of in the two-dimensional structure, the performance of logical circuit is improved greatly.For example, by the gate on the critical path is placed on a plurality of active layers, just they very closely can be arranged.Also voltage and/or the different circuit of performance requirement can be placed on the different layers.
Critical process based on the three-dimension packaging of silicon through hole manufacturing technology comprises: silicon through hole undercutting high-aspect-ratio (〉 5:1), silicon through hole dielectric and electric conducting material are filled, the attenuate of wafer, chip to chip, chip to wafer or wafer to the accurate aligning between the wafer, the caking property bonding method of low temperature etc.That silicon through hole undercutting is at present adopted usually is Deep Reaction ion(ic) etching (DRIE, Deep Reactive Ion Etch), and oneself surpasses 50 deep trouth silicon structure through being enough to the etching depth-to-width ratio current Deep Reaction ion(ic) etching system.At for example application number is to find more information relevant with the Deep Reaction ion(ic) etching in 00119596.4 the Chinese patent application.
Yet, surpass 50 just because of the etching depth-to-width ratio, brought challenge also for the fill process of follow-up silicon through hole electric conducting material.At present, form photoresist at the substrate surface that forms the silicon through hole usually,, form the photoresist opening, fill for the silicon through hole at the photoresist opening part then by resist exposure is developed for the filling of the electric conducting material of silicon through hole.Because photoresist generally all is liquid, form in the process of photoresist at the substrate surface that forms the silicon through hole, photoresist is packed into relatively difficulty of the higher deep hole of depth-to-width ratio, and after the exposure process for photoresist in, will just need more exposure energy for the resist exposure of deep hole, and often exposure accuracy can be affected also.
Summary of the invention
The invention provides a kind of method for filling through hole, through hole interstitital texture and through hole manufacture method, photoresist is inserted difficulty in the solution prior art through hole fill process, and the bigger problem of exposure energy consumption.
For addressing the above problem, the invention provides a kind of method for filling through hole, comprise, provide the surface to have the substrate of through hole, on described substrate, form dry film,, fill for described through hole at described dry film opening part for described dry film exposure, the formation dry film opening that develops.
The present invention also provides a kind of through hole interstitital texture, comprises, the surface has the substrate of through hole and the dry film of described substrate surface.
The present invention also provides a kind of through hole manufacture method, comprise the through hole filling, wherein said through hole is filled and is comprised, provide the surface to have the substrate of through hole, on described substrate, form dry film, for described dry film exposure, the formation dry film opening that develops, fill for described through hole at described dry film opening part.
Optionally, the thickness of described dry film is 10 to 120um.
Optionally, described dry film forms in wafer surface under the environment of vacuum and low pressure, and described low pressure is less than atmospheric pressure, and described low pressure is less than 200 millitorrs.
Optionally, fill the employing electric plating method for described through hole.
Optionally, described packing material is a copper.
Compared with prior art, such scheme has the following advantages: such scheme method for filling through hole, through hole interstitital texture and through hole manufacture method are passed through dry film as the photoresist layer material, avoided prior art to adopt liquid photoresist to insert the problem of deep hole difficulty, and when exposing for dry film, also reduced the energy of exposure, thereby the efficient that through hole is filled is improved.
Description of drawings
Fig. 1 is an embodiment of the invention method for filling through hole flow chart;
Fig. 2 to Fig. 8 is an embodiment of the invention method for filling through hole schematic diagram;
Fig. 9 is an embodiment of the invention through hole manufacture method flow chart.
Embodiment
Method for filling through hole of the present invention, through hole interstitital texture and through hole manufacture method are to select for use dry film as photoresist layer in the formation photoresist layer in the through hole fill process, and form dry film under the environment of vacuum, low pressure.
Method for filling through hole of the present invention, through hole interstitital texture and through hole manufacture method are elaborated by preferred embodiment, so that the description of method for filling through hole and through hole manufacture method is clearer.
With reference to shown in Figure 1, embodiment of the invention method for filling through hole comprises the steps,
Step s1 provides the surface to have the substrate of through hole;
Step s2 forms articulamentum and inculating crystal layer successively at described substrate surface;
Step s3 forms dry film at described substrate surface;
Step s4 for described dry film exposure imaging, forms the dry film opening;
Step s5, at described dry film opening part for described through hole filled conductive material;
Step s6 removes dry film and articulamentum and inculating crystal layer.
In conjunction with illustrated in figures 1 and 2, the substrate 10 that provides the surface to have through hole.Described substrate is generally silicon substrate.The high aspect ratio vias that described through hole just is to use the method for for example Deep Reaction ion(ic) etching to form, promptly the ratio of the degree of depth of through hole and width is greater than 5 through hole.What described Deep Reaction ion(ic) etching was adopted is high-density plasma, present induction type inductively coupled plasma (ICP, Inductively CoupledPlasma) etch system has become the preferable selection of Deep Reaction ion(ic) etching because high-density plasma and operational stability can be provided.
And, also be formed with dielectric side wall layer 11a on the sidewall of described through hole.Because silicon substrate itself also conducts electricity, so in through hole, need to form earlier dielectric side wall layer 11a before the filled conductive material to prevent forming current path in the through-hole side wall direction.The thickness of described dielectric side wall layer 11a is 1000 to 4000 dusts, for example 1000 dusts, 1200 dusts, 1400 dusts, 1600 dusts, 1800 dusts, 2000 dusts, 2200 dusts, 2400 dusts, 2600 dusts, 2800 dusts, 3000 dusts, 3200 dusts, 3400 dusts, 3600 dusts, 3800 dusts, 4000 dusts.Described dielectric side wall layer 11a can be SiO
2, SiON, Si
3N
4In any, wherein more preferably be SiO
2
In conjunction with Fig. 1 and shown in Figure 3, form articulamentum 12 and inculating crystal layer 13 successively at described substrate surface.The effect of described articulamentum 12 is to make the filled conductive material of through hole to keep good gluing with substrate 10.The thickness of described articulamentum 11 is 100 to 1000 dusts, for example 100 dusts, 120 dusts, 140 dusts, 160 dusts, 180 dusts, 200 dusts, 220 dusts, 240 dusts, 260 dusts, 280 dusts, 300 dusts, 320 dusts, 340 dusts, 360 dusts, 380 dusts, 400 dusts, 420 dusts, 440 dusts, 460 dusts, 480 dusts, 500 dusts, 520 dusts, 540 dusts, 560 dusts, 580 dusts, 600 dusts, 620 dusts, 640 dusts, 660 dusts, 680 dusts, 700 dusts, 720 dusts, 740 dusts, 760 dusts, 780 dusts, 800 dusts, 820 dusts, 840 dusts, 860 dusts, 880 dusts, 900 dusts, 920 dusts, 940 dusts, 960 dusts, 980 dusts, 1000 dusts.Described articulamentum 11 adopts the method for evaporation or sputter to form, and wherein more excellent method is sputter.Described articulamentum 11 is Ti or TiN, wherein more preferably is Ti.Ti and oxide, for example SiO
2Good adhesive is arranged, therefore can make the electric conducting material of filling keep good being connected, and Ti can also form the TiSi of low-resistance with pasc reaction with through hole
x, reduce through hole resistance.In the present embodiment, also can form one deck inculating crystal layer 13 on articulamentum 11, the effect of described inculating crystal layer 13 is in order to guarantee that follow-up filled conductive material is packed into the success rate of through hole.The thickness of described inculating crystal layer 13 is 1000 to 4000 dusts.For example 1200 dusts, 1400 dusts, 1600 dusts, 1800 dusts, 2000 dusts, 2200 dusts, 2400 dusts, 2600 dusts, 2800 dusts, 3000 dusts, 3200 dusts, 3400 dusts, 3600 dusts, 3800 dusts, 4000 dusts.The material of described inculating crystal layer 13 is identical with the filled conductive material.Described inculating crystal layer 13 adopts electric plating method to form.
In conjunction with Fig. 1 and shown in Figure 4, form dry film 14 at described substrate surface.As previously mentioned, liquid photoresist is relatively more difficult in being packed into the through hole of high-aspect-ratio, and it is also very big that follow-up exposure technology will make that the photoresist in the deep hole also is exposed to spent exposure energy, and therefore solid-state dry film just becomes one and selects preferably.Forming dry films 14 on substrate 10 surface all is under atmospheric pressure to adopt roller directly dry film 14 to be flattened on substrate 10 surfaces get final product usually, all can produce bubble on the contact-making surface of dry film 14 and substrate 10 still usually like this, influences subsequent technique.Form the method that dry film 14 is to use the vacuum low-pressure pad pasting in the present embodiment, promptly under the environment of vacuum, low pressure, form dry film 14.Described low pressure is less than atmospheric pressure, and further described low pressure is less than 200 millitorrs (mt), for example 10mt, 40mt, 50mt, 100mt, 120mt, 140mt, 160mt, 180mt.After described dry film 14 was affixed on substrate 10 surfaces, because the air pressure in the deep hole is littler than atmospheric pressure, thereby under atmospheric pressure, dry film 14 just had been pressed in substrate 10 surfaces tightly.And, also avoided producing on the contact-making surface of dry film 14 and substrate 10 situation of bubble because dry film 14 is to be affixed on substrate 10 surfaces under the environment of vacuum.The thickness of described dry film 14 is 10 to 120um, for example 10um, 12.5um, 20um, 25um, 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, 70um, 75um, 80um, 85um, 90um, 95um, 100um, 105um, 110um, 115um, 120um wherein more preferably are 12.5um.
By described step, just form the through hole interstitital texture of the embodiment of the invention, comprise that the surface has the substrate 10 of through hole, the dielectric side wall layer 11a on the through-hole side wall, the articulamentum 12 on substrate 10 surfaces, inculating crystal layer 13 on the articulamentum 12 and the dry film 14 on the inculating crystal layer 13.
In conjunction with Fig. 1 and shown in Figure 5, for described dry film 14 exposures, development, to form the dry film opening.At first define the shape and the size of opening by mask pattern, expose for dry film 14 then, the normal light source that adopts has for example high-pressure mercury lamp, beam-plasma etc., after overexposure, the dry film that is exposed the zone is that the dry film of opening part dissolves, use developer flush away dry film at last again, just can on dry film 14, form opening.
In conjunction with Fig. 1 and shown in Figure 6, at described dry film opening part for described through hole filled conductive material 15.Described filling for through hole all will make the horizontal plane of filled conductive material exceed through hole plane 3 to 10um usually, for example 3um, 3.5um, 4um, 4.5um, 5um, 5.5um, 6um, 6.5um, 7um, 7.5um, 8um, 8.5um, 9um, 9.5um, 10um.The packing material of described through hole is electric conducting materials such as copper, and copper is because resistivity is low as preferred electric conducting material.Describedly fill the employing electric plating method for through hole.Method with electro-coppering is exemplified below: described substrate with through hole is soaked in the electroplate liquid of copper ions, substrate is connected to negative electrode, electroplate liquid is connected to anode, between negative electrode and anode, switch on then, make copper ion in the electroplate liquid deposit in the through hole of dry film opening part by electric field action and form the copper connector.
In conjunction with Fig. 1 and shown in Figure 7, remove dry film 14.After the filling of having finished for through hole, just need to remove dry film 14.Removing dry film 14 used methods generally is to adopt dry process or wet processing or dry method and wet processing process combined.Dry process is aerating oxygen and the dry film decomposition photoresist that reacts at high temperature.And wet processing is to adopt chemical reagent flush away photoresist.The method that the embodiment of the invention adopts is to use compounded organic solvent to remove the wet processing of dry film 14.
In conjunction with Fig. 1 and shown in Figure 8, after having removed dry film 14, also need to remove substrate 10 inculating crystal layer 13 and the articulamentums 11 of surface except that electric conducting material 15 overlay areas.The method of removing inculating crystal layer 13 and articulamentum 11 is to adopt the method for wet etching, removes inculating crystal layer 13 and articulamentum 11 by the method for spraying acid solution for substrate 10 or substrate 10 is soaked in the acid solution.
With reference to shown in Figure 9, embodiment of the invention through hole manufacture method comprises the following steps,
Step s10 provides substrate;
Step s11 forms through hole at described substrate surface;
Step s12 forms articulamentum and inculating crystal layer successively at described substrate surface;
Step s13 forms dry film at described substrate surface;
Step s14 for described dry film exposure, development, forms the dry film opening;
Step s15, at described dry film opening part for described through hole filled conductive material;
Step s16 removes dry film and articulamentum and inculating crystal layer.
With reference to shown in Figure 9, described substrate has all formed function element usually thereon.Foregoing, in the three-dimensional systematic encapsulation technology, the access path of silicon through hole electrode can foreshorten to the thickness that has only a chip, so can the shortest and the highest interconnection of integrated level of realizing route.Therefore described silicon through hole all is to form in the silicon substrate of chip back.
In conjunction with Fig. 9 and shown in Figure 2, form through hole on described substrate 10 surfaces.Described through hole all is the through hole of high-aspect-ratio generally, and promptly the ratio of the degree of depth of through hole and width is greater than 5 through hole.What form the common employing of described high aspect ratio vias is Deep Reaction ion(ic) etching or laser drill, and what wherein optimize is the Deep Reaction ion(ic) etching.What described Deep Reaction ion(ic) etching was adopted is high-density plasma, and induction type inductively coupled plasma etch system has become the preferable selection of Deep Reaction ion(ic) etching because high-density plasma and operational stability can be provided at present.
And, also be formed with dielectric side wall layer 11a on the sidewall of described through hole.Because silicon substrate itself also conducts electricity, so in through hole, need to form earlier dielectric side wall layer 11a before the filled conductive material to prevent forming current path in the through-hole side wall direction.The thickness of described dielectric side wall layer 11a is 1000 to 4000 dusts, for example 1000 dusts, 1200 dusts, 1400 dusts, 1600 dusts, 1800 dusts, 2000 dusts, 2200 dusts, 2400 dusts, 2600 dusts, 2800 dusts, 3000 dusts, 3200 dusts, 3400 dusts, 3600 dusts, 3800 dusts, 4000 dusts.Described dielectric side wall layer 11a can be SiO
2, SiON, Si
3N
4In any, wherein more preferably be SiO
2
In conjunction with Fig. 9 and shown in Figure 3, form articulamentum 12 and inculating crystal layer 13 successively at described substrate surface.The effect of described articulamentum 12 is to make the filled conductive material of through hole to keep good gluing with substrate 10.The thickness of described articulamentum 11 is 100 to 1000 dusts, for example 100 dusts, 120 dusts, 140 dusts, 160 dusts, 180 dusts, 200 dusts, 220 dusts, 240 dusts, 260 dusts, 280 dusts, 300 dusts, 320 dusts, 340 dusts, 360 dusts, 380 dusts, 400 dusts, 420 dusts, 440 dusts, 460 dusts, 480 dusts, 500 dusts, 520 dusts, 540 dusts, 560 dusts, 580 dusts, 600 dusts, 620 dusts, 640 dusts, 660 dusts, 680 dusts, 700 dusts, 720 dusts, 740 dusts, 760 dusts, 780 dusts, 800 dusts, 820 dusts, 840 dusts, 860 dusts, 880 dusts, 900 dusts, 920 dusts, 940 dusts, 960 dusts, 980 dusts, 1000 dusts.Described articulamentum 11 adopts the method for evaporation or sputter to form, and wherein more excellent method is sputter.Described articulamentum 11 is Ti or TiN, wherein more preferably is Ti.Ti and oxide, for example SiO
2Good adhesive is arranged, therefore can make the electric conducting material of filling keep good being connected, and Ti can also form the TiSi of low-resistance with pasc reaction with through hole
x, reduce through hole resistance.In the present embodiment, also can form one deck inculating crystal layer 13 on articulamentum 11, the effect of described inculating crystal layer 13 is in order to guarantee that follow-up filled conductive material is packed into the success rate of through hole.The thickness of described inculating crystal layer 13 is 1000 to 4000 dusts.For example 1200 dusts, 1400 dusts, 1600 dusts, 1800 dusts, 2000 dusts, 2200 dusts, 2400 dusts, 2600 dusts, 2800 dusts, 3000 dusts, 3200 dusts, 3400 dusts, 3600 dusts, 3800 dusts, 4000 dusts.The material of described inculating crystal layer 13 is identical with the filled conductive material.Described inculating crystal layer 13 adopts electric plating method to form.
In conjunction with Fig. 9 and shown in Figure 4, form dry film 14 at described substrate surface.As previously mentioned, liquid photoresist is relatively more difficult in being packed into the through hole of high-aspect-ratio, and it is also very big that follow-up exposure technology will make that the photoresist in the deep hole also is exposed to spent exposure energy, and therefore solid-state dry film just becomes one and selects preferably.Forming dry films 14 on substrate 10 surface all is under atmospheric pressure to adopt roller directly dry film 14 to be flattened on substrate 10 surfaces get final product usually, all can produce bubble on the contact-making surface of dry film 14 and substrate 10 still usually like this, influences subsequent technique.Form the method that dry film 14 is to use the vacuum low-pressure pad pasting in the present embodiment, promptly under the environment of vacuum, low pressure, form dry film 14.Described low pressure is less than atmospheric pressure, and further described low pressure is less than 200 millitorrs (mt), for example 10mt, 40mt, 50mt, 100mt, 120mt, 140mt, 160mt, 180mt.After described dry film 14 was affixed on substrate 10 surfaces, because the air pressure in the deep hole is littler than atmospheric pressure, thereby under atmospheric pressure, dry film 14 just had been pressed in substrate 10 surfaces tightly.And, also avoided producing on the contact-making surface of dry film 14 and substrate 10 situation of bubble because dry film 14 is to be affixed on substrate 10 surfaces under the environment of vacuum.The thickness of described dry film 14 is 10 to 120um, for example 10um, 12.5um, 20um, 25um, 30um, 35um, 40um, 45um, 50um, 55um, 60um, 65um, 70um, 75um, 80um, 85um, 90um, 95um, 100um, 105um, 110um, 115um, 120um wherein more preferably are 12.5um.
In conjunction with Fig. 9 and shown in Figure 5,, form the dry film opening for described dry film 14 exposures, development.At first define the shape and the size of opening by mask pattern, expose for dry film 14 then, the normal light source that adopts has for example high-pressure mercury lamp, beam-plasma etc., after overexposure, the dry film that is exposed the zone is that the dry film of opening part dissolves, use developer flush away dry film at last again, just can on dry film 14, form opening.
In conjunction with Fig. 9 and shown in Figure 6, at described dry film opening part for described through hole filled conductive material 15.Described filling for through hole all will make the horizontal plane of filled conductive material exceed through hole plane 3 to 10um usually, for example 3um, 3.5um, 4um, 4.5um, 5um, 5.5um, 6um, 6.5um, 7um, 7.5um, 8um, 8.5um, 9um, 9.5um, 10um.The packing material of described through hole is electric conducting materials such as copper, and copper is because resistivity is low as preferred electric conducting material.Describedly fill the employing electric plating method for through hole.Method with electro-coppering is exemplified below: described substrate with through hole is soaked in the electroplate liquid of copper ions, substrate is connected to negative electrode, electroplate liquid is connected to anode, between negative electrode and anode, switch on then, make copper ion in the electroplate liquid deposit in the through hole of dry film opening part by electric field action and form the copper connector.
In conjunction with Fig. 9 and shown in Figure 7, remove dry film 14.After the filling of having finished for through hole, just need to remove dry film 14.Removing dry film 14 used methods generally is to adopt dry process or wet processing or dry method and wet processing process combined.Dry process is aerating oxygen and the dry film decomposition photoresist that reacts at high temperature.And wet processing is to adopt chemical reagent flush away photoresist.The method that the embodiment of the invention adopts is to use compounded organic solvent to remove the wet processing of dry film 14.
In conjunction with Fig. 9 and shown in Figure 8, after having removed dry film 14, also need to remove substrate 10 inculating crystal layer 13 and the articulamentums 11 of surface except that electric conducting material 15 overlay areas.The method of removing inculating crystal layer 13 and articulamentum 11 is to adopt the method for wet etching, removes inculating crystal layer 13 and articulamentum 11 by the method for spraying acid solution for substrate 10 or substrate 10 is soaked in the acid solution.
In sum, such scheme method for filling through hole, through hole interstitital texture and through hole manufacture method are to select for use dry film as photoresist layer when the through hole fill process forms photoresist layer, and under the environment of vacuum, low pressure, form dry film, thereby when having solved prior art and using liquid photoresist to form photoresist layer, in deep hole, insert the photoresist difficulty, be easy to generate bubble, and the energy problem of higher of exposure consumption, thereby the efficient that through hole is filled improved.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. method for filling through hole, it is characterized in that, comprise, provide the surface to have the Semiconductor substrate of through hole, the depth-to-width ratio of described through hole is greater than 5, form dry film at described substrate surface,, fill for described through hole at described dry film opening part for described dry film exposure, the formation dry film opening that develops; Described dry film forms at substrate surface under less than the environment of 200 millitorrs at air pressure.
2. method for filling through hole as claimed in claim 1 is characterized in that, the thickness of described dry film is 10 to 120um.
3. method for filling through hole as claimed in claim 1 is characterized in that, before forming dry film, also forms articulamentum and inculating crystal layer successively at described substrate surface.
4. method for filling through hole as claimed in claim 3 is characterized in that, described articulamentum is Ti or TiN.
5. method for filling through hole as claimed in claim 3 is characterized in that, described inculating crystal layer adopts electric plating method to form.
6. method for filling through hole as claimed in claim 1 is characterized in that, fills the employing electric plating method for described through hole.
7. method for filling through hole as claimed in claim 6 is characterized in that, described material of filling is a copper.
8. through hole manufacture method, comprise the through hole filling, it is characterized in that, described through hole is filled and is comprised, the Semiconductor substrate that provides the surface to have through hole, the depth-to-width ratio of described through hole form dry film greater than 5 at described substrate surface, for described dry film exposure, the formation dry film opening that develops, fill for described through hole at described dry film opening part; Described dry film forms at substrate surface under less than the environment of 200 millitorrs at air pressure.
9. through hole manufacture method as claimed in claim 8 is characterized in that, the thickness of described dry film is 10 to 120um.
10. through hole manufacture method as claimed in claim 8 is characterized in that, before forming dry film, described substrate surface also forms articulamentum and inculating crystal layer successively.
11. through hole manufacture method as claimed in claim 10 is characterized in that, described articulamentum is Ti or TiN.
12. through hole manufacture method as claimed in claim 10 is characterized in that, described inculating crystal layer adopts electric plating method to form.
13. through hole manufacture method as claimed in claim 8 is characterized in that, fills the employing electric plating method for described through hole.
14. through hole manufacture method as claimed in claim 13 is characterized in that, described material of filling is a copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100446347A CN101359618B (en) | 2007-08-05 | 2007-08-05 | Thru hole filling method, thru hole filling construction and thru hole manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100446347A CN101359618B (en) | 2007-08-05 | 2007-08-05 | Thru hole filling method, thru hole filling construction and thru hole manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101359618A CN101359618A (en) | 2009-02-04 |
| CN101359618B true CN101359618B (en) | 2011-12-07 |
Family
ID=40332017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100446347A Active CN101359618B (en) | 2007-08-05 | 2007-08-05 | Thru hole filling method, thru hole filling construction and thru hole manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101359618B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130042B (en) * | 2010-12-14 | 2013-06-26 | 北京大学 | Method for manufacturing through hole interconnection structure |
| CN103219278A (en) * | 2012-01-19 | 2013-07-24 | 刘胜 | Metal filling process of silicon wafer through hole |
| CN103841773B (en) * | 2012-11-20 | 2017-05-31 | 深南电路有限公司 | A kind of method and device for electroplating blind hole |
| CN105261590B (en) * | 2015-10-09 | 2017-11-24 | 张家港市东大工业技术研究院 | Method for filling three-dimensional glass through hole with high depth-to-width ratio |
| CN106191862A (en) * | 2016-07-25 | 2016-12-07 | 中国电子科技集团公司第四十研究所 | A kind of method making solid metal hole on substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737350B1 (en) * | 1998-09-02 | 2004-05-18 | Tokyo Electron Limited | Method of manufacturing semiconductor device |
-
2007
- 2007-08-05 CN CN2007100446347A patent/CN101359618B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6737350B1 (en) * | 1998-09-02 | 2004-05-18 | Tokyo Electron Limited | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101359618A (en) | 2009-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7898095B2 (en) | Fiducial scheme adapted for stacked integrated circuits | |
| US9054165B2 (en) | Semiconductor devices including a through-substrate conductive member with an exposed end | |
| CN103500729B (en) | Silicon adapter plate structure and wafer level manufacture method thereof | |
| CN101359618B (en) | Thru hole filling method, thru hole filling construction and thru hole manufacturing method | |
| CN101399195A (en) | Thinning method for backing side of wafer | |
| JP2007053149A (en) | Semiconductor wafer and its manufacturing method | |
| US9338900B2 (en) | Interposer substrate and method of fabricating the same | |
| US9324580B2 (en) | Process for fabricating a circuit substrate | |
| CN103779351B (en) | Three-dimension packaging structure and its manufacture method | |
| CN112802757B (en) | Substrate preparation method, substrate structure, chip packaging method and chip packaging structure | |
| CN102738131B (en) | Semiconductor module, encapsulating structure and method for packing thereof | |
| CN102479766A (en) | Process of fabricating semiconductor device and through substrate via, and through substrate via structure therefrom | |
| KR20170109865A (en) | Printed circuit board, and semiconductor package having the same | |
| CN103299419A (en) | Conductive pads defined by embedded traces | |
| JP2016514909A (en) | Low cost interposer with oxide layer | |
| CN102148221A (en) | Electronic component package and manufacturing method therefor | |
| CN102945840B (en) | Semiconductor chip package and method for packing | |
| CN107452769B (en) | OLED (organic light emitting diode) micro display and bonding pad bonding method thereof | |
| CN202905706U (en) | Three-dimensional packaging structure | |
| KR101128895B1 (en) | Overlay Vernier of Semiconductor Device and Method for Manufacturing the same | |
| CN112864030B (en) | Packaging method and packaging structure of photoelectric detection chip | |
| CN111834317A (en) | Semiconductor device and method for manufacturing the same | |
| US20240030146A1 (en) | Multichip interconnecting packaging structure and manufacturing method thereof | |
| CN111383992B (en) | Method for manufacturing semiconductor device | |
| CN214588747U (en) | Board-level three-dimensional chip packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |