KR100688561B1 - Method for forming interconnections for semiconductor device - Google Patents

Abstract

In forming the metal wiring, a barrier film and a metal film are sequentially formed in a recess such as a dual damascene pattern formed in the interlayer insulating film, and the metal film is CMP to form a metal wiring layer remaining only in the recess, and then the barrier film is CMP. A metal wiring forming method of a semiconductor device comprising the step of performing a plasma treatment of the metal wiring layer before it is disclosed. During the plasma treatment of the metal wiring layer, a hilock occurs due to an increase in compressive stress in the metal wiring layer, and in the fine pattern, the resistivity of the metal wiring decreases due to the growth of metal grains. The heel lock generated at this time is removed through the subsequent barrier film and the interlayer insulating film CMP, and when the capping insulating film is formed, the heel lock is generated since the heel lock has already been removed by the plasma treatment of the previous step in the weak part where the heel lock may occur. Greatly reduced.

Cu, Hillock, Resistivity, Grain, Stress, EM, SM, CMP, Plasma

Description

Method for forming interconnection of semiconductor device {Method for forming interconnections for semiconductor device}

1A to 1G are cross-sectional views illustrating a metal wiring forming method according to a prior art according to a process sequence.

2A is a photograph showing a state in which surface defects due to Cu hillocks are generated on the capping insulating layer when the capping insulating layer is formed thereon after forming the Cu wiring layer according to the related art.

Figure 2b is a photo showing the Cu hillock when the Cu wiring layer is formed in accordance with the prior art to form a capping insulating film thereon to remove the capping insulating film after the Cu hillock is formed.

3A is a photograph showing that black vias are generated by Cu hillock when the Cu wiring layer is formed according to the prior art.

3B is a photo of Cu hillock generated in an inductor pattern when the Cu wiring layer is formed according to the related art.

4A through 4H are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention.

5A and 5B are photographs showing the Cu film surface obtained as a result of plasma treatment after the first CMP of the Cu film formed by the electroplating method in forming the Cu wiring layer according to the metal wiring forming method according to the present invention, respectively. to be.

FIG. 6 is a photograph showing a result that surface defects caused by Cu hillocks are reduced when a Cu wiring layer is formed and a capping insulating layer is formed according to the metal wiring forming method according to the present invention.

7 is a graph showing the degree to which the resistance of the Cu film is reduced by plasma treatment in forming a Cu wiring layer according to the metal wiring forming method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

Reference Numerals 100: semiconductor substrate, 120: conductive layer, 122: etch stop layer, 124: interlayer insulating film, 126: recessed portion, 130: barrier film, 142: seed layer, 144: metal film, 144a: plasma treated metal film, 144b: Metal wiring layer, 146: plasma, 150: capping insulating film.

TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor element. Specifically, It is related with the manufacturing method of the metal wiring of a semiconductor element by a damascene process.

Copper (Cu) is used as a material useful for metal wiring formation in the manufacture of highly integrated semiconductor devices. Cu has a specific resistance of 1.67 μohm · cm, which is smaller than 2.67 μohm · cm of aluminum (Al), so that the signal transmission speed can be increased even if it is formed in a small width. Can improve. In addition, copper is known to be very useful as a wiring forming material because of its low power consumption and inexpensiveness compared with aluminum.

However, Cu is a material that is difficult to etch, and therefore, it is difficult to pattern the Cu film into a desired wiring shape. Therefore, in order to form a Cu wiring, a damascene process is formed by first forming recesses in a desired shape in an interlayer insulating film, and then filling the recesses with Cu and removing unnecessary portions by a method such as chemical mechanical polishing (CMP). Mainly used. In particular, a dual damascene process of forming a via trench and a wiring trench overlapping an upper portion thereof, and then filling the two trenches with a single Cu film formation and then flattening them is widely used.

1A to 1G are cross-sectional views illustrating a method of forming a Cu wiring by a dual damascene process according to the prior art.

Referring to FIG. 1A, an interlayer insulating film 24 having a recess 26 having a dual damascene structure is formed on a semiconductor substrate 10 having a conductive layer 20 formed thereon. An etch stop layer 22 may be used to form the recess 26 in the interlayer insulating layer 24.

Referring to FIG. 1B, a conductive barrier film 30 is formed on an inner wall of the recess 26 and an upper surface of the interlayer insulating film 24.

Referring to FIG. 1C, a Cu seed layer 42 is formed on the conductive barrier layer 30.

Referring to FIG. 1D, the Cu film 44 is formed to a thickness sufficient to fill the recess 26 by the electroplating method using the seed layer 42.

Referring to FIG. 1E, an unnecessary portion of the upper portion of the interlayer insulating film 24 of the Cu film 44 is removed using a CMP process to form a Cu wiring layer 44a filling the recess 26.

Referring to FIG. 1F, the upper surface of the interlayer insulating layer 24 is exposed by removing the conductive barrier layer 30 on the upper surface of the interlayer insulating layer 24 by a CMP process.

Referring to FIG. 1G, a capping insulating layer 50 is formed to cover the top surface of the Cu wiring layer 44a and the top surface of the interlayer insulating film 24.

As described above, in the metal wire forming method according to the related art, as shown in FIG. 1G, the capping insulating film 50 is formed. In this case, the process temperature is generally performed at 350 to 400 ° C. Then, plasma is treated to remove the copper oxide film formed on the CMP surface immediately before the capping insulating film 50 is formed. At this time, the temperature of the wafer is increased by the action of the high process temperature and the radicals formed by the plasma. As a result, a difference in the coefficient of thermal expansion (CTE) between the Cu wiring layer 44a and the semiconductor substrate 10 is caused. In the Cu wiring layer 44a, compressive stress is generated. As a result, in the Cu wiring layer 44a, Cu rises in some grain boundary regions of Cu to form a hillock.

2A is a photograph showing a state in which surface defects are generated due to Cu hillocks on the capping insulating layer when the capping insulating layer is formed thereon after forming the Cu wiring layer according to the related art.

Figure 2b is a photo showing the Cu hillock when the Cu wiring layer is formed in accordance with the prior art to form a capping insulating film thereon to remove the capping insulating film after the Cu hillock is formed.

As described above, when the capping insulation layer is formed on the Cu wiring layer in the state where the hillock is generated, the capping insulation layer may be deposited to have a non-uniform thickness around the hillock. Thus, the capping insulating film portion having a non-uniform thickness may be a portion vulnerable to dry etching. For example, when etching to form a via contact on the Cu wiring layer, etching is preferentially performed at a weak portion of the capping insulating layer, and a cleaning liquid or an etching solution penetrates through the place to oxidize the Cu wiring. Can be. When such a phenomenon occurs, a black via phenomenon as shown in FIG. 3A may be caused by dissolving and oxidizing the Cu wiring layer during the cleaning process. In addition, such a hillock is detected as a defect in the detection of a defect performed at every process step performed after the capping insulating film is formed on the Cu wiring layer on which the hillock has been generated. As a result, in the defect inspection performed at each step, the actual defect detection capability is lowered, and it may be difficult to distinguish a fatal defect.

The occurrence of hillock in the Cu wiring layer as described above is serious as the thickness of the Cu wiring is high or the area of the pattern is large, that is, the volume of Cu as a whole increases. For example, when a capacitor having a metal-insulator-metal (MIM) structure is formed on an upper surface of a relatively large Cu wiring layer, the dielectric film of the MIM capacitor may be broken due to the hillock in the lower Cu wiring layer. When this occurs, the capacitor's electrical performance is severely degraded, such as an increase in leakage current in the capacitor. In addition, in the case of an inductor in which the thickness of the Cu wiring is formed to be about 3 to 5 μm, the volume of the pattern on which the Cu is formed is relatively large, so that a large compressive stress acts on the Cu wiring, and as shown in FIG. Deepens

In the metal wiring forming method according to the prior art, when forming the metal wiring by the damascene process using the electroplating method as shown in Fig. 1d, when the recess 26 is filled with Cu, due to the characteristics of the electroplating process The size of Cu grains immediately after plating of the Cu film is as small as several tens of nm. In order to reduce the specific resistance in the wiring layer made of the Cu film, it is preferable to make the Cu grain size in the Cu film as large as possible. For this reason, after Cu plating, annealing of the resultant product on which the Cu film 44 is formed is performed for Cu grain growth in the Cu film 44. At this time, the annealing process temperature is usually selected within the range of about 100 to 400 ° C. However, the Cu film 44 includes not only a portion filling the recess 26 but also an overplated Cu film thereon, and an excessive stress is induced in the overplated Cu layer during annealing. As a result, a phenomenon in which the Cu film portion filling the recessed portion 26 comes out of the recessed portion 26 may occur. Such a phenomenon occurs frequently in the process of forming a damascene pattern of a particularly small size, and the higher the annealing temperature, the higher the frequency of occurrence.

In order to suppress the occurrence of the above problems, the annealing after the electroplating process is a general trend to proceed at a temperature of 200 ℃ or less. However, under such a low annealing temperature, Cu grains do not grow sufficiently, especially in a pattern of a size as small as a design rule. This phenomenon causes a problem that the specific resistance of Cu is increased.

An object of the present invention is to solve the above problems in the prior art, it is possible to reduce the hillock generation due to the compressive stress of the Cu wiring when the capping insulating film is formed in the Cu wiring layer formed by electroplating, and the fine pattern of the design rule The present invention provides a method for forming a metal wiring of a semiconductor device that can reduce the specific resistance of Cu even when forming.

In order to achieve the above object, in the metal wiring forming method of the semiconductor element according to the first aspect of the present invention, a metal film is formed on a substrate. The metal film is removed from the top by a predetermined thickness using CMP to form a flattened metal film. The planarized metal film is plasma treated to generate hillocks from the metal film. By using CMP, the metal film on which the hillock is formed is partially removed from the upper portion thereof to form a planarized metal wiring layer.

In addition, in order to achieve the above object, an interlayer insulating film is formed on a semiconductor substrate in the metal wiring forming method of the semiconductor element according to the second aspect of the present invention. A recess is formed on the upper surface of the interlayer insulating film. A barrier film is formed on the inner wall of the recess and on the upper surface of the interlayer insulating film. A metal film that completely fills the recess is formed on the barrier film. The metal film is polished to remove a portion from the upper surface of the metal film. The polished metal film is subjected to plasma treatment. The barrier film on the top surface of the interlayer insulating film is polished to expose the top surface of the interlayer insulating film around the plasma metal film. A capping insulating film is formed on the upper surface of the metal film and the upper surface of the interlayer insulating film in the recess.

Moreover, in order to achieve the said objective, in the metal wiring formation method of the semiconductor element which concerns on the 3rd aspect of this invention, a metal film is formed on a board | substrate. The metal film is removed from the top by a predetermined thickness using CMP to form a flattened metal film. The planarized metal film is plasma treated to grow metal grains constituting the metal film. By using CMP, the metal film on which the metal grains are grown is partially removed from the top to form a planarized metal wiring layer.

Preferably, the metal film is made of Cu or Cu alloy.

The metal film may be formed by an electroplating method. After forming the metal film by the electroplating method may further comprise the step of annealing the metal film at a temperature selected within the range of about 100 ~ 200 ℃.

Preferably, the plasma treatment of the metal film is performed in an atmosphere of NH ₃ , N ₂ , H ₂ , He, or a mixture thereof. In addition, the plasma treatment of the metal film may be performed for about 5 to 60 seconds at a temperature of about 300 to 450 ℃. Plasma treating the polished metal film is performed at or above the process temperature of forming the capping insulating film.

The method may further include an additional polishing step of polishing the surface of the metal film again after the plasma treatment of the metal film, and an additional plasma treatment step of plasma treating the exposed surface of the additional polished metal film.

According to the metal wiring forming method according to the present invention, before the capping insulating film is formed on the metal film, the metal film is subjected to plasma treatment so that the hillock is generated by the compressive stress at some grain boundaries of the metal film. At this time, grain growth is further performed in the fine pattern of the design rule, for example, the fine pattern of several micrometers to several tens of micrometers. As such, when the CMP is performed to expose the interlayer insulating film while the hillock or grain growth is performed, roughness of the surface of the metal film due to the hillock or grain growth is removed. Therefore, it is possible to reduce the occurrence of hillock in the formation of the capping insulating film in a subsequent step, and to reduce the resistance in the metal wiring formed of the metal film.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4A through 4H are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention.

Referring to FIG. 4A, an interlayer insulating layer 124 having a recess 126 having a dual damascene structure is formed on a semiconductor substrate 100 having a conductive layer 120 formed thereon. An etch stop layer 122 may be used to form the recess 126 in the interlayer insulating layer 124. The recess 126 may form a hole penetrating the interlayer insulating layer 124 as illustrated in FIG. 4A. Alternatively, although not illustrated, the recess 126 may be formed to have a trench shape having a depth lower than that of the interlayer insulating layer 124.

Referring to FIG. 4B, a conductive barrier layer 130 is formed on an inner wall of the recess 126 and an upper surface of the interlayer insulating layer 124. The conductive barrier layer 130 may be made of, for example, one or two or more materials selected from the group consisting of Ti, Ta, W, and nitrides thereof.

Referring to FIG. 4C, a metal seed layer 142 is formed on the conductive barrier layer 130. For example, a Cu seed layer may be formed as the metal seed layer 142 to form a Cu or Cu alloy interconnection.

Referring to FIG. 4D, an electroplating is performed using the metal seed layer 142 to form a metal film 144 on the metal seed layer 142. The metal film 144 may be formed of, for example, a Cu film or a Cu alloy film. The metal film 144 is formed to a thickness sufficient to fill the recess 126.

In order to grow the metal grains in the metal film 144, the resultant on which the metal film 144 is formed is annealed to a predetermined temperature. Preferably, the annealing is performed at a temperature of about 100 to 200 ° C.

Referring to FIG. 4E, a part of the metal film 144 is removed by polishing by using a first CMP process so that the metal film 144 remains only inside the recess 126.

FIG. 4E illustrates a result of the conductive barrier layer 130 remaining on the interlayer insulating layer 124 on the semiconductor substrate 100 after the first CMP. However, in some cases, the CMP may be performed on the upper surface of the interlayer insulating film 124 around the recess 126 until the metal film 144 remains a predetermined thickness on the conductive barrier film 130.

Referring to FIG. 4F, as shown in FIG. 4E, the metal film 144 remaining in the recess 126 in the state where the barrier film 130 remains on the upper surface of the interlayer insulating film 124 is formed in a predetermined process. The plasma 146 is processed for a predetermined time under temperature. As a result, in the plasma-treated metal film 144a in the recess 126, the hillock generated by the compressive stress is present in some grain boundaries of the metal film 144 by the plasma 146 processing. In particular, in the metal film 144 constituting a fine pattern of about a design rule, for example, about several micrometers to several tens of micrometers, not only hillock but also grain growth may be performed. Alternatively, although not shown, the metal film 144 may be treated with the plasma 146 while the barrier film 130 and a part of the metal film 144 having a predetermined thickness remain on the top surface of the interlayer insulating film 124. The plasma treated metal film 144a may be formed.

Preferably, the plasma 146 treatment of the metal film 144 may be performed for about 5 to 60 seconds at a temperature of about 300 to 450 ° C. under NH ₃ , N ₂ , H ₂ , He, or a mixture thereof. have. If the temperature at the time of the plasma 146 processing is lower than a subsequent film quality, for example, the process temperature at the time of forming the capping insulation film, additional hillock may be generated in the plasma-treated metal film 144a at the time of forming the capping insulation film. It may be. Therefore, it is preferable to set the temperature and plasma processing time during the plasma 146 processing to be equal to or greater than the temperature and time of the plasma processing performed before the subsequent capping insulating film formation.

As described above, the hillock is generated in the metal film 144 by treating the metal film 144 with the plasma 146.

Although not shown, as the grain growth progresses during the plasma 146 processing in FIG. 4F, the surface of the plasma-treated metal film 144a may be changed to a rough surface again. Therefore, in order to obtain a smooth surface on the upper surface of the plasma-treated metal film 144a, the roughened surface of the plasma-treated metal film 144a may be the same as the first CMP process described with reference to FIG. 4E. Process conditions can lead to further CMP processes. In addition, the method may further include an additional plasma treatment step of plasma-processing the exposed surface of the plasma-treated metal film 144a that has undergone the additional CMP process in the same manner as described with reference to FIG. 4F. However, this is not an essential step. That is, the roughened surface of the plasma-treated metal film 144a may be smoothed again in the polishing step of the barrier film 130 described later with reference to FIG. 4G without performing the additional CMP and additional plasma processing steps. have.

Referring to FIG. 4G, a second CMP process is performed to remove the conductive barrier film 130 on the top surface of the interlayer insulating film 124 to expose the top surface of the interlayer insulating film 124.

After the second CMP process, a third CMP process may be further performed to completely remove residues of the conductive barrier layer 130 that may remain on the upper surface of the interlayer insulating layer 124. In this case, a slurry having a high selective removal rate with respect to the conductive barrier film 130 material is used in the second CMP process, and a slurry having a high selective removal rate with respect to the interlayer insulating film 124 material is used during the third CMP process. Can be used. When the third CMP process is performed, the height of the upper surface of the interlayer insulating film 124 is lower than that immediately after the second CMP process. In the recess 126, the metal wiring layer 144b, the final result of the secondary CMP or tertiary CMP process, remains.

Referring to FIG. 4H, a capping insulating layer 150 is formed on the upper surface of the metal wiring layer 144b and the upper surface of the interlayer insulating layer 124. The capping insulating layer 150 may be formed of, for example, silicon nitride, SiCN, SiC, or a combination thereof.

Prior to forming the capping insulating layer 150, the metal oxide layer, which may be formed by contact with the atmosphere, may be formed on the exposed surface of the metal wiring layer 144b with respect to the surface of the metal wiring layer 144b so as to be removed by a reduction reaction. Plasma pretreatment may be performed. Since the heel lock has already been removed by the plasma 146 process as described with reference to FIG. 4F in the weak portion where the heel lock may occur, the metal wiring layer 144b is oxidized. During the plasma pretreatment process for reducing the surface, the possibility of hillock on the surface of the metal wiring layer 144b is greatly reduced. The plasma pretreatment process for reducing the oxidized surface of the metal wiring layer 144b may be performed, for example, in an atmosphere of NH ₃ , N ₂ , H ₂ , He, or a mixture thereof.

5A and 5B illustrate a Cu obtained by forming a Cu wiring layer according to the method for forming a metal wiring according to the present invention, wherein the Cu film formed by the electroplating method is subjected to a first CMP and then plasma-treated at 400 ° C. in an NH ₃ atmosphere. These pictures show the surface of the membrane.

In FIG. 5A, it can be seen that Cu grains grow on the surface of the Cu film due to the effect of plasma treatment, thereby increasing the roughness of the surface of the Cu film. In FIG. 5B, it can be seen that Cu hillock is generated under the influence of plasma treatment.

FIG. 6 is a photograph of the surface of the plasma treatment resultant of FIG. 5B to remove Cu hillock to improve surface roughness, and to form a capping insulating layer thereon. Compared with Figure 2a is a photograph showing that the surface defects caused by Cu hillock is greatly reduced.

7 is a graph showing the degree to which the resistance in the Cu film is reduced by plasma treatment in forming the Cu wiring layer according to the metal wiring forming method according to the present invention.

For evaluation of FIG. 7, annealing was performed at 100 ° C. after plating the Cu film on the wafer, and resistance was measured in a 0.12 μm trench pattern after CMP of the Cu film. In addition, the reduction rate (Delta Rs) is shown in FIG. 7 by comparing the re-measured resistance after performing a plasma treatment at 400 ° C. in an NH ₃ atmosphere using the wafer used for the measurement as it is. As shown in FIG. 7, it can be seen that the resistance was reduced by about 5% by the plasma treatment.

In the metal wiring forming method according to the present invention, in forming a metal wiring by a dual damascene process, a first CMP step for polishing a metal film formed on an interlayer insulating film having recesses on an upper surface thereof, and a conductive barrier under the metal film. Plasma treating the metal film with a secondary CMP step for polishing the film. In the plasma treatment step, the hillock may be generated by an increase in the compressive stress of the metal film, and the grain resistance, which is not sufficiently grown in the metal pattern of the fine pattern as much as the design rule, may be sufficiently grown to lower the specific resistance of the metal film. In addition, by removing the increased surface roughness in the hillock and metal film generated during the plasma treatment process using a secondary CMP process or a separate CMP process for subsequent conductive barrier film polishing to remove the metal wiring layer having a smooth surface It is possible to form. In addition, since the hillocks are already generated and removed after the capping insulation layer is formed, the hillocks can be greatly reduced. Therefore, according to the metal wiring formation method which concerns on this invention, generation | occurrence | production of the hillock in a metal wiring can be reduced, and the reliability of a metal wiring layer can be improved by forming the metal wiring layer which a grain size fully grows and has a smooth surface.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

Claims (37)

Forming a metal film on the substrate, Annealing the metal film; Removing the annealed metal film by a predetermined thickness using CMP to form a planarized metal film; Plasma treating the planarized metal film to generate hillock from the metal film; And forming a planarized metal wiring layer by partially removing the metal film on which the hillock is formed using the CMP. The method of claim 1, And said metal film is made of Cu or Cu alloy. The method of claim 1, And the metal film is formed by an electroplating method. The method of claim 3, Annealing of the said metal film is performed in 100-200 degreeC, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 4, wherein The annealing is performed in an N ₂ or H ₂ atmosphere. The method of claim 1, The plasma treatment of the metal film is performed in an atmosphere of NH ₃ , N ₂ , H ₂ , He, or a mixture thereof. The method of claim 1, Plasma treatment of said metal film is performed at the temperature of 300-450 degreeC, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 1, Plasma treatment of the metal film is performed for 5 to 60 seconds. The method of claim 1, And forming a capping insulating layer on the planarized metal wiring layer. The method of claim 9, Reducing the oxidized surface of the planarized metallization layer before forming the capping insulating film, And plasma treating the oxidized surface to reduce the oxidized surface of the planarized metal wiring layer. The method of claim 9, And the process temperature of the capping insulating film forming step is maintained at or above the temperature of the capping insulating film forming step during plasma treatment of the planarized metal film to produce the hillock. Forming an interlayer insulating film on the semiconductor substrate; Forming recesses on an upper surface of the interlayer insulating film; Forming a barrier film on an inner wall of the recess and an upper surface of the interlayer insulating film; Forming a metal film on the barrier film to completely fill the recesses; Annealing the metal film; Polishing the annealed metal film to remove a portion from an upper surface of the metal film; Plasma processing the polished metal film; Polishing and removing a barrier film on the top surface of the interlayer insulating film so that the top surface of the interlayer insulating film is exposed around the plasma metal film; And forming a capping insulating film on an upper surface of the metal film and an upper surface of the interlayer insulating film in the recessed portion. The method of claim 12, And said metal film is made of Cu or Cu alloy. The method of claim 12, Forming the metal film Forming a metal seed layer on the barrier layer; Forming the metal film on the metal seed layer by an electroplating method. The method of claim 14, Annealing of the said metal film is performed in 100-200 degreeC, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 15, The annealing is performed in an N ₂ or H ₂ atmosphere. The method of claim 12, The plasma treatment of the metal film is performed in an atmosphere of NH ₃ , N ₂ , H ₂ , He, or a mixture thereof. The method of claim 12, Plasma treatment of said metal film is performed at the temperature of 300-450 degreeC, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 12, Plasma treatment of the metal film is performed for 5 to 60 seconds. The method of claim 12, Plasma-processing the polished metal film is performed at a process temperature or higher than the step of forming the capping insulating film. The method of claim 12, Further polishing the surface of the metal film again, after polishing the barrier film after plasma treatment of the metal film; And further performing a plasma treatment on the exposed surface of the additional polished metal film. The method of claim 21, The further plasma treatment is performed in an atmosphere of NH ₃ , N ₂ , H ₂ , He, or a mixture thereof. The method of claim 21, The further plasma treatment is carried out at a temperature of 300 to 450 ° C. The method of claim 12, And plasma treatment of the metal film is performed in a state in which the metal film and the barrier film are simultaneously exposed. The method of claim 12, And the barrier film is made of one or two or more materials selected from the group consisting of Ti, Ta, W, and nitrides thereof. The method of claim 12, A recess formed in the upper surface of the interlayer insulating film has a trench formed in the hole penetrating through the interlayer insulating film or having a depth lower than the thickness of the interlayer insulating film. Forming a metal film on the substrate, Annealing the metal film; Removing the annealed metal film by a predetermined thickness using CMP to form a planarized metal film; Plasma treating the planarized metal film to grow metal grains constituting the metal film; And forming a planarized metal wiring layer by partially removing the metal film having the metal grains grown thereon from the top thereof using CMP. The method of claim 27, And said metal film is made of Cu or Cu alloy. The method of claim 27, And the metal film is formed by an electroplating method. The method of claim 29, Annealing of the said metal film is performed at the temperature chosen in the range of 100-200 degreeC, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 30, The annealing is performed in an N ₂ or H ₂ atmosphere. The method of claim 27, The plasma treatment of the metal film is performed in an atmosphere of NH ₃ , N ₂ , H ₂ , He, or a mixture thereof. The method of claim 27, Plasma treatment of said metal film is performed at the temperature of 300-450 degreeC, The metal wiring formation method of the semiconductor element characterized by the above-mentioned. The method of claim 27, Plasma treatment of the metal film is performed for 5 to 60 seconds. The method of claim 27, And forming a capping insulating layer on the planarized metal wiring layer. 36. The method of claim 35 wherein Reducing the oxidized surface of the planarized metallization layer before forming the capping insulating film, And plasma treating the oxidized surface to reduce the oxidized surface of the planarized metal wiring layer. 36. The method of claim 35 wherein And the process temperature of the capping insulating film forming step is maintained at or above the temperature of the capping insulating film forming step during the plasma treatment of the planarized metal film to grow the metal grains.

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