JP2013504886A - 相互接続構造およびこれを形成する方法(細い相互接続開口のための導電性構造) - Google Patents
相互接続構造およびこれを形成する方法(細い相互接続開口のための導電性構造) Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
Abstract
【解決手段】相互接続構造は、少なくとも1つの開口を含む誘電物質を含む。少なくとも1つの開口内には、任意のバリア拡散層、結晶粒成長促進層、凝集めっきシード層、任意の第2のめっきシード層、および導電性構造が配置される。典型的にはCuである金属含有導電性物質を含む導電性構造は、バンブー微細構造を有し、平均グレイン・サイズが0.05ミクロンよりも大きい。いくつかの実施形態では、導電性構造は、(111)結晶方位を有する導電性結晶粒を含む。
【選択図】図6
Description
Claims (23)
- 少なくとも1つの開口を含む誘電物質と、
前記少なくとも1つの開口内に位置する結晶粒成長促進層と、
前記結晶粒成長促進層の上面の上に位置する凝集めっきシード層と、
前記少なくとも1つの開口内かつ前記凝集めっきシード層の上面の上に位置する導電性構造であって、バンブー微細構造を有し平均グレイン・サイズが0.05ミクロンよりも大きい金属含有導電性物質を含む、導電性構造と、
を含む、相互接続構造。 - 前記導電性構造が、(111)結晶方位を有する導電性結晶粒を含む、請求項1に記載の相互接続構造。
- 前記誘電物質が、SiO2、シルセスキオキサン、Si、C、O、およびHの原子を含むCをドーピングした酸化物、または熱硬化性ポリアリーレン・エーテルの1つである、請求項1または2に記載の相互接続構造。
- 前記少なくとも1つの開口が、ライン開口、バイア開口、ライン開口およびバイア開口の組み合わせ、またはそれらの組み合わせである、前出の請求項のいずれかに記載の相互接続構造。
- 前記結晶粒成長促進層が、Ru、Co、Ir、Rh、Mo、Re、Hf、Nb、またはそれらの合金を含む、前出の請求項のいずれかに記載の相互接続構造。
- 前記結晶粒成長促進層が0.5nmから10nmの厚さを有する、前出の請求項のいずれかに記載の相互接続構造。
- 前記結晶粒成長促進層の下に位置する拡散バリアを更に含み、前記拡散バリアが、Ta、TaN、Ti、TiN、Ru、RuN、W、WN、または他の、導電性物質の拡散を防ぐバリアとして機能することができるいずれかの物質を含む、前出の請求項のいずれかに記載の相互接続構造。
- 前記凝集めっきシード層がCuまたはCu含有合金を含む、前出の請求項のいずれかに記載の相互接続構造。
- 前記凝集めっきシード層と前記導電性構造との間に別のめっきシード層が位置している、前出の請求項のいずれかに記載の相互接続構造。
- 前記導電性構造の前記金属含有導電性物質が、導電性金属、少なくとも1つの導電性金属を含む合金、または導電性金属シリサイドを含む、前出の請求項のいずれかに記載の相互接続構造。
- 前記金属含有導電性物質が、Cu、Al、W、およびAlCuから成る群から選択された導電性金属である、請求項10に記載の相互接続構造。
- 前記導電性構造が、開放バイア底部、固定バイア底部構造、または閉鎖バイア底部に存在する、前出の請求項のいずれかに記載の相互接続構造。
- 少なくとも1つの開口を含む誘電物質と、
前記少なくとも1つの開口内に位置する拡散バリアと、
前記拡散バリア上に位置する結晶粒成長促進層と、
前記結晶粒成長促進層上に位置する凝集めっきシード層と、
前記凝集めっきシード層上に位置する別のめっきシード層と、
前記少なくとも1つの開口内に位置する銅含有導電性構造であって、バンブー微細構造を有し、平均グレイン・サイズが0.05ミクロンよりも大きく、(111)結晶方位を有する銅結晶粒を有する、銅含有導電性構造と、
を含む、相互接続構造。 - 誘電物質に少なくとも1つの開口を形成するステップと、
前記少なくとも1つの開口内に結晶粒成長促進層を形成するステップと、
前記少なくとも1つの開口内に凝集めっきシード層を形成するステップと、
前記少なくとも1つの開口内に前記凝集めっきシード層の上に導電性構造を形成するステップであって、前記導電性構造が、バンブー微細構造を有し平均グレイン・サイズが0.05ミクロンよりも大きい金属含有導電性物質を含む、ステップと、
を含む、相互接続構造を形成する方法。 - 前記結晶粒成長促進層を形成する前に前記少なくとも1つの開口内に拡散バリアを形成するステップを更に含む、請求項14に記載の方法。
- 前記結晶粒成長促進層を形成する前記ステップが400℃以下の堆積温度で行われる、請求項14または15に記載の方法。
- 前記凝集めっきシード層を形成する前記ステップが、めっきシード層を堆積することおよび前記めっきシード層をアニールすることを含む、請求項14から16のいずれかに記載の方法。
- 前記アニールが、還元性雰囲気または真空下で200℃から400℃までの温度で実行される、請求項14から17のいずれかに記載の方法。
- 前記凝集めっきシード層の上に別のめっきシード層を形成するステップを更に含む、請求項14から18のいずれかに記載の方法。
- 前記導電性構造を形成する前記ステップが、前記少なくとも1つの開口内に前記金属含有導電性物質を堆積することおよび前記金属含有導電性物質をアニーリングすることを含む、請求項14から19のいずれかに記載の方法。
- 前記アニーリングが80℃から300℃までの温度で実行される、請求項20に記載の方法。
- 前記導電性構造が(111)結晶方位を有する結晶粒を含む、請求項14から21のいずれかに記載の方法。
- 誘電物質に少なくとも1つの開口を形成するステップと、
前記少なくとも1つの開口内に拡散バリアを形成するステップと、
前記拡散バリアの上面上に結晶粒成長促進層を形成するステップと、
前記少なくとも1つの開口内に凝集めっきシード層を形成するステップと、
前記凝集めっきシード層の上に別のめっきシード層を形成するステップと、
前記少なくとも1つの開口内に銅含有導電性構造を形成するステップであって、前記銅含有導電性構造が、バンブー微細構造を有し、平均グレイン・サイズが0.05ミクロンよりも大きく、(111)結晶方位を有する銅結晶粒を有する、ステップと、
を含む、相互接続構造を形成する方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/560,878 | 2009-09-16 | ||
US12/560,878 US7956463B2 (en) | 2009-09-16 | 2009-09-16 | Large grain size conductive structure for narrow interconnect openings |
PCT/EP2010/062407 WO2011032812A1 (en) | 2009-09-16 | 2010-08-25 | Conductive structure for narrow interconnect openings |
Publications (3)
Publication Number | Publication Date |
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JP2013504886A true JP2013504886A (ja) | 2013-02-07 |
JP2013504886A5 JP2013504886A5 (ja) | 2013-10-03 |
JP5444471B2 JP5444471B2 (ja) | 2014-03-19 |
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JP (1) | JP5444471B2 (ja) |
CN (1) | CN102498560A (ja) |
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GB201200519D0 (en) | 2012-02-29 |
US20110062587A1 (en) | 2011-03-17 |
TWI497673B (zh) | 2015-08-21 |
WO2011032812A1 (en) | 2011-03-24 |
DE112010003659T5 (de) | 2012-10-31 |
TW201126683A (en) | 2011-08-01 |
GB2485689A (en) | 2012-05-23 |
JP5444471B2 (ja) | 2014-03-19 |
GB2485689B (en) | 2013-06-12 |
CN102498560A (zh) | 2012-06-13 |
US7956463B2 (en) | 2011-06-07 |
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