JP5385610B2 - 相互接続構造体の形成方法 - Google Patents
相互接続構造体の形成方法 Download PDFInfo
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- JP5385610B2 JP5385610B2 JP2008534600A JP2008534600A JP5385610B2 JP 5385610 B2 JP5385610 B2 JP 5385610B2 JP 2008534600 A JP2008534600 A JP 2008534600A JP 2008534600 A JP2008534600 A JP 2008534600A JP 5385610 B2 JP5385610 B2 JP 5385610B2
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- Prior art keywords
- plating seed
- region
- oxygen
- forming
- nitrogen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
12:下部相互接続レベル
14:誘電体キャップ層
16:上部相互接続レベル
18:第1の誘電体材料
20:導電性構造体
22:バリア層
24:第2の誘電体材料
26、28:開口部
30:底部メッキシード領域
32:酸素/窒素遷移領域
34:上部メッキシード領域
36:メッキシード層
38:相互接続導電性材料
Claims (5)
- 誘電体材料の中に少なくとも1つの開口部を形成するステップと、
前記少なくとも1つの開口部内の前記誘電体材料の少なくとも露出壁部分に、Ru、RuとTaN、RuとTiSi、Ir、IrとTaN、およびIrとTiSiを含むグループから選択された1つからなる第1のメッキシード領域を形成するステップと、
前記第1のメッキシード領域上に酸素及び窒素遷移領域を形成するステップであって、前記第1のメッキシード領域を酸素及び窒素を含む環境に曝すことにより、前記第1のメッキシード領域よりも5倍以上の酸素及び窒素の含有量を有する前記酸素及び窒素遷移領域を形成することを含む、ステップと、
前記酸素及び窒素遷移領域上に、Ru、RuとTaN、RuとTiSi、Ir、IrとTaN、およびIrとTiSiを含むグループから選択された1つからなる第2のメッキシード領域を形成するステップであって、前記第1のメッキシード領域、前記酸素及び窒素遷移領域、及び前記第2のメッキシード領域が向上したバリア性を有する単一のメッキシード層を画定する、ステップと、
前記少なくとも1つの開口部内において前記単一メッキシード層上にCuまたはCuAlからなる相互接続導電性材料を形成するステップと、
を含む相互接続構造体の形成方法。 - 前記第1及び第2のメッキシード領域はRuからなり、前記酸素及び窒素遷移領域はRuONからなる、請求項1に記載の方法。
- 前記酸素及び窒素遷移領域を形成する前記ステップは、O 2 とN 2 、NO、またはN 2 Oを含むガスまたはプラズマ中で前記第1のメッキシード領域を処理するステップを含む、請求項1または2に記載の方法。
- 前記酸素及び窒素遷移領域は、0.5〜5nmの厚さを有する、請求項1〜3のいずれか1項に記載の方法。
- 前記相互接続導電性材料を形成する前記ステップは、前記単一メッキシード層を前記開口の底部から除去するステップを含む、請求項1〜4のいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/245,540 | 2005-10-07 | ||
US11/245,540 US7215006B2 (en) | 2005-10-07 | 2005-10-07 | Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement |
PCT/US2006/038475 WO2007044305A2 (en) | 2005-10-07 | 2006-10-03 | Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009512191A JP2009512191A (ja) | 2009-03-19 |
JP2009512191A5 JP2009512191A5 (ja) | 2009-04-30 |
JP5385610B2 true JP5385610B2 (ja) | 2014-01-08 |
Family
ID=37910407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008534600A Expired - Fee Related JP5385610B2 (ja) | 2005-10-07 | 2006-10-03 | 相互接続構造体の形成方法 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7215006B2 (ja) |
EP (1) | EP1941545A4 (ja) |
JP (1) | JP5385610B2 (ja) |
KR (1) | KR101072152B1 (ja) |
CN (1) | CN100576530C (ja) |
TW (1) | TW200717714A (ja) |
WO (1) | WO2007044305A2 (ja) |
Families Citing this family (19)
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JP2008091835A (ja) * | 2006-10-05 | 2008-04-17 | Toshiba Corp | 半導体装置およびその製造方法 |
JP5305599B2 (ja) * | 2007-02-19 | 2013-10-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7829454B2 (en) * | 2007-09-11 | 2010-11-09 | Tokyo Electron Limited | Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device |
US7867895B2 (en) * | 2007-09-20 | 2011-01-11 | International Business Machines Corporation | Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric |
US7772110B2 (en) * | 2007-09-28 | 2010-08-10 | Tokyo Electron Limited | Electrical contacts for integrated circuits and methods of forming using gas cluster ion beam processing |
US20090089515A1 (en) * | 2007-10-02 | 2009-04-02 | Qualcomm Incorporated | Memory Controller for Performing Memory Block Initialization and Copy |
US20090179328A1 (en) | 2008-01-14 | 2009-07-16 | International Business Machines Corporation | Barrier sequence for use in copper interconnect metallization |
US20090194875A1 (en) * | 2008-01-31 | 2009-08-06 | International Business Machines Corporation | HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS |
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CN101911264B (zh) * | 2008-03-19 | 2012-07-04 | 日矿金属株式会社 | 在基材上形成有阻挡层兼种子层的电子构件 |
US7928570B2 (en) * | 2009-04-16 | 2011-04-19 | International Business Machines Corporation | Interconnect structure |
US8242600B2 (en) | 2009-05-19 | 2012-08-14 | International Business Machines Corporation | Redundant metal barrier structure for interconnect applications |
US8252680B2 (en) * | 2010-09-24 | 2012-08-28 | Intel Corporation | Methods and architectures for bottomless interconnect vias |
DE102010063294B4 (de) * | 2010-12-16 | 2019-07-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung von Metallisierungssystemen von Halbleiterbauelementen, die eine Kupfer/Silizium-Verbindung als ein Barrierenmaterial aufweisen |
US8461683B2 (en) * | 2011-04-01 | 2013-06-11 | Intel Corporation | Self-forming, self-aligned barriers for back-end interconnects and methods of making same |
JP5618941B2 (ja) * | 2011-08-10 | 2014-11-05 | 株式会社東芝 | 半導体装置 |
CN102931168A (zh) * | 2012-11-14 | 2013-02-13 | 日月光半导体(上海)股份有限公司 | 封装基板及其制造方法 |
JP6365106B2 (ja) * | 2014-08-18 | 2018-08-01 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
US11430692B2 (en) * | 2020-07-29 | 2022-08-30 | Taiwan Semiconductor Manufacturing Company Limited | Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same |
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-
2005
- 2005-10-07 US US11/245,540 patent/US7215006B2/en not_active Expired - Fee Related
-
2006
- 2006-10-02 TW TW095136593A patent/TW200717714A/zh unknown
- 2006-10-03 EP EP06825349A patent/EP1941545A4/en not_active Withdrawn
- 2006-10-03 KR KR1020087008192A patent/KR101072152B1/ko not_active IP Right Cessation
- 2006-10-03 WO PCT/US2006/038475 patent/WO2007044305A2/en active Search and Examination
- 2006-10-03 CN CN200680036654A patent/CN100576530C/zh not_active Expired - Fee Related
- 2006-10-03 JP JP2008534600A patent/JP5385610B2/ja not_active Expired - Fee Related
-
2007
- 2007-03-06 US US11/682,581 patent/US7498254B2/en not_active Expired - Fee Related
-
2008
- 2008-07-22 US US12/177,309 patent/US8003524B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7498254B2 (en) | 2009-03-03 |
WO2007044305A3 (en) | 2007-12-13 |
EP1941545A4 (en) | 2011-03-30 |
US20090155996A1 (en) | 2009-06-18 |
US8003524B2 (en) | 2011-08-23 |
US7215006B2 (en) | 2007-05-08 |
KR20080059559A (ko) | 2008-06-30 |
EP1941545A2 (en) | 2008-07-09 |
CN101278396A (zh) | 2008-10-01 |
KR101072152B1 (ko) | 2011-10-10 |
CN100576530C (zh) | 2009-12-30 |
US20070148826A1 (en) | 2007-06-28 |
US20070080429A1 (en) | 2007-04-12 |
WO2007044305A2 (en) | 2007-04-19 |
JP2009512191A (ja) | 2009-03-19 |
TW200717714A (en) | 2007-05-01 |
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