TW494443B - Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on a workpiece - Google Patents

Abstract

A semiconductor manufacturing tool configuration and corresponding process for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a semiconductor workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed.

Description

494443 A7 B7 V. Description of the Invention (Background of the Invention: An integrated circuit is an interconnected complex of a semiconductor material and a device formed in a dielectric material overlying the semiconductor material. Devices that may be formed in a semiconductor material include MOS transistors, bipolar transistors, diodes, and diffusion resistors. Devices that may be formed in dielectric materials include thin film resistors and capacitors. Typically, a single 8-inch-diameter silicon wafer is composed of more than 100 integrated circuit chips (1C chip). The devices used in each die are interconnected by conductor paths formed in the dielectric. Typically, two or more layers of conductor paths (continuous layers) (Separated by a dielectric layer) is used as an interconnect. In current implementations, aluminum alloys and silicon oxides are typically used as conductors and dielectrics, respectively. Electrical signals between devices on a single crystal The propagation delay limits the performance of the integrated circuit. More specifically, these delays limit the speed at which the integrated circuit can process these electrical signals. Large propagation delay Reduces the speed at which integrated circuits can process electrical signals, and smaller propagation delays increase this speed. Therefore, manufacturers of integrated circuits are seeking ways to reduce propagation delays (please read the precautions on the back before filling out this page)- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For each interconnected path, the signal propagation delay is characterized by the time delay r. See "Interconnect Technology" by EH Stevens, QMC, July 993. Time delay An approximate expression for τ (which is related to the transmission of signals between transistors on integrated circuits) is as follows: r = RC [1+ (Vsat / RIsat)] In this equation, R And C series are the equivalent resistance scales of the interconnecting path, applicable to the Chinese National Standard (CNS) A4 specification (210X29 ^^ 7 494443 A7 B7) 5. Description of the invention (7 /) (Please read the precautions on the back before filling in this Page) and equivalent capacitance, while ISAT and VSAT are the saturation (maximum) current and the onset of the current-onset drain-to-source potential of the transistor that applies a signal to the interconnect path. The path resistance is directly proportional. The resistance coefficient of the conductor material. The number P. The path capacitance is proportional to the dielectric coefficient Ke of the dielectric material. If the 小 of r is small, the interconnect wiring must carry a sufficient current density to make the ratio of Vsat / RIsat smaller. Then, in the manufacture of high-performance integrated circuits, low-P conductors capable of carrying high current density and low-Ke dielectrics should be used. In order to meet the aforementioned standards, copper interconnects in low-Ke dielectrics are suitable to replace oxidation Aluminum alloy wires in silicon dielectrics are used as the best interconnection structure. See "Copper Goes Mainstream: Follow Low K", International Semiconductor, November 1997, pages 67 to 70. The resistivity of copper films is 1.7 To 2.0 // Ώcm, and Ming alloy film is in the range of 3.0 to 3.5 // cm. Regardless of the beneficial properties of copper, in large-scale manufacturing processes, it must be mentioned that for copper interconnects, multiple issues become significant. One such problem is the proliferation of copper printed by employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs. Under the influence of an electric field, and only at an appropriately elevated temperature, copper moves rapidly through silicon oxide. It is generally believed that copper also moves rapidly through low Ke dielectrics. This copper diffusion prevents devices from being formed in silicon. Another problem is that when copper is immersed in an aqueous solution or exposed to an oxygen-containing gas, it tends to oxidize quickly. The oxidized surface of copper becomes non-conductive, and thus limits the current carrying capacity of a given conductor path when compared to unoxidized copper paths of the same size. Another problem with using copper in integrated circuits is that it is difficult to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) to paper standards with dielectrics. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 494443 A7 B7 V. Invention Note The use of copper in multilayer integrated circuit structures of (,) quality materials. With the traditional method of copper deposition, copper is only weakly adhered to the dielectric material. Finally, copper does not form volatile halide compounds, so when copper is used as a fine line pattern, direct plasma etching of copper cannot be used. As such, the copper system is difficult to use in increasingly smaller geometries required for advanced integrated circuit devices. The semiconductor industry has referred to some of the aforementioned issues and has adopted a general standard interconnect architecture for copper interconnects. To this end, the industry has found that fine line patterns of copper can be etched in trenches and channels in dielectrics, plugged trenches and channels with copper, and removed from above the top surface of the dielectric by chemical mechanical polishing (CMP). Achieved by removing copper. An interconnect architecture called dual damascene can be used to implement this architecture to form copper wires in the dielectric. The first figure shows the processing steps typically required to implement a dual ripple architecture. The inventors of the present invention have found that for semiconductor manufacturers, the dual corrugated architecture is often difficult to implement in large-scale manufacturing processes. It is a low Ke material that is difficult to deposit a thin silicon oxide etch stop layer without damaging the underlying layer. The technique of plasma etching dielectric materials is well established, but it is difficult to etch sub-micron features in low Ke dielectrics while maintaining selectivity to silicon oxide. There are at least two procedures that are particularly troublesome in the construction of the double ripple structure. First, it is difficult to deposit thin and uniform barriers and seed layers into high aspect ratio (depth / diameter) channels and high aspect ratio (depth / width) trenches. Until the respective trenches and / or channels are completely congested or stacked with the required material, the upper part of such trenches and channels tends to be stripped (size ^ medium-(Please read the precautions on the back before filling this page )

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 A7 B7 V. Invention Description (4) pinch-off). Moreover, CMP and related cleaning procedures are particularly complex and difficult to implement. In addition to its difficulty and complexity, the dual corrugated architecture has limitations in interconnect performance. The etch stop layer, which typically includes silicon nitride, has a high dielectric constant; therefore, unless the uranium etch stop layer is very thin compared to the line thickness, the capacitance between the metal lines of the same interconnect layer is passed through. The coupling of the etch stop is suppressed. It is known that the conductivity of barrier materials is negligible compared to that of copper; therefore, the conductivity of thin interconnects is significantly reduced because of the barrier layer that must be interposed between copper and the dielectric. . A processing tool architecture suitable for implementing the double wave processing steps shown in the first figure is shown in the second figure. As shown in the second figure, the dual ripple architecture can be implemented using ten tool sets. The formation of each interconnecting layer generally requires two photolithographic processes, two precision etchings, four dielectric depositions, barrier and seed layer deposition, copper deposition, CMP, and post-CMP erasure. Both small channels and small trenches must be scribed by uranium; therefore, an etch tool needs to define channel features in the silicon nitride film, and a second engraving tool needs to define channel openings and trench features in low-Ke dielectrics. With the conventional processing tool of the second figure, the formation of each metallization layer requires at least 13 workpiece movements in the tool set. The considerable number of wafer movements used to form the double corrugated interconnect metallization structure reduces the reliability and productivity of the manufacturing process. As the number of wafer movements increases, the potential for mishandling of one or more wafers also increases. Furthermore, the implementation of manufacturing equipment for the application of double corrugated interconnect metallization structures requires large sums of money to purchase the required tool set. At least one feature of the present invention ----------- 6- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

494443 Α7 Β7 V. Invention description (3) is aimed at such reliability and main equipment expenditure issues. The inventor of the foregoing problem has also recognized that the copper metallization layer needs an effective barrier material to prevent copper diffusion, and an effective protective layer covers the copper metallization layer to prevent copper oxidation. Existing procedures for manufacturing these metallization layers are not effective ' and their use in large-scale manufacturing operations is not economical. Brief summary of the present invention: A semiconductor manufacturing tool structure is disclosed in which one or more metallization layers are applied to a substantially flat dielectric surface of a semiconductor workpiece with a minimum number of workpiece transfer operations between tool sets. The tool structure includes a thin film deposition tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set. The thin film deposition tool set is used to deposit a conductive barrier layer outside the flat dielectric surface of a semiconductor workpiece and a conductive seed layer to the outside of the barrier layer. The pattern processing tool set is used to provide an interconnection pattern to the seed layer 'and provide a column pattern to the interconnection metallization formed using the interconnection pattern. The wet processing tool set is used to perform at least the following wet processing operations: use of an electrodeposition process to apply copper metallization to interconnect wiring patterns and column patterns formed by the pattern processing tool set; remove material applied by the pattern processing tool set To form interconnection patterns and pillar patterns; and removing portions of the seed layer and the barrier layer that are not covered by the interconnection wiring metallization. The dielectric processing tool set is used to deposit a dielectric layer over the interconnection metallization and pillar metallization, and is used to etch the deposited dielectric layer to expose the connection area above the pillar metallization. A single metallization layer may use multiple workpiece movements between tool sets. Η This paper size applies to Chinese National Standard (CNS) A4 specifications (210 × 297 mm) (Please read the precautions on the back before filling this page), 1T Ministry of Economic Affairs Printed by the Intellectual Property Bureau Employee Cooperatives 494443 A7 B7 5. Invention Description u) Formation. Preferably, the workpiece movement between the used tool sets is not more than ten times, and more preferably, the workpiece movement between the used tool sets is not more than five times. In some cases' it may be necessary to use a hard mask to pattern the interconnect metallization. To this end, another alternative tool structure includes a thin film deposition tool set, a hard mask forming tool set, a hard mask etching tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set. The thin film deposition tool set is used to deposit a conductive barrier layer on the outside of the flat dielectric surface of the workpiece, and a conductive seed layer on the outside of the barrier layer. The hard mask formation tool set is used to form a hard mask dielectric layer outside the seed layer and to form another hard mask dielectric layer outside the hard mask dielectric layer according to one of the disclosed procedures. . According to the first disclosed procedure, the pattern processing tool set is used to provide an interconnection pattern overlying the dielectric layer of the hard mask, and is used to provide a column pattern over the interconnection metallization formed using the interconnection pattern. According to the second disclosed procedure, the pattern processing tool set is used to provide a column pattern over a subsequent hard mask dielectric layer. According to the third disclosed procedure, the hard mask engraving tool set is used to etch the exposed area of the hard mask dielectric layer after the interconnect wiring pattern is formed thereon, and after the pillar pattern is formed thereon, it is etched later. Exposed portion of the hard mask dielectric layer. The wet processing tool set performs at least the following wet processing operations: 1) using a galvanic deposition process to deposit copper metallization into interconnect wiring patterns and column patterns formed by the pattern processing tool set, and 2) removing the pattern processing tool set Material applied to form interconnect patterns and pillar patterns '3) Remove hard mask dielectric layer and, if necessary, remove subsequent hard mask dielectric layer' and 4) Move to paper size Applicable to China National Standard (CNS) A4 (2l0x297mm) (Please read the notes on the back before filling out this page) # Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 494443 Α7 Β7 V. Invention Description (π ) Except for the seed and barrier layers that are not covered by the interconnect wiring metallization. The dielectric processing tool set is used to deposit a dielectric overlying interconnect metallization and pillar metallization, and a dielectric layer for uranium etching to expose the upper connection area of the pillar metallization layer. Depending on the particular embodiment of the toolkit architecture, an inspection toolkit may also be included. For example, semiconductor workpieces are transferred to inspection devices at various intermediate stages of the metallization process to ensure the correct registration of the pattern layer and the resulting metallization structure. In some cases, a single metallization layer may be formed using no more than ten workpiece movements between tool sets. When using a hard mask tool structure, it is better to use no more than fourteen workpiece movements between the tool groups when using the inspection tool group. More preferably, it uses no more than seven workpiece movements between tool sets. 0 describes a procedure for providing one or more protected copper components on the surface of a workpiece. According to this procedure, a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for a subsequent plating process, a separate seed layer is applied to the surface of the barrier layer. The next copper component or components are then electroplated to selected parts of the seed or barrier layer (if applicable). If a seed layer is used, it is then substantially removed. At least a portion of the surface of the barrier layer is left unplatable while leaving copper components suitable for electroplating. The latter protective layer is then plated on the surface of one or more copper elements. The tool architecture for implementing the aforementioned procedures is also described. The disclosed tool architecture can be used to minimize and minimize the number of wafer movements between tool sets required to form a complete metallization layer structure. This paper size applies to Chinese National Standard (CNS) Α4 size (210X 297 mm) (Please read the precautions on the back before filling this page) Order

Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (1) Simple illustration of the multi-faceted view of the drawings: One way program flow chart. The first figure shows the tool set structure and the corresponding workpiece movement that are not used to implement the procedure shown in the first figure. The third figure shows one way of constructing a tool set for use in the tool set architecture of the present invention. The fourth diagram is a flow chart showing one way to implement an interconnected metallization structure using a minimum number of workpiece movements between the tool sets of the third diagram. The fifth A to K diagrams show the development of the metallization layer at various stages of the interconnection metallization structure formed by the procedure of the fourth diagram. The sixth diagram shows the structure of the tool set and the corresponding workpiece movements for implementing the procedures shown in the fourth diagram. The seventh diagram shows the tool set architecture and the corresponding workpiece movement for implementing the procedure shown in the fourth diagram, and the inspection tool set is used to inspect the semiconductor workpiece in the middle stage of the metallization process. The eighth figure shows one way of constructing a tool set structure for implementing another processing architecture of the present invention, in which a hard mask is used as an interconnection pattern. The ninth and tenth drawings are specific embodiments of the tool set for the tool set structure of the eighth display. The eleventh figure is a flow chart showing one way of forming an interconnected metallized structure using the minimum number of workpiece movements between the tool sets shown in the eighth figure. Standards are applicable to China National Standard (CNS) A4 specifications (210 X 2 mm) (Please read the precautions on the back before filling this page)

494443 A7 __ B7 V. Description of the Invention (q) The twelfth to fourteenth diagrams show the selected stages of the development of the metallization layer of the interconnected metallization structure formed by the procedure of the eleventh diagram. (Please read the precautions on the back before filling out this page.) Figure 15 shows the flow chart of another way to implement the interconnection metallization structure using the minimum number of workpiece movements and hard mask patterns The figure shows the structure of the tool set and the corresponding workpiece movement for implementing the procedure shown in figure 15. Figures 17 and 18 show selected stages of the development of the metallization layer of the interconnected metallization structure formed using the procedure of Figure 15. Figures 19 and 20 show the tool set structure and corresponding workpiece movements for implementing the procedures shown in Figures 11 and 15 respectively. The inspection tool set is used to check the middle stage of the metallization process. Of artifacts. Detailed description of the invention: A basic understanding of the specific vocabulary used herein will help the reader understand the subject matter disclosed. For this reason, the basic definitions used for the specific vocabulary of this disclosure are set forth below. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The first metallization layer is defined as the composite layer of workpieces outside a certain board. This composite layer includes one or more interconnecting wires and one or more interconnecting posts. These interconnecting wires and interconnecting posts are substantially covered by a dielectric layer, so that the dielectric layer will be designed not to be interconnected. The selected interconnections and interconnection posts are isolated. A substrate system is defined as a base layer of material on which one or more metallization layers are deposited. For example, 'This substrate can be a semiconductor wafer, ceramic block, etc. This paper is scaled to the Chinese National Standard (CNS) A4 (210X297 mm). It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 A7 ____ —_B7__ V. Invention Explanation (ί〇1 is defined as an object that includes at least a substrate, and it may include materials or other layers (such as one or more metallized layers) from which components are fabricated. The invention employs a novel method to deposit The copper metallization is applied to the workpiece 'like a semiconductor object. This method allows the copper metallization layer to be easily manufactured using a minimum number of processing tool sets and a minimum number of workpiece movements between the tool sets. Used to form the resulting copper interconnects The manufacturing process steps of the layers avoid many of the inherently problematic processing steps associated with corrugated interconnect structures. For example, seed layers, copper metallization layers, and barrier layers no longer require the use of non-conformal ) Vapor deposition and deposition into trenches and channels with high aspect ratios. On the contrary, the barrier layer and metal seed layer The coating is applied to the workpiece in a blanket deposition process, which is spread over the flattened surface of the workpiece. Subsequent deposition of copper metallizations used to form at least these lines is done using an electrodeposition process. Copper The deposition starts at the bottom of the opening in the patterned hard mask layer to ensure that the resulting line is fully formed and eliminates problems related to the 3-dimensional pinch-off of trenches and channels used in the corrugation process. Similarly, the copper metallization used to form the pillars is achieved by using an electrodeposition process, where copper-based deposition begins at the bottom of the opening in the patterned hard mask layer or the patterned photoresist layer. Furthermore, chemical mechanical polishing treatments can be eliminated to facilitate electrochemical planarization and / or etching treatments. The fabrication of the disclosed interconnection layer structure is achieved with a minimum number of workpiece processing tool sets and a minimum number of workpiece movements between tool sets. . In its own case, in the design of manufacturing facilities used to produce these interconnected structures -__; _12 _ This paper standard applies to China Standard (CNS) A4 (210X 297 mm) (Please read the precautions on the back before filling out this page), 11 494443 A7 __ B7 V. Description of the invention () The cost of major equipment can be minimized. Moreover, borrowing The danger of workpiece damage can be substantially reduced by reducing the number of workpiece movements between tool sets. The basic tool set used to implement the tool architecture according to an embodiment of the present invention is shown in the third figure. As shown, the tool set It includes a thin film deposition tool set 20, a pattern processing tool set 25, a wet processing tool set 30, and a dielectric processing tool set 35. In the embodiment disclosed in the third figure, the thin film deposition tool set 20 is preferably a vacuum. Deposition Tool Set. As will become clearer from the following discussion of processing operations performed on semiconductor workpieces, the thin film deposition tool set 20 deposits one or more thin films on a substantially flat surface of the semiconductor work piece. This type of thin film deposition preferably deposits a thin film in a micro-recessed feature used in the corrugation process. On its own, a low-cost vacuum deposition technique such as physical vapor deposition (PVD) can be used. Chemical vapor deposition (CVD) processes can also be used. A particular embodiment of the thin film deposition tool set 20 shown in the third figure includes an input station 40 provided to receive a semiconductor workpiece. The input station 40 is configured to receive semiconductor workpieces in a multi-workpiece cassette or a multi-workpiece or a single-workpiece pouch. The semiconductor workpiece is transferred from the input station 40 to a plurality of processing stations. More preferably, the semiconductor workpiece is first transferred to a dressing station 45, where the surface of a substantially flat dielectric layer disposed outside the semiconductor workpiece substrate is treated to enhance the adhesion of successive thin film layers. Such adhesion enhancement of the dielectric layer can be achieved using any one or more known dry chemical treatments. Depending on the characteristics of the dielectric layer and subsequent thin film layers, adhesion enhancement may not be required. In this case, the finishing station 45 does not need to be included in the thin film deposition tool set. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 1T, 494443 A7 B7 V. Description of the invention (p) 20 ° Each semiconductor workpiece is then provided to the connection film application station 50, where an optional connection layer is applied To the outside of the dielectric layer (preferably applied directly to it). Suitable materials for the tie layer include aluminum, titanium, and chromium. Preferably, such materials for the tie layer are deposited using a vapor deposition technique such as PVD or CVD. Depending on the characteristics of the adjacent thin film layers, a tie layer may not be required, and if so, the tie film application station 50 need not be included in the thin film deposition tool set 20. The barrier layer application station 55 is provided in the thin film deposition tool set 20 to transfer the barrier layer material to the outside of the dielectric material of the semiconductor workpiece. Depending on the characteristics of other materials interacting in the interconnect structure, the barrier layer may include tantalum, giant nitride, titanium nitride, titanium oxynitride, titanium tungsten alloy, or tungsten nitride. Especially when the interconnection layer contacts the terminals of the semiconductor device, it is preferable to use a composite barrier including two layers, as disclosed in Stevens U.S. Patent No. 4,977,440 and U.S. Patent No. 5,070,036. The barrier layer can be formed by a vacuum deposition process such as PVD and CVD. In order to increase the conductivity of the barrier layer and to provide good adhesion of the subsequent layers, the thin film deposition tool set 20 preferably includes a seed layer application station 60. The seed layer application station 60 preferably deposits the seed layer using a PVD or CVD process. The seed layer is preferably copper, but the seed layer may also be composed of a metal such as nickel, iridium, lead, palladium, chromium, vanadium, or other conductive materials such as iridium oxide. After the seed layer has been applied, the semiconductor workpiece is transferred to an output station 62 for subsequent transfer to another semiconductor processing tool set. The pattern processing tool group 25 includes a plurality of processing stations, which are used to provide the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page), 11 Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 494443 A7 V. Description of the invention (...) The interconnection wiring pattern is overlaid on the seed layer applied by the thin film deposition processing tool set 20. The pattern processing control group 25 is also used to provide a column pattern over the interconnect metallization formed using the interconnect line pattern. As will be described in further detail below, the interconnect pattern defines the area provided with the main conductor path for horizontal electrical interconnection in the plane of the semiconductor workpiece, while the bar pattern defines the adjacent plane provided for the semiconductor workpiece The area of the main conductor path between which there is a vertical electrical interconnection. In the embodiment of the tool set shown in the third figure, the pattern processing tool set 25 is a photolithography tool set. Depending on the circumstances, the pattern processing tool set 25 includes an input station 65 which houses a semiconductor workpiece in a multi-tool cassette, or a single-workpiece or multi-workpiece pouch. Semiconductor workpieces undergo standard photoetching trimming, coating, and baking processes at processing stations 70, 75, and 80, respectively. After the photoresist is baked on the semiconductor workpiece at the station 80, the workpiece is transferred to the input station 85 of the photoresist exposure apparatus 90. For example, the photoresist exposure device 90 may be a stepping and repeating device that exposes the photoresist to ultraviolet light in a manner that selectively affects the photoresist layer so that a portion of the photoresist layer can be subsequently Remove to form interconnects or pillar patterns. After processing in the photoresist exposure device 90, the semiconductor workpiece is provided to the output station 95 of the device 90 for transfer to other processing stations, which selectively removes the photoresist layer to form in the layer and the photoresist The patterns in the exposure device 90 are uniformly exposed. These processing stations include a photoresist developing station 100 and a plasma removal ("slag removal") station 105. After selective removal of the photoresist layer and plasma eradication, the semiconductor workpiece can be transferred to the output station 110, or optionally transferred to the UV curing station 107 and transferred from it to the output station 11 for scale application. China National Standard (CNS) A4 Specification (210X29 ^ cent) (Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 1T 494443 A7 B7 V. Invention Description (a) Provided to one or more other tool groups. The wet processing tool set 30 performs a wide range of processing to form interconnect wiring metallization and pillar metallization structures. The wet processing tool set 30 may be implemented in a LT-210 ™ brand copper electroplating tool supplied by Semitool Corporation, Carlisbur, Montana. Such a wet processing tool set preferably includes an input station 115 and an output station 120. The input station is used for accommodating multiple workpiece cassettes, or semiconductor workpieces in a single workpiece or multiple workpiece pockets. The output station is used for The processed workpieces in the bladder or cassette are supplied to one or more subsequent tool sets. The stations 115 and 120 are preferably combined into a single input / output station. The dual robot arms 125a and 125b are arranged to run in the direction of arrow 130, and are used to transfer semiconductor workpieces between a plurality of processing stations, and move to and from the output station 120 and the input station 115. The processing station of the wet processing tool set 30 performs at least three main wet processing operations. First, the wet processing tool set 30 includes a processing station that applies an electrodeposition process to apply copper metallization to the interconnection wiring patterns and column patterns formed by the pattern processing tool set 25. For this purpose, electrodeposition stations 135 and 140 are provided. In addition, the dressing station 145 may be used to dress a surface of a semiconductor workpiece to be electro-deposited with copper. Second, the wet processing tool set 30 includes a processing station for removing materials used to form the interconnect wiring patterns and the column patterns applied by the pattern processing tool set 25. Treatment stations 150 and washing / drying stations 155 and 160 are included for this purpose. Finally, one or more processing stations are used to remove portions of the seed layer and / or barrier layer that are not covered by the metallized interconnects, and / or to make these portions non-conductive. As will be explained in detail later, the oxidation station 165, etching station 170, and electrochemical paper size are applicable to China National Standard (CNS) A4 specifications (21〇 > < 297mm) (Please read the precautions on the back first (Fill in this page again) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 A7 ______B7 Five ^^ () Except station 175 can be used for this seed layer and the barrier layer treatment. The oxidation station 165 and the Cangjie carving station 170 may be combined into a single processing station. Alternatively, the processing tool 30 may be used to apply a protective coating over the interconnect wiring metallization and the pillar metallization. In the embodiment shown, the electrodeposition station 180 may be used for this purpose. The material used for the protective coating is preferably a material that prevents copper from migrating into both the dielectric and the coated copper oxide. Materials that can be used for protective coatings include, for example, nickel, nickel alloys, and chromium. The dielectric processing tool set 35 includes a plurality of processing stations for depositing a dielectric layer overlying interconnect wiring metallization and pillar metallization. In addition, the dielectric processing tool set 35 includes one or more processing stations for etching the deposited dielectric layer to expose the connection area above the pillar metallization. In the described embodiment, the dielectric processing tool set 35 includes an input station 185 for receiving semiconductor workpieces in a multi-workpiece cassette or in a single-workpiece or multi-workpiece pouch. The semiconductor workpiece is supplied from the input station 185 to the coating station 190, where the surface of each semiconductor workpiece is coated with a dielectric precursor or the like. After the workpiece has been coated, it is sequentially supplied to the baking station 195 and the curing station 200 to complete the formation of the dielectric material surrounding the interconnect wiring metallization and the pillar metallization. The semiconductor workpiece is then supplied to an etch-back station 205, where the upper surface of the dielectric layer is etched back to expose the upper connection area of the pillar metallization. Referring again to the third figure, the separate input and output stations 40 and 62 for the tool set 20 can optionally be combined at a single input / output station. In the same way, the separate input and output stations 65 and 110 of the tool group 25 can be combined into a single __ 17___ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) '— (Please read the back first Please pay attention to this page and fill in this page again}-, Yiding-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 A7 B7 V. Description of the invention (4) Input / output station, and a single input / output station for tool group 30 115 can be divided into separate input and output stations. When can one or more cassettes or capsules be kept in the input / output station. For separate input of tool set 35. And output stations 185 and 210 can also be selected A single input / output station. With reference to the sixth figure, the processing tool set described in conjunction with the third figure can be used to implement the manufacturing method procedure described below in conjunction with the fourth figure with a minimum number of workpiece movements between the tool sets. The program steps 215, 225, 237, and 260 of the figure can be implemented in the thin film deposition tool set 20. The program steps 270 and 300 can be implemented in the pattern processing tool set 25. The program steps 280, 290, and 308 to 380 can be implemented in the wet processing tool set. 30 Program steps 400 to 425 are implemented in the dielectric processing tool set 35. As a result of the specific processing steps used and the distribution of the processing steps among the various tool sets, it may be used no more than ten times, preferably no more than five times. The workpieces of the tool set move to form a single interconnected metallization layer, which is really less than the 13 workpiece movements required for the above double corrugation treatment. For this reason, the single workpiece movement indicated by the arrow 500 in the sixth figure is used to The workpiece is transferred between the thin film deposition tool set 20 and the pattern processing tool set 25. The three workpiece moving systems indicated by arrows 505, 510, and 515 are used to transfer the workpiece to the pattern processing tool set 25 and the wet processing tool set 30 Between. The single workpiece movement indicated by arrow 520 is used to transfer the workpiece between the wet processing tool 30 and the dielectric processing tool set 35. Thus, when compared to the traditional figures of the first and second figures The double corrugation processing and tool structure significantly reduce the number of workpiece movements. Used to form the disclosed metallized structure to move workpieces between tool sets (please read the precautions on the back before filling this page) , Τ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, “The Zhang scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 A7 ____B7________ V. Description of the Invention (Π) One of the basic procedures with the least movement is shown in the flowchart of the fourth figure, and the corresponding formation system of one embodiment of the metallized structure in various processing states is shown in the fifth A through 5K As shown in FIGS. 4 and 5A, the dielectric layer 210 is provided on the substrate 215, such as a semiconductor wafer. Although not specifically disclosed in the fifth A figure, the dielectric layer 210 also includes a channel from the contact to the plugging metal, which is exposed on top of the dielectric layer, which has been planarized and provided with a dielectric layer. The electrical connection between one or more components below its planar surface. One or more components below the planarized surface of the dielectric layer include another interconnected metallization layer that is directly connected to a semiconductor component or the like formed in a substrate. The dielectric layer 210 preferably has a relative permittivity of less than 4, and can be formed by applying or spraying the precursor material or the cured precursor material, which is anaerobic or oxygen-containing. Gases at temperatures below 450 ° C. A better choice for dielectric materials is benzocyclobutene (BCB). Preferably, the surface of the dielectric layer 210 is trimmed at step 215 to enhance the adhesion of the subsequently applied layers. The surface of the dielectric layer 210 can be trimmed by wet or dry chemical treatment or by ion polishing. The arrow 220 in the fifth A diagram shows that the upper surface of the dielectric layer 210 is trimmed by, for example, impacting argon or nitrogen ions. Alternatively, the upper surface can be trimmed by short (10 to 30 seconds) etching in a solution containing 1% to 2% hydrofluoric acid in deionized water. As shown in step 225 in Figures 5B and 4, an optional tie layer 230 may be applied to the surface of the dielectric 210. As mentioned above, the connecting layer 230 may include aluminum, titanium, or chromium, which uses a vapor deposition degree such as pVE, and is suitable for use with CNS A4 specifications (21GX29Hxian) " 'Please read the note on the back first Matters refill this page}

494443 A7 B7 V. Description of the invention () Technology and deposition. In step 237 of the fourth figure, the barrier layer 240 is deposited on the connecting layer 230 (if used), or directly on the surface of the dielectric 210. As shown, the barrier layer 240 is deposited over the substantially flat surface of the semiconductor workpiece, thereby eliminating the need to apply barrier material to high aspect ratio trenches and channels. The barrier layer 240 may include tantalum, giant nitride, titanium nitride, titanium oxynitride, titanium tungsten alloy, or tungsten nitride depending on the characteristics of other materials used for the interconnect structure. As described above, a two-layer composite barrier as disclosed by Stevens in U.S. Patent No. 4,977,440 and U.S. Patent No. 5,070,036 can be used to contact semiconductor device contacts. It should be noted that a tie layer that is deposited is not required to achieve acceptable adhesion between the tantalum barrier layer and the appropriately modified BCB surface of the dielectric layer 210. The barrier layer 240 may be made sufficiently conductive to facilitate subsequent electrodeposition processes for depositing interconnect wiring and pillar metallization. However, if the barrier layer 240 is not sufficiently conductive, a sub-layer may be required. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figures 5B and 4 of step 260 show the application of the seed layer 265, which is deposited in, for example, PVD or CVD. The seed layer 265 is typically copper, but may also include metals such as nickel, iridium, platinum, palladium, chromium, vanadium, or other conductive materials such as iridium oxide. The preferred thickness of the seed layer and the barrier layer is in the range of 200 to 600 A. Referring again to step 270 of FIG. 5B and FIG. 4, the interconnection pattern can be deposited using a well-established procedure in the photo-etching technique. For example, a photoresist 272 is used as a photomask. In this case, plasma treatment can be included as the last step in the photolithography process, or the Chinese National Standard (CNS) M specification (no, 〆297 mm) can be applied to the paper size of the interconnect wiring metal. 4444 Ministry of Economy Printed by Intellectual Property Bureau employee consumer cooperatives A7 B7 V. Description of the invention (q) Any processing stage prior to the electrodeposition of metal compounds' in order to remove photoresist residues from exposed portions of the seed layer surface. Treatment in HMDS can be used to form a layer 270, which enhances the adhesion between the photoresist and the copper seed layer 265. In addition, or instead, a thin (less than 100 A) copper oxide may be formed on the upper surface of the seed layer 265 to form the layer 270, and thereby improve the adhesion between the seed layer and the photoresist. Referring to step 280 of FIG. 5C and FIG. 4, the interconnection metallization 285 is formed by, for example, selective electrodeposition of copper into a photoresist interconnection pattern. Preferably, an acidic chemical bath is used for electrodeposition. The chemical bath can be prepared by adding copper sulfate and sulfuric acid to deionized water. As is generally known in the metal plating art, chemical baths can additionally include materials in small concentrations that affect the metal grain size and film consistency. After the interconnection metallization 285 has been deposited into the photoresist interconnection pattern, the photoresist is removed. Removal of the photoresist can be achieved by exposing the photoresist to a solvent or oxidant (such as ozonized deionized water) and then washing in water. This step is shown in steps 290 and 295 of the fourth figure and should be sufficient to remove the photoresist after selective metal deposition. The resulting structure is shown in the fifth D-graph. As shown in step 300 in the fifth E and fourth drawings, another photoresist pattern 305 is applied to the semiconductor workpiece to form an opening through which the pillar metallization 307 can be electrodeposited as shown in step 308. The metallization column 307 is shown in the fifth F diagram. After the pillar metallization has been deposited, the photoresist pattern is removed, leaving the interconnect structure of the fifth G pattern. Now refer to steps 315, 320 of the fifth and fourth drawings, and the paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page)

494443 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (,) 325, the seed layer 265 is partially or completely removed by, for example, electrochemical etching. Electrochemical contact can be achieved by exposing the seed layer to a suitable electrolytic solution such as a solution containing o-acid, while the seed layer is maintained at a positive potential relative to the electrode immersed in the electrolytic solution. Figure 5 shows a representative cross-section after partially removing the exposed seed layer, then forming copper tantalum oxide on the exposed surface of the barrier layer, and forming copper oxide on the exposed surfaces of the wires and pillars. Illustration. As detailed above, the seed layer 265 may be partially removed by immersion in an electrolytic solution containing phosphoric acid while the seed layer is maintained at a positive potential relative to an electrode immersed in the same electrolytic solution. The seed layer remaining after electrochemical etching is then converted into copper oxide. Alternatively, when the thickness of the seed layer is less than about 10% of the minimum line width, electrochemical etching may be omitted, and the seed layer may be completely converted into copper oxide. Referring to step 320, the exposed surfaces of the copper structures 285, 307, and 265 and the barrier layer 240 are oxidized by a solution including air, oxygen, water vapor, water containing undissolved oxygen, or ozone not dissolved in water. Alternatively, the surfaces may be oxidized by heating in an oxygen-containing gas. As shown in step 325, the resulting copper oxide can be removed by exposure to a solution containing sulfuric acid, gallic acid, or both sulfuric acid and gallic acid. Referring to the third figure, copper oxide removal can be achieved at the station 145 or the tool set 25. The protective coating 370 preferably provides an overlying interconnect structure. Such a protective coating is preferably formed in an electrochemical process, such as in step 375, which allows the material to be deposited on the exposed copper but not on the exposed barrier material coated with the oxide. The material used for the protective coating preferably includes a barrier

494443γ A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (v \) Copper migrates into the dielectric and further prevents the oxidation of the coated copper. These materials include nickel, nickel alloys, and chromium. The preferred thickness of the protective coating is in the range of 50 A to 500 A. The structure of the result is shown in the fifth I diagram. Referring to step 380 of the fourth figure, the barrier layer 240 and its covered oxide layer can be removed by wet chemical etching where it is not covered by the covered copper features. The wet chemistry may include a 1% to 5% solution of hydrofluoric acid in water, which is provided so that the barrier removal process does not excessively attack the copper features of the interconnect structure 302 or is located under the barrier layer 240. Dielectric 210. As shown in steps 400 and 405 of the fifth J diagram and the fourth diagram, another dielectric layer 410 is formed to a thickness sufficient to cover the upper surface of the pillar of the interconnect structure. This other dielectric layer 410 is preferably formed by spin application or spray application of a first-driven material or a subsequently cured precursor material, which is in an anaerobic or oxygen-containing gas at a temperature below 450 ° C. Under temperature. The composition of the dielectric layer 410 may be different from or the same as the composition of the dielectric layer 210. After the other dielectric layer 410 has been cured, the upper surface of this layer 410 is etched back to expose the upper contact area 420 of the pillar structure 307. For example, blanket plasma etch can be used to reduce the thickness of the layer 410 until the upper surface 420 of all the pillar structures 307 is exposed. For example, etching of BCB can be done in a plasma containing oxygen and fluoride ions. This step is shown in step 425 of the fourth diagram, and the structure of the result is shown in the fifth K diagram. Another embodiment of a tool architecture suitable for implementing the aforementioned processing steps is shown in FIG. The tool architecture shown in the seventh figure is similar to the specific embodiment of the tool set shown in the third figure used for the tool architecture of the sixth figure (although (please read the precautions on the back before filling this page) β, ν5 The size of the paper is applicable to the Chinese National Standard (CNS) Λ4 specification (210X2 and mm) 494443 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (π) Of course, the sixth picture is more general (Sexual processing tool group names can also be used in Figure 7 instead of implementing the specific tool group disclosed in Figure 3.) However, the tool architecture of the seventh figure includes an inspection tool set 600 for inspecting semiconductor workpieces in the middle stage of the application of a single metallization layer. For example, intermediate inspections are used to ensure the correct registration of various photoresist patterns and corresponding metallizations, and thus to ensure proper dielectric etchback. As such, each semiconductor workpiece may be provided to the inspection tool set 600 after the processing steps 270, 290, 300, 380, and 425 shown in the fourth figure. In the illustrated embodiment, ten workpiece movements are used to transfer a semiconductor workpiece between various tools of a tool processing architecture to form a single interconnect metallization layer. For example, the inspection tool set 600 may be implemented with an inspection device supplied and sold by KLA-Tencor. Tool architecture and procedures for patterning using a hard mask: Reveal at least four embodiments of a procedure for manufacturing a metallization layer using a pattern of a hard mask. In the first embodiment, only the interconnection metallization pattern is formed using a hard mask dielectric layer. In the second embodiment, both the interconnect metallization pattern and the pillar pattern are formed using a hard mask dielectric layer. The third and fourth program embodiments are similar to the first and second program embodiments, respectively, except that an intermediate inspection is performed during processing to ensure the correct formation of interconnections and column patterns. The processing architecture, processing tool set, and workpiece movement will be described in relation to each program embodiment. The basic tool set for implementing the processing architecture according to one embodiment of the present invention is not shown in the eighth figure. As mentioned, the tool set includes a thin film deposition tool set 1020, a hard mask forming tool set 1023, a pattern processing tool set 1025, and a paper size applicable to the Chinese National Standard (CNS) A4 specification (210X2 fiscal mm) " 494443 A7 B7 V. Description of the Invention (A) Hard mask etching tool set 1027, electrochemical / wet processing tool set 1030, and dielectric processing tool set 1035. In the embodiment disclosed in the eighth figure, the thin film deposition tool set 1020 is preferably a vacuum deposition tool set. As will be apparent from subsequent discussions of the processing operations performed on the workpiece, the thin film deposition tool set 1020 deposits one or more films on a substantially flat surface of the workpiece. Such thin film deposition is preferably a micro-recessed feature of the deposited film, which is used in the corrugation process. In this way, low cost vacuum deposition techniques such as physical vapor deposition (PVD) can be used. Chemical vapor deposition (CVD) processing can also be used. The specific embodiment of the thin film deposition tool set 1020 shown in the ninth figure includes a plurality of processing stations for trimming the surface of the workpiece, depositing a bonding layer, depositing a barrier layer, and deposition. The seed layer is on the workpiece. Preferably, the workpiece is first transferred to a dressing station where the surface of the substantially flat dielectric layer exposed on the outside of the substrate of the workpiece is processed to enhance adhesion of subsequent thin film layers. The adhesion enhancement of such a dielectric layer can be achieved by any one or more known plasma treatments. Depending on the characteristics of the dielectric layer and subsequent thin film layers, adhesion enhancement may not be required. In this case, the dressing station need not be included in the thin film deposition tool set 20. Each workpiece is then provided to a bonding film application station, where an additional bonding layer is applied to the outside of the dielectric layer (preferably directly onto it). Suitable materials for the tie layer include titanium, titanium, and chromium. Depending on the nature of the adjacent thin film layers, a tie layer may not be needed, and thus there is no need to include a tie film application station in the thin film deposition tool set 1020. The barrier layer application station is used to apply the barrier layer material to the workpiece. The Chinese National Standard (CNS) A4 specification (210X2 mm) is used. --- (Please read the precautions on the back before filling this page), 11-line economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives 494443 A7 V. Description of Invention (%) of the dielectric material outside. Depending on the nature of the other materials used in the interconnect structure, the barrier layer may include macro, molybdenum nitride, titanium nitride, titanium oxide, titanium tungsten alloy, or tungsten nitride. Especially when the interconnection layer contacts the terminals of the semiconductor device, it is better to use a composite barrier including two layers, as disclosed in Stevens U.S. Patent No. 4,977,440 and U.S. Patent No. 5,070,036. In order to increase the conductivity of the barrier layer and to provide good adhesion of the subsequent layers, the thin film deposition tool set 1020 preferably includes a seed layer application station. The seed layer application station preferably uses PVD or CVD processing to deposit the seed layer. The seed layer is preferably copper. After the seed layer has been applied, the workpiece is transferred to the output station for subsequent transfer to other processing toolsets. Printed hard mask forming tool set 1023 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes a plurality of processing stations for providing a hard mask dielectric layer over a seed layer applied by the thin film deposition processing tool set 1020 . This hard mask dielectric layer is finally patterned according to a photoresist pattern applied by the pattern processing tool set 1025. One or more hard mask layers are applied to provide a patterned mask for depositing one or both of interconnect wiring and pillar metallization. As will be described in further detail below, the interconnection pattern defines the area where the main conductor path is provided for the horizontal electrical connection of the plane of the workpiece, and the column pattern defines the area where the phase for the workpiece is provided. The main conductor path of a vertical electrical connection between adjacent planes. In the specific tool set embodiment shown in the tenth figure, the hard mask forming tool set 1023 includes an input station 1465, which is preferably a work piece received in a multi-workpiece cassette or in a single-workpiece or multi-workpiece pouch. Workpieces are imported from the input station '^ Paper size is applicable to Chinese National Standard (CNS) A4 specifications (210X20 mm) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 494443 A7 B7 V. Description of the invention (/) 1465 Provided to the coating station 1467 At this point, the workpiece is coated with one or more precursor materials. The workpiece is then provided to a baking station 1470 to (for example) bake off the solvent. The baking station 1470 is typically a hot plate. After processing at the baking station 1470, the workpiece is provided to a curing station 1473. Depending on the duration of the curing cycle, the curing station can be a hot plate or a small kiln. The curing cycle must not be selected as a work piece damage. After curing, the workpiece is supplied to the output station 1475. Although the illustrated embodiment shows separate input and output stations, it can be combined into a single input / output station. The pattern processing tool set 1025 of FIG. 8 includes a plurality of processing stations for providing interconnection wiring patterns to cover the hard mask layer applied by the hard mask forming tool set 1023. According to one of the disclosed processes, the pattern processing tool set 1025 is also used to provide a column pattern over an interconnect metallization formed using an interconnect pattern. Alternatively, as will be described below, the pattern processing tool set 1025 is used to provide a column pattern over another hard mask layer deposited by the hard mask forming tool set 1023, which is then A photomask is provided for the deposition of pillar metallization. In the embodiment of the tool set shown in FIG. 9, the pattern processing tool set 1025 is a photo-etching tool set. The pattern processing tool set 1025 itself includes workpieces such as semiconductor wafers that are received in an input station in a multi-piece cassette or in a single-piece or multi-piece hygienic pouch. In tool set 1025, the workpieces are sequentially subjected to standard photo-etching procedures such as trimming, coating, and baking. After the photoresist is baked on the workpiece, the workpiece is transferred to the input station of the photoresist exposure device, which is, for example, a step and repeat device that exposes the photoresist to ultraviolet light in the following manner: Selectively affect the photoresist layer, so that the size of the photoresist layer is applicable to the Chinese National Standard (CNS) A4 specification (210X2 mm)

494443 A7 V. The part of the description of the invention (ice) can be subsequently removed to form interconnections or column patterns. After the photoresist layer is exposed, the workpiece is provided to an output station for transfer to another processing station. It selectively removes the photoresist layer to form a pattern in this layer consistent with the exposure pattern in the photoresist exposure device. Pattern. These processing stations include a photoresist developing station and may include a plasma removal ("residue removal") station. After the selective removal of the photoresist layer and plasma removal, the work is transferred to an output station to be provided to one or more other tool sets. As shown in the ninth figure, the hard mask etching tool set 1027 includes an input station 1480, which is preferably a workpiece received in a multi-workpiece cassette or in a single-workpiece or multi-workpiece capsule. The workpiece is supplied from the input station 1480 to the etching station 1483, where the hard mask layer is selectively etched through the opening area of the patterned photoresist layer applied by the pattern processing tool set 1025. After the hard mask layer has been etched to form a mask pattern, the workpiece is supplied to the output station 1485. Although the embodiment shown in the tenth figure shows separate input and output stations, a single input / output station may be used. The hard mask etching tool set 1027 may be an electric pad etching device, such as sold by Tegal, Applied Materials, or LAM Research. Electrochemical / wet processing tool set 1030 of FIG. 8 implements a wide range of procedures for forming interconnect metallization and pillar metallization structures. Wet treatment tool set 1030 can be implemented on Equinox ™ brand tools or LT-210 ™ brand tools, both of which are supplied and sold by Semitool Company of Montana and Kalispell. As shown in the ninth figure, such an electrochemical / wet processing tool set preferably includes input and output stations and a plurality of stations for performing electrochemical and wet chemical processing. The processing stations of the wet processing tool set 30 perform at least three main wet processing operations. The first standard is applicable to China National Standard (CNS) 8-4 specification (210X2 mm) (Please read the precautions on the back before filling out this page) Printed by the Ministry of Economic Affairs Intellectual Property Bureau Employee Consumer Cooperatives Printed 494443 A7 B7 Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative V. Description of the invention (4) 1. The wet processing tool set 30 includes a processing station for applying a copper metallization to the pattern processing tool set 25 and / or a hard mask using an electrodeposition process. The interconnection wiring pattern and the pillar pattern formed by the etching tool set 1027. In addition, a dressing station may be used to dress the surface of a workpiece to be electrochemically deposited with copper. Second, the tool set 30 includes one or more processing stations for removing a hard mask material, which is used to define an interconnect wiring pattern and (in some program embodiments) a pillar pattern, It is applied by the hard mask forming tool set 1023, and by the hardening mask etching tool set 1027. Similarly, the wet processing tool set 30 includes one or more processing stations for removing photoresist material, which is used to define interconnect wiring patterns in a hard mask layer, and in some processes In the embodiment, the photoresist material is used to define the column pattern. Typically, a solvent station and a washing / drying station are provided for photoresist removal. Finally, one or more processing stations are used to remove portions of the seed layer and / or the barrier layer that are not covered by the interconnect lines and / or make these portions non-conductive. Alternatively, the processing tool 30 may be used to apply a protective coating to the interconnection metallization and pillar metallization. In particular embodiments, an electrodeposition station may be used for this purpose. The material used for the protective coating is preferably a material that prevents copper migration into the dielectric and oxidation of the coated copper. Examples of materials that can be used for protective coatings include nickel, nickel alloys, and chromium. The dielectric processing tool set 1035 includes a plurality of processing stations for forming a dielectric layer overlying interconnect metallization and pillar metallization. In addition, the dielectric / mass processing tool set 1035 includes one or more processing stations for a dielectric layer deposited by uranium etching to expose the connection area above the pillar metallization. Regarding the specific embodiment of the dielectric processing tool set shown in the ninth figure, the workpiece is input from the Please read the memorandum

Binding book paper size suitable for home _ home standard (CNS) A4 specification (21 () > < 2 mm) 494443 A7 ___B7 5. Description of the invention (J) station is provided to the coating station, where each workpiece The surface is coated with a dielectric precursor or the like. After the workpiece has been coated, it is sequentially supplied to a baking station and a curing station to complete the formation of a dielectric material surrounding the interconnect wiring metallization and the pillar metallization. The workpiece is then supplied to an etch-back station where the upper surface of the dielectric layer is etched back to expose the upper connection area of the pillar metallization. Referring to the eighth figure, the processing tool set can be used to implement the manufacturing process program described below in conjunction with the eleventh figure with a minimum number of workpiece movements between the tool sets. The processing steps 1215, 1225, 1237, and 1260 of the eleventh figure can be implemented in the thin film deposition tool set 1020. Processing steps 1270 and 1308 may be implemented in the pattern processing tool set 1025. Process steps 1277, 1280, and 1309 to 1380 may be implemented in wet processing tool set 1030. Process steps 1400 to 1425 can be implemented in the dielectric processing tool set 1035. The processing step 1261 may be performed in the hard mask forming tool set 1023, and the processing step 1273 may be performed in the hard mask etching tool set 1027. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as a result of the specific processing steps used and the distribution of processing steps among various tool sets. When the hard mask is only used as a pattern for interconnection wiring, it can be used up to The workpieces between the secondary tool sets move to form a single interconnected metallization layer. When the hard mask is used for the pattern of both the interconnect wiring and the pillar, as shown in Figure 16, a single interconnect metallization layer can be formed with no more than nine workpiece movements. For this purpose, a single work piece indicated by arrow 1500 of the eighth figure is used to transfer the work piece between the thin film deposition tool set 1020 and the hard mask forming tool set 1023. A workpiece moving system indicated by the arrow 1505 is adopted to apply the Chinese National Standard (CNS) A4 specification (210 × 29 ^ mm) to a scale between the hard mask forming tool group 1023 and the pattern processing tool group 1025. 494443 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4) Transfer of workpieces. Two workpiece movements 1510 and 1512 are used to transfer the workpiece between the pattern processing tool set 1025 and the wet processing tool set 1030. The single workpiece movement 1515 is used to transfer a workpiece between the pattern processing tool set 1025 and the hard mask etching tool set 1027. Similarly, a single workpiece movement 1517 is used to transfer a workpiece between the hard mask etching tool set 1027 and the wet processing tool set 1030. Finally, the single workpiece movement 1520 is used to transfer the workpiece between the chemical processing tool set 1030 and the dielectric processing tool set 1035. In this way, when compared to the conventional double wave processing structure and tool structure of the first and second figures, the number of workpiece movements between the tool sets is substantially reduced. In step 1261 of the first figure, the hard mask dielectric layer 1263 is deposited on the hard mask forming tool set 1023 and overlies the seed layer 1265. In step 1270 of the first figure, a well-established procedure in the photolithography technique can be used to deposit the interconnection pattern over the hard mask dielectric layer 1263 using, for example, a photoresist as an intermediate mask. The hard mask dielectric layer 1263 is then selectively etched through the opening portion of the photoresist layer 1272, as shown in step 1273. Step 1273 occurs at hard mask etch station 1027. Referring to step 1277 of FIG. 11, the photoresist layer 1272 is removed from the wet chemical processing station in the tool set 1030, leaving a patterned hard mask dielectric layer 1263 having a substantially vertical Wall to define interconnected metallization patterns. Referring to step 1280 of the eleventh figure, the interconnection metallization 1285 is formed by selectively electro-depositing, for example, copper into a hard mask interconnection pattern. Preferably, an acidic chemical bath is used for electrodeposition. The chemical bath can be prepared by adding copper sulfate and sulfuric acid to deionized water. For example, in the metal plating technology, the Chinese National Standard (CNS) A4 specification (hOX2 ^) mm is applicable.

Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 494443 A7 B7 V. Description of invention (furnace) As known in the art, small concentrations of substances that affect the metal grain size and thin film uniformity can be optionally included in the chemical bath in. The structural system created after the electrodeposition of copper is shown in Figure 12. In the twelfth figure, the roughly flat surface of the workpiece is shown at 1210, the finished part of the workpiece is shown at 1230, the barrier layer is shown at 1240, the hard mask layer is shown at 1263, and the seed layer is shown At 1265, and the demonstration interconnected metallization line is shown at a cross section of 1285. After the interconnect metallization has been deposited into the patterned hard mask dielectric layer, the workpiece can be returned to the pattern processing tool set 1025, where photoresist is applied and patterned using, for example, conventional photoresist patterning techniques Agent to form a pattern for pillar metallization. As in step 1308, another photoresist pattern is applied to the workpiece to form an opening through which the pillar metallization can be electrodeposited. The thirteenth figure shows the structure resulting from the patterning of the photoresist layer 1305 and the electrodeposition of the pillar metallization 1307 after step 1309 of the eleventh figure. After the pillar metallization has been deposited in step 1309, the photoresist pattern is removed in step 1310, and the hard mask dielectric layer is removed in step 1313. The removal of the hard mask dielectric layer is preferably performed in the tool set 1030, but it can also be performed in the hard mask etching tool set 1027 with two additional wafer movements. The hard mask dielectric layer 1263 can be removed before the patterned photoresist layer is formed. The fourteenth figure shows the structure after the photoresist 1305 is patterned and the pillar metal compound 1307 is electrodeposited. In this case, the treatment in HMDS can be adopted to form the lifting photoresist 305 and the copper seed layer. This standard is applicable to the Chinese Standard (CNS) A4 specification (21GX2 rape mm) ~~~ (Please read first (Notes on the back then fill out this page)

494443 A7 B7 V. Description of the invention (W)

The Ministry of Economic Affairs and Intellectual Property Bureau S Consumer Co., Ltd. printed an adhesive layer between 1265. In addition, or instead, a thin (less than 100 A) copper oxide layer may be formed on the surface of the seed layer 1265 to form a layer 1278, thereby improving the adhesion between the seed layer and the photoresist. Referring now to steps 1315, 1320, and 1325 of FIG. 11, the seed layer 1265 is partially or completely removed by, for example, an electrochemical etching process. Electrochemical etching can be achieved by exposing the seed layer to a suitable electrolytic solution (such as a solution containing phosphoric acid) while the seed layer 1265 is maintained at a positive potential relative to the electrode immersed in the electrolytic solution. At step 1320, the exposed surfaces of the copper structures 1285, 1307, and 1265 and the barrier layer 1240 are oxidized by exposure to undissolved air, oxygen, or ozone. Alternatively, the surface may be oxidized by heating in an oxygen-containing gas. As shown in step 1325, the resulting copper oxide can be removed by exposure to a solution containing sulfuric acid, osmic acid, or both sulfuric acid and osmic acid. For example, copper oxide removal may be done at an etching station of the tool set 30. Preferably, a protective coating is provided over the remaining interconnect structure. This protective coating is preferably formed in an electrochemical process, such as step Π75, which causes the material to be deposited on the exposed copper rather than on the exposed barrier material covered with oxide. The materials used for the protective coating preferably include materials that prevent copper from migrating into the dielectric and thereby prevent oxidation of the coated copper. These materials include nickel, nickel alloys, and chromium. The preferred thickness for the protective coating is in the range of 50 to 500 A. Referring to step 1380 of the eleventh figure, the barrier layer 1240 and its covered oxide layer can be removed by wet chemical etching where it is not covered to cover the copper features. Wet chemical engraving can include dilute acids, such as water with 5% to 5%

Order

494443 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (W) A solution of hydrofluoric acid, which is provided so that the barrier removal procedure does not excessively impact the copper wire and column features 1285 and 1307 or place A dielectric 1210 under the barrier layer 1240. In step 1400 of FIG. 11, another dielectric layer is formed to a thickness sufficient to cover the upper surface of the pillar of the interconnect structure. This other dielectric layer is preferably formed by spin-applying or spray-applying a precursor substance or precursor substance and then solidified, which is in an anaerobic or oxygen-containing gas at a temperature below 450 ° C. The composition of this dielectric may be different from or the same as the dielectric layer 1210. After another dielectric layer has been cured, the upper surface of this layer is etched back to expose the upper contact area of the pillar structure 1307. For example, blanket plasma etch can be used to reduce the thickness of the layer until the upper surface of the pillar structure 1307 is exposed. For example, the etching of BCB can be done in a plasma containing oxygen and fluoride ions. In this embodiment, the processing of the workpiece is substantially similar to the processing shown in the eleventh figure. From a processing point of view, the main difference occurs after the electrodeposition step 1280. In this later embodiment, the workpiece is removed from the wet processing tool set 1030 and returned to the hard mask forming tool set 1023, where the other hard mask dielectric layer 1422 (Figure 17) is disposed over The surface of the workpiece is shown in step 1427 in FIG. 15. After the formation of another hard mask dielectric layer 1422, the workpiece is transferred to the pattern forming tool set 1025 ', for example, where another photoresist layer 1432 is arranged to cover another hard mask dielectric Layer 1422, and pattern according to the desired pillar metallization pattern 'as in step 1429. The intermediate layer of the hard mask 1422, and then in step 1443, the paper size of the mound is applicable to China_5 " ^ 准 (CNS) A4 size (210X 2 mm) 1 '(Please read the precautions on the back first and then the page)-Installation ·

1T line 494443 A7 V. Description of the invention (V)) According to this pattern, an opening is formed by forming a pillar structure in the opening. The workpiece is then returned to the wet chemical processing tool set 1030, in which the photoresist layer 1432 is stripped in step 1310, and the copper pillar structure is electrodeposited in step 1309 via the hard mask dielectric layer 1422. Referring to FIG. 18, after electrodepositing the pillar metallization, the hard mask layer is removed, and processing is performed in the same manner as described in the procedure of FIG. As shown in the sixteenth figure, the entire metallization layer can be formed with nine wafers moved between the indicated tool groups. The Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs printed each of the aforementioned procedures and tool group / wafer movement to further strengthen the system. Shown in Figure 19 and Figure 20. The tool structures of the nineteenth and twentieth drawings each include an inspection tool set 600 for inspecting a workpiece in the middle stage of the application of a single metallization layer. For example, the intermediate inspection is used to ensure the correct registration of various photoresist and / or hard mask patterns and corresponding metal compounds, and thus to ensure the correct dielectric etchback. As shown in the nineteenth figure, after the processing steps 1270, 1280, 1308, 1380, and 1425 shown in the eleventh figure, each workpiece may be provided to the inspection tool set 1600. Similarly, as shown in the twentieth figure, after the processing steps 1270, 1280, 1429, .1380, and 1425 shown in the sixteenth figure, each workpiece may be provided to the inspection tool set 1600. In the embodiment shown in Figure 19, twelve workpiece movements are used to transfer the workpiece between various tools of the tool processing framework to form a single interconnected metallization layer. In the embodiment shown in Fig. 15, fourteen workpiece movements are used to transfer the workpiece between various tools of the tool processing framework to form a single interconnected metallization layer. For example, the inspection tool set 600 may be implemented with an inspection device supplied by KLA-Tencor. This paper size applies Chinese National Standard (CNS) A4 specification (210X2 milk mm) 494443 A7 B7 V. Description of the invention (called) The aforementioned system can be modified in various ways without departing from its basic disclosure. Although the invention has been described in detail with reference to one or more specific embodiments, those skilled in the art will recognize that changes can be made thereto without departing from the scope and scope of the invention described in the scope of the appended patents. spirit. (Please read the precautions on the back first, then this tribute.) Binding and binding Printed on paper by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs \ — / Ns 6 /.V

Centimeter

Claims (1)

494443 VI. Application Patent Scope 1 · ——A kind of manufacturing tool structure for applying one or more layers of interconnected metallization to the fully planarized dielectric surface of a workpiece, the tool structure includes: a thin film deposition tool set for deposition The barrier layer is on the outside of the flat dielectric surface, and the seed layer is deposited on the outside of the barrier layer; the pattern processing tool set is used to provide the interconnection wiring pattern covering the seed layer, and is used to provide the column pattern covering the interconnection wiring pattern. Formed interconnect wiring metallization; a wet processing tool set for performing at least the following wet processing operations: • applying an electrodeposition process to apply copper metallization to the interconnect wiring pattern and column pattern formed by the pattern processing tool set, • removal of materials applied by the pattern processing tool set to form interconnection wiring patterns and column patterns, • removal of seed layer and barrier layer portions not covered by interconnection wiring metallization; and dielectric processing tool set For depositing a dielectric layer over the interconnection metallization and pillar metallization, and for constructing interconnections The metallized structure etches the deposited dielectric layer to expose the upper connection area of the pillar metallization. 2 · The manufacturing tool structure described in item 1 of the scope of the patent application, wherein the thin film deposition tool set, pattern processing tool set, wet processing tool set and dielectric tool set are used to use no more than ten workpieces between the tool sets Movement forms an interconnect metallization structure, which includes interconnect metallization, pillar metallization, and a dielectric layer. 3 · The manufacturing tool structure as described in item 1 of the scope of patent application, where __—------ 1__ This paper size applies to China National Wood Standard (CNS) A4 (210 X 297 public) (Please read first Note on the back page, please fill in this page): Reference: Line: w: _ 494443 A8B8C8D8 VI. Application scope of patent (please read the notes on the back page before filling out this page) Thin film deposition tool set, pattern processing tool set, wet processing The tool set and the dielectric tool set are used to form an interconnected metallization structure using no more than five workpiece movements between the tool sets, which include interconnect wiring metallization, pillar metallization, and a dielectric layer. 4 · The manufacturing tool structure according to any one of claims 1 to 3 of the patent application scope, further comprising an inspection tool set for inspecting one or more processing states in the formation of the interconnected metallization structure . 5. The manufacturing tool structure as described in any one of claims 1 to 3, wherein the wet processing tool set includes at least one processing station for providing an electrodeposited protective coating on the outside of the copper metallization. 6 · The manufacturing tool structure according to any one of claims 1 to 3, wherein the wet processing tool set includes at least one processing station for trimming the surface of the workpiece before the wet processing tool set is further processed. Line 7 The manufacturing tool structure as described in any one of claims 1 to 3, wherein the wet processing tool set includes at least one processing station for oxidizing the exposed metallized portion of the workpiece. 8 · A manufacturing tool structure as described in any one of items 1 to 3 of the patent application, further comprising: a hard mask forming tool set designed to form a hard mask outside the seed layer A dielectric layer; and a hard mask etching tool set for etching an exposed area of the hard mask dielectric layer after the interconnection metallization structure is formed. 9. · A manufacturing tool structure for providing one or more layers of interconnected metallizations to a workpiece to fully planarize the dielectric surface. The tool structure includes: _ 2 This paper size is applicable to China National Standard (CNS) A4 specification (210 x 297 Mod ') 1 — 494443 098825 ABCD 6. Scope of Patent Application (Please read the notes on the back before writing this page) The first device is used to deposit a barrier layer on the outside of a flat dielectric surface, and It is used for depositing a sub-layer outside the barrier layer; the second device is used to provide an interconnection wiring pattern overlying the seed layer, and a pillar pattern over an interconnection wiring metallization formed by using the interconnection wiring pattern;.: > The third device is used to achieve at least the following wet processing operations. The electrodeposition process is used to provide copper metallization to the interconnection wiring patterns and column patterns formed by the second device, and the second device is removed. Material applied to the device to form interconnect wiring patterns and column patterns, and to remove seed layer portions and barrier layer portions not covered by interconnect metallization; a fourth device Depositing a dielectric substance layer for overlying interconnect metallization and metal pillars thereof, and means for etching the deposited dielectric layers, more exposed to the upper end of the connecting beam metallization region to form a single metallization layer. 10 · The manufacturing tool structure according to item 9 of the scope of the patent application, wherein the tool group forms a single metallization layer including interconnect wiring metallization, pillar metallization, and dielectric layer. Use no more than ten between the tool groups. Workpiece moves. 11 · The manufacturing tool structure according to item 9 of the scope of the patent application, wherein the tool set is formed, and a single metallization layer including interconnect metallization, pillar metallization, and dielectric layer is used not more than between the tool sets. Five workpieces move. 12 · If any of the items in the scope of the patent application item 9 to 11 apply to the Chinese paper standard (CNS) A4 specification (210 X 29 $ mm) " A8B8C8D8 494443 Tool structure, wherein the second device includes an electrodeposited protective coating for providing an exterior of a copper metallization. 13 · The manufacturing tool structure according to any one of claims 9 to 11 in the scope of the patent application, wherein the third device includes at least one processing station for trimming the workpiece before the third device is further processed. surface. 14 · The manufacturing tool structure according to any one of claims 9 to 11 in the scope of the patent application, wherein the two types of & device include at least one processing station for oxidizing the exposed metallized part of the workpiece ° 15 · — A manufacturing tool structure for providing a fully planarized dielectric surface of interconnected metallizations or multiple layers to a workpiece. The tool structure includes: a thin film deposition tool set for depositing Barrier layer; a pattern processing tool set for manufacturing interconnection wiring patterns outside the barrier layer and forming a column pattern over the interconnection wiring metallization using the interconnection wiring pattern; a wet processing tool set for realizing At least the following wet processing operations: Supply copper metallization, which uses an electrodeposition process to 'interconnect wiring patterns and column patterns formed by the pattern processing tool set' Remove materials provided by the pattern processing tool set to form interconnect wiring Patterns and column patterns, and removing seed layer portions and barrier layer portions that are not covered by the interconnection wiring metallization; and a dielectric treatment Kit for interconnecting metallization and pillars (please read the notes on the back before writing this page) 丨 _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 494443 A8. B8 ___ ^ _ VI. Deposit a dielectric layer on top of the metallization and apply to the deposited dielectric layer to expose the upper end connection area of the pillar metallization, including the interconnection The single metallization layer of the wiring metallization, pillar metallization, and dielectric layer is formed by using no more than ten workpiece movements between tool sets. 16 · The manufacturing tool structure according to item 15 of the scope of the patent application, which includes a single metallization layer of interconnect wiring metallization, pillar metallization and dielectric layer, which is moved using no more than five workpieces between tool sets Formed. Π · --A tool system for manufacturing a metallized structure on a fully planarized dielectric surface of a microelectronic workpiece, comprising: a thin film deposition tool set having at least one design formed on the outside of the planarized dielectric layer A thin film deposition tool for at least one thin film layer; a pattern processing tool set designed to form a pattern layer having a voided metallization pattern that defines an interconnect junction pattern and / or a column pattern over an exposed portion of the thin film layer; A wet processing tool set designed to (a) deposit copper into the voids of the pattern layer to form copper elements, (b) remove the pattern layer to release copper elements, and (c) form outside the planarized dielectric surface The method of interconnecting the metallization structure removes the part of the thin film layer that is not covered by the copper element. 18 · The tool system according to item 17 of the scope of the patent application, wherein the thin film deposition tool set, pattern processing tool set, and wet processing tool set use no more than ten workpieces to move between the tool sets to form an interconnected metallization structure. 19 · The tool system as described in item 17 of the scope of the patent application, in which the thin film deposition tool set, pattern processing tool set, and wet processing tool set, the __ ^ ________ ^ paper degree is applicable to China National Standard (CNS) A4 specifications (210 X 297; centimeters) (Please read the precautions on the back before writing this page) Order: Line · 494443 SI VI. Patent application scope Use no more than five workpieces to move between groups to form an interconnected metal structure . 20. The tool system according to any one of claims 17 to 19 of the scope of patent application, further comprising a dielectric processing tool set, which deposits a dielectric layer on the interconnected metallization structure, and The deposited dielectric layer is etched by exposing the locally interconnected metallization structure. 2! The tool system according to any one of claims 17 to 19, wherein the at least one thin film deposition tool includes a first thin film deposition tool designed to form a barrier outside a flat dielectric Layer, and a second thin film deposition tool designed to form a seed layer outside the barrier layer. 22. The tool system according to any one of claims 17 to 19 in the scope of patent application, wherein the wet processing tool includes at least one processing station to provide an electrodeposited protective coating on the outside of the interconnected metallization structure. 23. The tool system according to any one of claims 17 to 19 in the scope of patent application, wherein the wet processing tool includes an electrodeposition station to provide copper into the metallization pattern, and a dressing station to dress X The surface of the piece, and the exposed metallized portion of the workpiece used to oxidize the workpiece. 24. The tool system according to any one of claims 17 to 19 of the scope of patent application, further comprising an inspection tool set for inspecting one or more workpieces in a processing state in the interconnected metallization structure composition. 25. The tool system according to any one of the 17th to 19th in the scope of patent application, further comprising: a hard mask forming a tool set to form a hard mask dielectric layer at __ _— & -— ___ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before writing this page), 1T! Line 494443 A8 B8 C8 D8 VI. Application Patent scope outside the seed layer; and (Please read the precautions on the back before writing this page) A hard mask etching tool set for etching the hard mask dielectric layer after interconnecting the metallization structure. Exposure area. 26. A process for providing one or more protective copper elements on a surface of a workpiece, the process comprising: providing at least one thin film conductive layer to a workpiece; making a first part of the surface of the at least one thin film conductive layer non-platable to Define the desired metallization pattern on the second portion of the thin film conductive layer, where the second portion of the thin film conductive layer is electro-depositable; and plate one or more copper components onto the second plateable portion of the thin film conductive layer. 27. The treatment as described in item 26 of the scope of patent application, further comprising: substantially removing the exposed portion of the thin-film conductive layer after the line from the electric ore. Copper element to the second plateable portion of the thin-film conductive layer; and electroplating; A protective layer is applied to the surface of the copper element. 28. The process of claim 26 or 27, further comprising providing a dielectric layer on at least a portion of one or more copper elements. 29. The process according to item 27 of the scope of patent application, wherein the substantial removal of the seed layer includes dissolving the seed layer into an electrolyte liquid bath with phosphoric acid, while maintaining the seed layer at a high potential, which is relative to immersion in the electrolyte solution Bath electrode potential. ^ 30 · The treatment as described in item 26 or 27 of the scope of patent application, further including: π This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494443 A8B8C8D8 A dielectric layer to substantially cover the one or more copper components; and (please read the precautions on the back before writing this page) remove the surface portion of the dielectric layer to expose the one or more copper components One or more areas. 31. The treatment as described in item 26 or 27 of the scope of patent application, making the first part of the surface of the at least one thin-film conductive layer non-platable, which includes the exposed surface of the thin-film conductive layer. 32. The process as described in item 26 or 27 of the scope of patent application, wherein electroplating the copper element includes: electroplating one or more copper wires on a selected portion of the thin-film conductive layer; and electroplating one or more copper posts on Selected part of copper wire. · 33 · The process described in the scope of patent application No. 26 or 27, wherein the surface of the first part of the at least one thin film conductive layer is made non-platable to define the desired metallization pattern on the second part of the thin film conductive layer, Including: simultaneously oxidizing the thin film conductive layer and the exposed surface of the copper element; and removing the final copper oxide from the copper element. 34. The process according to item 26 or 27 of the scope of patent application, wherein at least one thin-film conductive layer is provided, comprising: forming a barrier layer as a first thin-film layer on the workpiece; and one or more copper elements formed by At this time, a kind of sub-layer is formed on the barrier layer as a second thin film layer. 35. The process as described in item 26 or 27 of the scope of patent application, wherein electroplating the copper element includes: exposing a selected portion of the thin-film conductive layer to provide a pattern light --- § ------ this Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 494443 C8 D8 6. The scope of patent application is on the thin film conductive layer; and (Please read the precautions on the back before writing this page) Plating The copper element passes through the selectively exposed portion onto a thin film conductive layer. 36. A process for providing one or more protective copper elements to a workpiece surface, the process comprising: providing a conductive barrier layer to a workpiece; electroplating one or more copper elements to a selected portion of the conductive barrier layer; At least a portion of the surface of the conductive barrier layer cannot be plated; and a protective layer is plated on the surface of one or more copper elements. 37. A treatment for providing one or more copper metallization layers to a surface of a neutrino workpiece, the treatment comprising: providing a barrier layer to the microelectronic workpiece; providing a sublayer to the barrier layer; electroplating one or more A copper interconnect to a selected portion of the seed layer; electroplating one or more copper pillars to a selected portion of the copper interconnect connection; substantially removing the seed layer; and simultaneously oxidizing the exposed surface of the one or more copper interconnect connections. The exposed surface of one or more copper pillars and the exposed surface of the barrier layer; the final copper oxide layer is removed from the one or more copper interconnects and the one or more copper pillars, while maintaining a substantially complete surface of the oxide barrier layer So that the surface of the barrier layer cannot be electro-mineralized; and a protective layer is plated to the exposed surface of the one or more copper interconnections. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)