JP2002515645A - Method and manufacturing tool structure for use in forming one or more metallization levels in a workpiece - Google Patents

Abstract

  (57) [Summary] Semiconductor fabrication tool arrangements and methods for providing one or more interconnect metallization levels on a generally planar dielectric surface of a semiconductor workpiece with only a minimal number of workpiece transfer operations between tool sets A method is disclosed.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION An integrated circuit is an ensemble of interconnecting devices formed in a semiconductor material and in a dielectric overlying the surface of the semiconductor material. Devices that can be formed in semiconductor materials include MOS transistors, bipolar transistors, diodes, and dissipation resistors. Devices that can be formed in the dielectric include thin film resistors and capacitors. Typically, more than 100 integrated circuit dies (IC chips) are constructed on a single 8-inch diameter silicon wafer. The equipment used for each die is
Interconnected by conductor paths formed in the dielectric. Typically, two or more levels of conductor paths are used as interconnects, with successive levels separated by dielectric layers. In current practice, aluminum alloys and silicon oxides are commonly used for conductors and dielectrics, respectively.

[0002] The propagation delay of electrical signals between devices on a single die limits the performance of integrated circuits. More specifically, these delays limit the measure by which an integrated circuit can process these electrical signals. As the propagation delay increases, the speed at which the integrated circuit can process the electrical signal decreases, while as the propagation delay decreases, the speed increases. Therefore, integrated circuit manufacturers are looking for ways to reduce the propagation delay.

[0003] For each interconnect path, the signal propagation delay can be characterized by a time delay τ. EH Stevens, Interconnect Technology, QMC, Inc., July 1993
Please refer to. As it relates to the transmission of signals between transistors on an integrated circuit,
The approximate expression for the time delay (τ) is given by τ = RC [1+ (V _SAT / RI _SAT )].

[0004] In this equation, R and C are the equivalent resistance and capacitance, respectively, for the interconnect path, and I _SAT and V _SAT are respectively the current saturation of the transistor that applies the signal to the interconnect path. Saturation (maximum) current at onset and drain to source potential. Path resistance is proportional to the resistivity (ρ) of the conductor material. Path capacitance is proportional to the relative dielectric constant (K _e ) of the dielectric. For small values of τ, the interconnect line must carry a sufficiently large current density to reduce the ratio V _SAT / RI _SAT . Therefore, low ρ conductors and low _Ke dielectrics that can carry high current densities must be utilized in the manufacture of high performance integrated circuits.

To meet the aforementioned criteria, instead of copper interconnect lines in a low K _e dielectric,
Using aluminum alloy lines in silicon oxide dielectrics is probably the most preferred interconnect structure. Here, "Copper Goes Mainstream:
Low-k to Follow, Semiconductor International, November 1997, pp. 67-70.
Please refer to. The specific resistance of the copper film is in the range of 1.7 to 2.0 μΩcm, while the specific resistance of the aluminum alloy film is higher and is higher than 3.0 to
. It is in the range of 5 μΩcm.

[0006] Despite the advantageous properties of copper, several issues must be addressed to make copper interconnects practical in large-scale manufacturing processes.

[0007] Copper diffusion is one such problem. Under the influence of an electric field, at only moderately elevated temperatures, copper moves rapidly through silicon oxide. It is believed that copper migrates rapidly through the low _Ke dielectric. Such copper diffusion results in the failure of devices formed in the silicon.

Another problem is that copper tends to oxidize rapidly when immersed in an aqueous solution or when exposed to an oxygen-containing atmosphere. The oxidized surface of copper becomes non-conductive, limiting the current carrying capacity of a given conductor path as compared to non-copper oxide paths of similar dimensions.

[0009] Yet another problem with the use of copper in integrated circuits is the difficulty of using copper with dielectrics in multilayer integrated circuit structures. Using traditional copper deposition methods, the adhesion of copper to the dielectric is much weaker.

Finally, direct plasma etching of copper cannot be used in copper fine line patterning because copper does not form volatile halogen compounds. Thus, copper is difficult to use in the increasingly smaller geometries required for advanced integrated circuit devices.

[0011] Although the semiconductor industry has addressed some of the aforementioned problems, it has generally adopted a standard interconnect architecture for copper interconnects. To this end, to achieve copper fine line patterning, trenches and vias are etched in the dielectric, copper is deposited in the trenches and vias, and the top of the dielectric is etched by chemical mechanical polishing (CMP). They found a method of removing copper from above the surface. Copper wires can also be formed in the dielectric using an interconnect architecture called a double wave pattern. FIG. 1 illustrates the process steps typically required to implement this double-wave pattern architecture.

The present inventors have found that it is often difficult for a semiconductor manufacturer to implement a double-wave pattern architecture in a large-scale manufacturing process. It is difficult to deposit a thin silicon nitride etch stop layer without damaging the underlying low _Ke material. Although techniques for plasma etching the dielectric is well established, it is difficult to perform Sabuhafu micrometer of etching the low-K _e dielectrics while maintaining selectivity to silicon nitride.

There are at least two particularly complicated processes in forming a double-wave pattern architecture. First, it is difficult to deposit thin and uniform barrier and seed layers in high aspect ratio (depth / diameter) vias and high aspect ratio (depth / width) trenches. The tops of such trenches, vias, tend to pinch off before completely filling or layering the respective trenches and / or vias with the desired material. In addition, CMP and its associated cleaning procedures are particularly complex and difficult to perform.

[0014] In addition to its difficulties and complexity, the double-wave pattern architecture limits interconnect performance. The etch stop layer (typically consisting of silicon nitride)
Has a high dielectric constant. Thus, unless the etch stop layer is very thin compared to the line thickness, the capacitance between metal lines at the same interconnect level is dominated by coupling through the etch stop. The conductivity of known barrier materials is negligible compared to the conductivity of copper, so the conductance of thin interconnect lines is reduced by the barrier layer, which must be interposed between copper and dielectric. It decreases significantly.

A processing tool architecture suitable for performing the double-wavy process steps shown in FIG. 1 is shown in FIG. As shown in FIG. 2, this double wave pattern architecture can be implemented by a set of 10 tools. The formation of each interconnect level generally involves two precision photo printing processes, two precision etchings, four dielectric depositions, barrier layers, seed layer depositions, copper depositions, CMP and post-C
Requires MP Clean. Small vias and trenches must be etched together. Therefore, the etching tool requires defining the via properties in the silicon nitride film. And the second etching tool is low
Requires that define the via openings and trenches function K _e dielectric. Using the traditional processing tool architecture of FIG. 2, forming each metallization level requires moving at least 13 workpieces of the tool set.

The significant number of wafer movements used to form the double-wave pattern interconnect metallization structure reduces the reliability and yield of the manufacturing process. As the number of wafer movements increases, the possibility of mishandling of one or more wafers increases. In addition, embodying manufacturing facilities for applying a double-wavy interconnect metallization structure requires significant invested capital for purchases above the average of the required tool set. Such reliability and invested capital costs issues are addressed by at least one aspect of the present invention.

In view of the foregoing problems, the present inventors have determined that a copper metallization layer may be an effective barrier material to prevent copper diffusion and an effective barrier material on the copper metallization layer to prevent copper oxidation. It also recognized that a protective layer was required. Existing processes for producing such metallization layers are inefficient and not economically viable for use in large-scale manufacturing operations. SUMMARY OF THE INVENTION Semiconductor fabrication for applying one or more interconnect metallization levels to a substantially planar dielectric surface of a semiconductor workpiece while minimizing the number of workpiece transfer operations between tool sets. A tool structure is disclosed herein. This tool structure consists of a film deposition tool set, a pattern processing tool set,
It includes a wet processing tool set and a dielectric processing tool set. The film deposition tool set is used to deposit a barrier layer independent of the planar dielectric surface of the semiconductor workpiece and a conductive seed layer independent of the barrier layer. The patterning tool set is used to provide an interconnect line pattern over the seed layer and to provide a post pattern over the interconnect line metallization formed using the interconnect line pattern. The wet processing tool set is used to perform at least the following wet processing operations. Applying a copper metallization to the interconnect line and post patterns formed by the patterning tool set using an electrochemical deposition process, removing the applied material by the patterning tool set. Forming interconnect line patterns and post patterns, and removing portions of the non-overlapping seed and barrier layers of the interconnect line metallization. A dielectric processing tool set deposits a dielectric layer over the interconnect line metallization and post metallization,
It is used to etch the deposited dielectric layer to expose the upper connection area of the post metallization.

The workpiece may be moved multiple times between tool sets to form a single metallization level. Preferably, no more than 10 workpiece movements between the tool sets are performed, more preferably, no more than 5 workpiece movements between the tool sets.

In some instances, it may be necessary or desirable to use a hard mask to pattern the interconnect metallization. To this end, alternative tool structures include a film deposition tool set, a hard mask forming tool set, a hard mask etching tool set, a pattern processing tool set, a wet processing tool set, A dielectric processing tool set. The film deposition tool set is used to deposit a conductive barrier layer on the outer surface of a flat dielectric surface of a workpiece and a conductive seed layer on the outer surface of the barrier layer. The hardmask forming tool set forms a hardmask dielectric layer on the outer surface of the seed layer according to one of the processes disclosed herein, and then applies yet another hardmask dielectric layer on the outer surface of the hardmask dielectric layer. Used to form. According to the first disclosed process, a pattern processing tool set provides an interconnect line pattern over a hardmask dielectric layer;
Used to provide a post pattern over an interconnect line metallization formed using the interconnect line pattern. According to a second disclosed process,
The patterning tool set provides a post pattern over the additional hardmask dielectric layer such that the post pattern is ultimately formed within the additional hardmask dielectric layer. Used for The hardmask etch tool set is used to etch exposed areas of the hardmask dielectric layer after forming the interconnect line pattern, and according to the second disclosed process, after forming the post pattern. Used to etch exposed portions of the further hardmask dielectric layer. The wet processing tool set performs at least the following wet processing operations. 1) applying copper metallization to the interconnect line and post patterns formed by the patterning tool set using an electrochemical deposition process; and 2) applying the copper metallization by the patterning tool set. 3) removing the hardmask dielectric layer and, if necessary, removing another hardmask dielectric layer; and 4) removing the removed material to form interconnect line and post patterns. The removal of the non-overlapping seed and barrier layers of the interconnect line metallization. A dielectric processing tool set is used to deposit a dielectric layer over the interconnect line metallization and the post metallization, and to etch the deposited dielectric layer to expose the upper interconnect region of the post metallization. .

According to a particular embodiment of the tool set architecture, an inspection tool set may be included. The semiconductor workpiece is transferred to an inspection device at various intermediate stages of the metallization process, for example, to ensure proper positioning of the pattern layer and the resulting metallization structure. In such an example, no more than 10 workpiece movements between the tool sets can be made to form a single metallization level. When using a hardmask tool architecture, when the inspection tool set is used, it is preferable to make no more than 14 workpiece movements between the tool sets. More preferably, no more than seven workpiece movements are made between the tool sets.

A process for providing one or more protected copper elements on a surface of a workpiece is also described. According to this process, a barrier layer is applied to a workpiece. If the barrier layer is not suitable as a seed layer for a subsequent electroplating process, another seed layer is applied over the surface of the barrier layer. Next, one or more copper elements are electroplated on selected portions of the seed layer, or, if appropriate, on selected portions of the barrier layer. If used, the seed layer is then substantially removed. At least a portion of the surface of the barrier layer is rendered non-plateable while leaving copper elements suitable for electroplating. Next, a protective layer is electroplated on the surface of the one or more copper elements.

A tool architecture for performing the above-described process is also described herein. The disclosed tool architecture is used to minimize the number of wafer movements between tool sets required to form a complete metallization structure.

DETAILED DESCRIPTION OF THE INVENTION A basic understanding of certain terms used herein will assist the reader in understanding the disclosed subject matter. To this end, the basic definitions of certain terms as used in this disclosure are set forth below.

A single level of metallization is defined as a composite level of the workpiece independent of the substrate. This composite level includes one or more interconnect lines, one or more interconnect posts substantially covered by a dielectric layer, such that the dielectric layers interconnect with each other. Isolate selected interconnect lines, interconnect posts that are not designed.

A substrate is defined as one base material layer on which one or more metallization levels are disposed. For example, the substrate may be a semiconductor wafer, ceramic block, or the like.

A workpiece is defined as an object that includes at least a substrate, and includes another layer of material or a manufactured component, such as one or more metallization levels disposed on the substrate. Is also good.

The present invention uses a novel method of applying a copper metallization to a workpiece (eg, a semiconductor product). This method minimizes the number of processing tool sets,
Provides an easily manufacturable copper metallization level with a minimum number of workpiece transfers between tool sets. The manufacturing process steps used to construct the resulting copper interconnect levels can avoid many processing steps, including the inherent problems associated with corrugated interconnect structures. For example, seed layers, copper metallization layers, and barrier layers no longer need to be deposited on high aspect ratio trenches, vias using an incompatible deposition process. Rather, the barrier layer and the metal seed layer are preferably applied to the workpiece in a blanket deposition process over the planarized surface of the workpiece. Subsequent deposition of the copper metallization used to form at least the lines is performed using an electrochemical deposition process that deposits copper only at the bottom of the openings in the patterned hard mask layer, thereby ensuring the lines. The pinch-off problem associated with the three-dimensional filling of trenches and vias that are completely formed and used in the wave patterning process can be eliminated. Similarly, deposition of the copper metallization used to form the posts is accomplished using an electrochemical deposition process, where either a patterned hard mask layer or a patterned photoresist layer is formed. Copper is deposited first at the bottom of the opening in the hole. Further, an electrochemical planarization and / or etching process may be chosen, avoiding a chemical mechanical polishing process.

Manufacturing of the disclosed interconnect level architecture is achieved with a minimum number of workpiece processing tool sets and a minimum number of workpiece movements between the tool sets. In this way, the invested capital costs in the design of the manufacturing facility used for the creation of this interconnect structure can be minimized. Further, by reducing the number of workpiece movements between tool sets, the risk of damage to the workpiece can be significantly reduced.

A basic tool set for implementing a tool architecture according to one embodiment of the present invention is shown in FIG. As shown, the tool set includes a film deposition tool set 20, a pattern processing tool set 25, a wet processing tool set 30, and a dielectric processing tool set 35.

In the disclosed embodiment of FIG. 3, the film deposition tool set 20 is preferably a vacuum deposition tool set. As will become apparent from the following description of the processing operations performed on the semiconductor workpiece, the film deposition tool set 20 deposits one or more films on a substantially planar surface of the semiconductor workpiece. Such film deposition is preferred for depositing films with micro-indentation features used in corrugating processes. In this way, low cost vacuum deposition techniques, such as physical vapor deposition (PVD), can be used. Chemical vapor deposition (
CVD) processes can also be used.

A particular embodiment of the film deposition tool set 20 shown in FIG. 3 includes an input station 40 arranged to receive a semiconductor workpiece. The input station 40 can be configured to receive a semiconductor workpiece in a multi-workpiece cassette or multi-workpiece or single-workpiece clean pod. The semiconductor workpiece is transferred from the input station 40 to a plurality of processing stations. Preferably, the semiconductor workpiece is first transferred to a conditioning station 45, where the surface of the substantially planar dielectric layer disposed on the outer surface of the substrate is treated to improve the adhesion of the next film layer.
Such adhesion enhancement of the dielectric layer can be achieved using one or more any of the known dry chemical processes. Depending on the properties of the dielectric layer and the subsequent film layer, adhesion enhancement may not be necessary. In such an example, conditioning station 45 need not be included in film deposition tool set 20.

Next, each semiconductor workpiece is sent to a bonding film application station 50,
There, an optional bonding layer is applied to the outer surface of the dielectric layer (preferably directly).
Apply. Suitable materials for the bonding layer include aluminum, titanium, and chromium. Preferably, such bonding layer material is deposited using a deposition technique (eg, PVD or CVD). Depending on the properties of the adjacent film layers, tie layers may not be desirable. In that case, the film application station 50 need not be included in the film deposition tool set 20.

A barrier layer application station 55 is located within the film deposition tool set 20 and is adapted to apply a barrier layer material to a dielectric outer surface of the semiconductor workpiece. Depending on the properties of other materials incorporated into the interconnect structure, the barrier layer may be comprised of tantalum, tantalum nitride, titanium nitride, titanium oxynitride, titanium-tungsten alloy or tungsten nitride. In particular, when the interconnect level is in contact with the terminal of the semiconductor device, the two layers can be used as taught in Stevens US Pat. No. 4,977,440 and US Pat. No. 5,070,036. Advantageously, a composite barrier is used. This barrier layer can be formed using a vacuum deposition process (eg, PVD or CVD).

To increase the conductivity of the barrier layer and improve the adhesion of subsequently formed layers, the film deposition tool set 20 preferably includes a seed layer application station 60. Seed layer application station 60 preferably deposits the seed layer using a PVD or CVD process. The seed layer is preferably copper, but may be made of a metal such as nickel, iridium, platinum, palladium, chromium, vanadium, or other conductive material (eg, iridium oxide). Good. After the seed layer has been applied, the semiconductor workpiece is transferred to the output station 62 and from there to another set of semiconductor processing tools.

The pattern processing tool set 25 includes a plurality of processing stations that are used to provide an interconnect line pattern over the seed layer applied by the film deposition processing station 20. . The patterning tool set 25 is also used to provide a post pattern over the interconnect metallization formed using the interconnect line pattern. As described in more detail below, the interconnect line pattern defines an area where the primary conductor paths are horizontal electrical interconnects in the plane of the semiconductor workpiece, and the post pattern defines An area is defined as a vertical electrical connection between adjacent planes of the semiconductor workpiece.

In the tool set embodiment shown in FIG. 3, the pattern processing tool set 2
5 is a photolithography tool set. Thus, the pattern processing tool set 25 includes an input station 65 that houses the semiconductor workpiece in a multi-workpiece cassette or single-workpiece or multi-workpiece clean pod. The semiconductor workpiece undergoes standard photolithographic conditioning, coating, and baking processes at respective processing stations 70, 75, 80. After the photoresist has been printed onto the semiconductor workpiece at station 80, the workpiece is transferred to an input station 85 of a photoresist exposure apparatus 90. Photoresist exposure apparatus 90 selectively affects the photoresist layer and then removes portions of the photoresist layer to form an interconnect line pattern or post pattern.
It may be a step-and-repeat device that exposes the photoresist to ultraviolet light.

After processing in the photoresist exposure apparatus 90, the semiconductor workpiece is sent to an output station 95 of the apparatus 90, from where it is transferred to another processing station.
These other processing stations selectively remove the photoresist layer and form a pattern in the layer that matches the pattern exposure in the photoresist exposure apparatus 90. Such a processing station includes a photoresist developing station 10
0 and a plasma cleaning (“descaling”) station 105. After selectively removing the photoresist layer and performing a plasma cleaning, the semiconductor workpiece may be transferred to an output station 110 or, optionally, to an intermediate UV cure station 107, where From one to more output stations 110 with one or more further tool sets.

The wet processing tool set 30 implements a wide range of processes used to form interconnect line metallization and post metallization structures. The wet processing tool set 30 may be implemented with LT-210 blade copper plating tools available from Semitool, Inc. of Kalispell, Montana. Such a wet processing tool set preferably includes an input station 115 that houses semiconductor workpieces in a multi-workpiece cassette or single-workpiece or multi-workpiece pod, and one or more An output station 120 for supplying processed workpieces in pods or cassettes to a subsequent set of tools. Stations 115, 120 are preferably combined into a single input / output station. Double robot arm 1
25a, 125b are arranged to move in the direction of arrow 130, and output stations 120 and input stations 115 between a plurality of processing stations.
Used to transfer semiconductor workpieces to and from them.

The processing stations of the wet processing tool set 30 perform at least three primary wet processing operations. First, the wet processing tool set 30 uses an electrochemical vapor deposition process to apply copper metallization to the interconnect line and post patterns formed by the pattern processing tool set 25. Includes the processing station used. For this purpose, the electrochemical deposition station 1
35 and 140 are provided. In addition, conditioning station 145 can be used to condition the surface of the semiconductor workpiece on which copper is to be electrochemically deposited. Second, the wet processing tool set 30 is used to remove one or more of the materials used to form the interconnect line and post patterns applied by the pattern processing tool 15. Includes further processing stations. A processing station 150 and washing / drying stations 155, 160 are provided for this purpose. Finally, it is used to remove portions of the seed layer and / or barrier layer that do not overlap the metallized interconnect lines, or to render such portions non-conductive. As described in more detail below, an oxidation station 165, an etching station 170, and an electrochemical removal station 175 may be used for such seed layer, barrier layer processing. Oxidation station 165 and etching station 170 may be combined into a single processing station.

Optionally, the processing tool 30 may be used to apply a protective coating over the interconnect line metallization and post metallization. In the illustrated embodiment, an electrochemical deposition station 180 may be used for this purpose.
The material for the protective coating is preferably a material that prevents both migration of the copper into the dielectric and oxidation of the coated copper. For example, materials that can be used for protective coatings include nickel, nickel alloys, and chromium.

The dielectric processing tool set 35 includes a plurality of processing stations used to deposit a dielectric layer over the interconnect line metallization and post metallization. Moreover, the dielectric processing tool set 35 includes one or more processing stations for etching the deposited dielectric layer to expose the upper connection area of the post metallization. In the illustrated embodiment, the dielectric processing tool set 35 includes an input station 185 adapted to house the semiconductor workpiece in a multi-workpiece cassette or single-workpiece or multi-workpiece clean pod. I do. Semiconductor workpieces are sent from input station 185 to coating station 190, where the surface of each semiconductor workpiece is coated with a dielectric precursor or the like. The workpiece is
After being coated, it is subsequently sent to the bake station 195 and cure station 200 to complete the formation of the dielectric surrounding the interconnect line metallization and post metallization. The semiconductor workpiece is then sent to an etch back station 205, where the upper surface of the dielectric layer is etched back, exposing the upper connection area of the post metallization.

Referring again to FIG. 3, separate input and output stations 40, 62 for tool set 20 may optionally be integrated into a single input / output station. Similarly, optionally, separate input / output stations 65, 110 of tool set 25 are integrated into a single input / output station, and single input / output station 115 of tool set 30 is separated into separate input / output stations May be divided. One or more cassettes or pods may be present in the I / O station at any one time. Separate input and output stations 185, 210 for tool set 35 may also optionally be integrated into a single input / output station.

Referring to FIG. 6, the processing tool set described in connection with FIG. 3 can be used to implement a manufacturing process procedure described below in connection with FIG. The number of workpiece movements between sets can be minimized. The process steps 215, 225, 237, 260 of FIG.
0. Process steps 270 and 300 may be implemented in pattern processing tool set 25. Process steps 280, 290 and 308
380 may be implemented in the wet processing tool set 30. Process stage 4
Steps 00 to 425 are performed in the dielectric processing tool set 35.

As a result of the use of each processing stage and the distribution of the processing stages between the various tool sets,
A single interconnect metallization level with only 10 and preferably 5 workpiece movements, significantly less than the 13 work-to-tool set movements required for the dual damascene method described above Can also be formed. For this purpose,
Transferring the workpiece between the film deposition tool set 20 and the pattern processing tool set 25 employs a one-time movement of the workpiece as indicated by arrow 500 in FIG. To transfer the workpiece between the pattern processing tool set 25 and the wet processing tool set 30, three workpiece movements indicated by arrows 505, 510 and 515 are employed. Wet processing tool set 30 and dielectric processing tool set 3
In order to transfer the work piece to and from the work piece 5, only one movement of the work piece, indicated by arrow 520, is employed. Thus, when compared to the traditional dual damascene method and tool architecture of FIGS. 1 and 2, the number of workpiece movements between tool sets is greatly reduced.

One embodiment of the basic method employed to form the disclosed metallization structure to minimize the number of movements of the workpiece between the tool sets is shown in the flowchart of FIG. The corresponding formation of one embodiment of a metallization structure in various processing states is shown in FIGS. Figures 4 and 5A
As shown, a dielectric layer 210 is provided on a substrate such as a semiconductor wafer.
Although not specifically shown in FIG. 5A, the dielectric layer 210 is exposed to the top of the dielectric layer in an already planarized state and provides electrical contact between one or more components below the planarized surface of the dielectric layer. It often includes contacts with metal-filled vias that provide a secure connection.
This one or more components below the planarized surface of the dielectric layer may also form another interconnect metallization level that provides a direct connection to semiconductor components formed in the substrate or the like. The dielectric layer 210 preferably has a dielectric constant of less than 4, spin or spray apply one or more precursors, and then cure in an anaerobic or oxygen containing atmosphere at a temperature below 450 ° C. It can also be formed by performing. The preferred dielectric material is benzocyclobutene (BCB).

Preferably, the surface of the dielectric layer 210 is conditioned as in step 215 to increase the adhesion of the subsequently applied layers. The surface of the dielectric layer 210 can be conditioned by a wet or dry chemical method or an ion milling method. FIG. 5A
Arrow 220 indicates the conditioning of the upper surface of dielectric layer 210 by bombarding, for example, argon or nitrogen ions. Alternatively, the top surface can be conditioned by short-time (10-30 seconds) etching in a 1% to 2% aqueous solution of hydrofluoric acid in deionized water.

As shown in FIG. 5, and further, as in step 225 of FIG. 4, an optional bonding layer 230 may be applied to the surface of the dielectric layer 210. This bonding layer 230 may be aluminum, titanium or chromium deposited by a deposition technique such as PVD, as described above.

In step 237 of FIG. 4, a barrier layer 240 is applied over the bonding layer, if used, or directly on the surface of the dielectric layer 210. Barrier layer 240 is applied to the generally planar surface of the semiconductor workpiece, as shown, thereby eliminating the need to apply barrier layer 240 in high aspect ratio trenches and vias. Depending on the properties of other materials incorporated within the interconnect structure, the barrier layer 240
Can be tantalum, tantalum nitride, titanium nitride, titanium oxynitride, titanium-tungsten alloy or tungsten nitride. As described above, as contacts to semiconductor device contacts, two such as those taught by Stevens in U.S. Pat. Nos. 4,977,440 and 5,070,036.
A composite barrier consisting of two layers can also be used. It is noted that the deposited bonding layer is not required to achieve good adhesion between the titanium barrier layer and the properly conditioned BCB layer of the dielectric layer. The barrier layer 240 may also be provided with sufficient conductivity to facilitate a subsequent electrochemical deposition step for depositing interconnect lines and post metallization. However, if the barrier layer 2
If the conductivity of 40 is insufficient, a seed layer may be required.

5B and step 260 in FIG. 4 show the application of a seed layer 265 deposited, for example, by PVD or CVD. Seed layer 265 is typically copper, but could be a metal such as nickel, iridium, platinum, palladium, chromium, vanadium, or other conductive materials such as iridium oxide. The preferred thickness of the seed layer and the barrier layer is in the range of 200-600 °.

Referring again to FIG. 5B and step 270 of FIG. 4, employ well-established procedures in photolithography, for example, to deposit an interconnect line pattern using photoresist 272 as a mask. You can also. In such cases, the plasma may be removed as a final step in a photolithographic procedure or in any processing step prior to electrochemical deposition of interconnect line metallization to remove photoresist residues from exposed portions of the seed layer surface. Processing can also be included. To form a layer 270 that promotes the adhesion between the photoresist and the copper seed layer 265, H
Processing in MDS can also be adopted. Additionally or alternatively, layer 27
0 to thereby promote adhesion between the seed layer and the photoresist.
A thin layer of copper oxide (less than 100 °) can also be formed on the top surface of seed layer 265.

According to FIG. 5C and step 280 of FIG. 4, an interconnect line metallization is formed, for example, by selectively electrochemically depositing copper into the photoresist interconnect pattern. Preferably, an acidic electrochemical bath is employed for electrochemical deposition. This chemical bath can be prepared by adding copper sulfate and sulfuric acid to deionized water. As is known in the metal plating art, materials that affect metal particle size and film compatibility can also be included in the chemical bath at low concentrations.

After the interconnect metallization 285 has been deposited on the photoresist interconnect pattern, the photoresist is removed. Removal of the photoresist can also be accomplished by exposing the photoresist to a solvent or an oxidizing agent (such as ozonized deionized water), followed by a water rinse. These steps correspond to steps 290 and 2 in FIG.
At 95, this step must be sufficient to remove the photoresist after selective metal deposition. The resulting structure is shown in FIG. 5D.

As shown in FIG. 5E and step 400 of FIG. 4, another photoresist pattern 305 is formed to form an opening for electrochemically depositing post-metallization 307 as in step 308. Applies to semiconductor workpieces. The metallized post 307 is shown in FIG. 5F. After the post metallization has been deposited, the photoresist pattern is removed, thereby leaving the interconnect structure of FIG. 5G.

Next, according to steps 315, 320 and 325 of FIGS. 5H and 4, part or all of the seed layer 265 is removed, for example, by an electrochemical etching method. Electrochemical etching can also be performed by exposing the seed layer to a suitable electrolyte, such as a solution containing phosphoric acid, while the seed layer 265 is maintained at a positive potential with respect to the electrode immersed in the electrolyte. Dripping.

FIG. 5H shows a representative cross section after partial removal of the exposed seed layer,
Thereafter, copper tantalum oxide is formed on the exposed surface of the barrier layer, and copper oxide is formed on the lines and posts. As already detailed, the seed layer 265
Can be partially removed by immersion in an electrolyte containing phosphoric acid, while the seed layer is kept at a positive potential with respect to the electrodes immersed in the same electrolyte. The seed layer remaining after the electrochemical etching is converted to copper oxide. Alternatively, if the thickness of the seed layer is less than about 10% of the minimum line width, the electrochemical etching can be omitted and the seed layer can be entirely converted to copper oxide.

According to step 320, the exposed surfaces of the copper structures 285, 307 and 265 and the barrier layer 240 are oxidized by exposure to a solution of air, oxygen, dissolved oxygen-containing water or dissolved ozone in water. Alternatively, the exposed surface can be oxidized by heating in an oxygen-containing atmosphere. As shown in step 325, the resulting copper oxide can also be removed by exposure to sulfuric acid, hydrochloric acid, or a solution containing both sulfuric acid and hydrochloric acid. According to FIG. 3, removal of copper oxide is performed by tool set 2
5 station 145.

A protective coating 370 is preferably provided over the remaining interconnect structure. Such a protective coating, as in step 375, is preferably formed by a metal chemistry method that deposits the material on the exposed copper but not on the oxide-coated exposed barrier material. The protective coating material is preferably a material that prevents migration of copper to the dielectric and also prevents oxidation of the coated copper. Such materials are nickel, nickel alloys and chromium. The preferred thickness of the protective coating ranges from 50 ° to 500 °. The resulting structure is shown in FIG.
I.

According to step 380 of FIG. 4, the barrier layer 240 and the oxide layer thereon may be removed by a wet chemical etchant if not covered by copper. If the barrier removal procedure is performed on the copper function of the interconnect structure or dielectric 21 underlying the barrier layer 240
The wet chemical etchant can be a 1% to 5% aqueous solution of hydrofluoric acid, provided that it does not cause excessive destructive chemistry to zero.

As shown in FIG. 5J, and as in steps 400 and 405 of FIG. 4, another dielectric layer 4 is formed to a thickness sufficient to cover the top surface of the posts of the interconnect structure.
Form 10 This additional dielectric layer 410 is preferably formed by spinning or spraying one or several precursors, followed by curing in an anaerobic or oxygen containing atmosphere at a temperature below 450 ° C. Dielectric layer 4
The composition of 10 may be different from or the same as that of the dielectric layer 210.

After another dielectric layer 410 is cured, the exposed surface of layer 410 is etched back to expose upper contact area 420 of post structure 307. For example, a blanket plasma etch may be employed to reduce the thickness of layer 410 until all of the upper surface of post structure 307 is exposed. BCB etching is
For example, it can be performed in a plasma containing oxygen and fluorine ions. Such a step is shown in FIG. 4 at step 425 and the resulting structure is shown in FIG. 5K.

Another embodiment of a tool architecture suitable for performing the above steps is shown in FIG.
It is shown in The tool architecture shown in FIG. 7 is similar to the embodiment of the toolset shown in FIG. 3 as being incorporated into the tool architecture of FIG. 6 (except for the more general processing toolset of FIG. 6). It will be appreciated that the names could be used in FIG. 7 as well, without incorporating the toolset disclosed in FIG. 3). However, the tool architecture of FIG. 7 includes a set of inspection tools used to check semiconductor workpieces in the middle of a single metallization level application. The intermediate check is performed, for example, in order to ensure proper registration of various photoresist patterns and corresponding metallization, and to perform proper dielectric etchback. Thus, FIG.
After each of the processing steps 270, 290, 300, 380 and 425 shown in FIG. In the illustrated embodiment, the semiconductor workpiece is transported between the various tools of the tool processing architecture and the workpiece is moved ten times to form a single interconnect metallization level. The inspection tool set 600 can also be configured by, for example, an inspection device available from KLA-Tencor. Tool Architecture and Method Using Hard Mask Patterning At least four embodiments of a method of fabricating metallization levels using hard mask patterning are disclosed. In a first embodiment, a hard mask dielectric layer is used to form only the interconnect metallization pattern. In a second embodiment, a hard mask dielectric layer is used to form both interconnect metallization patterns and post patterns. The third and fourth embodiments are the first and second embodiments, respectively, except that an intermediate inspection is performed during processing to ensure proper formation of interconnect lines and post patterns. Is similar to The processing architecture, processing tool set, and workpiece movement are shown for each embodiment. The basic toolset for implementing a processing architecture according to one embodiment of the present invention is shown in FIG. As shown, the toolset
Film deposition tool set 1020, hard mask forming tool set 1023, pattern processing tool set 1025, and electrochemical / wet processing tool set 1030
And a dielectric processing tool set 1035.

In the disclosed embodiment of FIG. 8, the film deposition set 1020 is preferably a vacuum deposition tool set. As will become apparent from the following discussion of processing operations performed on a workpiece, the film deposition tool set 1020 deposits one or more films on a generally flat surface of a workpiece. Such film deposition is suitable for depositing a film in a fine concave portion used for damascene processing. Thus, low-cost vacuum deposition techniques, such as physical vapor deposition (PVD), may be employed. Chemical vapor deposition (CVD) may also be employed.

The embodiment of the film deposition tool set 1020 shown in FIG. 9 is used to condition a surface of a workpiece, deposit a bonding layer, deposit a barrier layer, and deposit a seed layer on the workpiece. Processing station. Preferably, the workpiece is first transferred to a conditioning station where the surface of the generally planar dielectric layer deposited on the outside of the workpiece substrate is treated to increase the adhesion of subsequent film layers. Such enhanced adhesion of the dielectric layer can be achieved through the use of any one or more known plasma techniques. Depending on the properties of the dielectric layer and subsequent film layers, adhesion enhancement may not be necessary.
In such cases, the conditioning station need not be included in the film deposition tool set 20. Each workpiece is then provided to a bonding film application station where an optional bonding layer is applied (preferably directly) outside the dielectric layer. Suitable materials for the bonding layer are aluminum, titanium and chromium. Depending on the properties of adjacent film layers, a bonding layer may not be desired, in which case a bonding film application station need not be included in the film deposition tool set 1020. A barrier layer application station is used to apply the barrier layer material outside the dielectric material of the workpiece. The barrier layer can be tantalum, tantalum nitride, titanium nitride, titanium oxynitride, titanium-tungsten alloy, or tungsten nitride, depending on the properties of the other materials incorporated within the interconnect structure.
Particularly when the interconnect level is in contact with the terminals of the semiconductor device, a two layer composite as taught by Stevens in U.S. Pat. No. 4,977,440 and U.S. Pat. No. 5,070,036. Advantageously, barriers are employed.

The film deposition tool set 1020 preferably includes a seed layer application station to increase the conductivity of the barrier layer and to properly adhere subsequently formed layers. The seed layer application station deposits the seed layer, preferably using a PVD or CVD method. The seed layer is preferably copper. After the seed layer has been applied,
The workpiece is transferred to an output station and then further to another set of processing tools.

The hard mask forming tool set 1023 includes a film deposition processing tool set 1020.
Including a plurality of processing stations used to provide a hard mask dielectric layer over the seed layer applied by the method. This hardmask dielectric layer is ultimately patterned according to the photoresist pattern applied by the patterning tool set 1025. One or more hardmask layers are applied to provide a patterned mask used to deposit one or both of the interconnect line metallization and post metallization. As will be shown in more detail below, the interconnect line pattern forms an area in which conductor paths are provided for horizontal electrical interconnection in the plane of the workpiece, while the post pattern is adjacent to the workpiece. Forming areas in which conductor paths are provided for vertical electrical connections between the two planes.

In the tool set embodiment shown in FIG. 10, the hard mask forming tool set 10
23 includes an input station 1465 for receiving a workpiece, preferably in a multi-workpiece cassette or a single-workpiece cassette or a multi-workpiece sanitary pod. From the input station 1465, the workpiece is provided to a coating station 1467, where the workpiece is coated with one or more precursor materials. The workpiece is then provided to a baking station 1470, for example, to burn off the solvent. The baking station is typically a hot plate. After processing at the baking station 1470, the workpiece is provided to a curing station 1473.
Depending on the length of the cure cycle, the cure station 1473 can be a hot plate or a small batch furnace. The curing cycle must not damage the workpiece. After curing, the workpiece is provided to output station 1475. In the illustrated embodiment, the input station and the output station are shown separately, but these stations can be combined into a single input / output station.

The pattern processing tool set 1025 of FIG. 8 includes a plurality of processing stations used to provide interconnect line patterns on the hard mask layer applied by the hard mask forming tool set 1023. One of the disclosed methods
Accordingly, the pattern processing toolset 1025 is also used to provide post patterns on interconnect metallizations formed using interconnect line patterns. Alternatively, as shown below, a pattern processing tool set 1025 may be used to provide a post pattern on another hard mask layer deposited by a hard mask forming tool set that provides a mask for post metallization deposition. used.

In the embodiment of the tool set shown in FIG. 9, the pattern processing tool set 1025
Is a photoengraving tool set. The pattern processing tool set 1025 then includes an input station for receiving a workpiece, such as a semiconductor wafer, into a multi-workpiece cassette or a single-workpiece cassette or a multi-workpiece sanitary pod. Inside the tool set 1025, the workpiece is continuously subjected to standard photomechanical processes of conditioning, coating and baking. After the photoresist has been baked onto the workpiece, the workpiece selectively affects the photoresist so that portions of the photoresist layer can be subsequently removed to form interconnect lines or post patterns. The photoresist is then transferred to an input station of a photoresist exposure device, such as a step repeat device, which exposes the photoresist to ultraviolet light. After exposure of the photoresist layer, the workpiece is sent to the output station, and a photoresist layer is selected to form a pattern in the photoresist layer that is compatible with pattern exposure in the photoresist exposure apparatus. Transferred to another processing station where it is removed. Such processing stations include a photoresist development station, and may also include a plasma cleaning ("descum") station. After selective removal of the photoresist layer and plasma cleaning, the workpiece is transferred to an output station and further provided to one or more additional tool sets.

As shown in FIG. 9, the hard mask etching tool set 1027 includes an input station 1480 for receiving a workpiece, preferably in a multi-workpiece cassette or a single-workpiece cassette or a multi-workpiece sanitary pod. I have. Input station 1
From 480, the workpiece is provided to an etching station 1483, where the hard mask layer is selectively etched through open areas of the patterned photoresist layer applied by the patterning tool set 1025. After the hard mask layer has been etched to form the desired mask pattern, the workpiece is provided to output station 1485. Although the input and output stations are shown separately in the embodiment shown in FIG. 10, a single input and output station may be used. Hard mask etching tool set 1027 is available from Tegal, Applied Material, or LAM
A plasma etching apparatus such as that sold by ach may be used.

The electrochemical and wet processing toolset 1030 of FIG. 8 implements a wide range of processes used to form interconnect line metallization and post-metallization structures. The wet processing tool set 1030 can also be implemented in the form of Equinox ^™ brand tools or LT-210 ^™ brand tools, both available from Semitool, Kalispell, MT. FIG.
As shown in Table 1, such an electrochemical and wet processing tool set preferably includes an input station, an output station, and a plurality of stations for performing electrochemical and wet chemical methods. The processing stations of the wet processing tool set 30 perform at least three primary processing operations. First, the wet processing tool set 30
Applies copper metallization, using electrochemical deposition, into interconnect line patterns and post patterns formed using pattern processing tool set 25 and / or hard mask etching tool set 1027. Includes processing station used for In addition, a conditioning station can be used to condition the surface of the workpiece on which the copper is to be electrochemically deposited. Second, the tool set 30 is a hard mask forming tool set 1
023, and is used to remove the hard mask material used to form the interconnect line pattern and, in some embodiments, the post pattern, etched by the hard mask etching tool set 1027. It includes one or more processing stations. Similarly, wet processing tool set 3
0 removes the photoresist material employed to form the interconnect line pattern in the hard mask layer and, in some processing embodiments, the photoresist material employed to form the post pattern. It includes one or more processing stations used for processing. Generally, a solvent station and a rinse / dry station are provided for photoresist removal. Finally, one or more processing stations are employed to remove portions of the seed and / or barrier layers where the interconnect lines do not overlap and / or to render such portions non-conductive. ing.

Optionally, the processing tool 30 can be used to apply a protective coating over the interconnect metallization and the post metallization. In one particular implementation, an electrochemical vapor deposition station may be used for this purpose. The protective coating material is preferably a material that prevents both migration of the copper to the dielectric and oxidation of the coated copper. Materials that can be employed for the protective coating are nickel, nickel alloys and chromium.

The dielectric processing tool set 1035 includes a plurality of processing stations used to form a dielectric layer over interconnect metallization and post metallization. In addition, to expose the upper connection area of the post-metallization, the dielectric processing tool set 1035 includes one or more processing stations for etching the deposited dielectric layer. For the embodiment of the dielectric processing tool set shown in FIG. 9, a workpiece is provided from an input station to a coating station where the surface of each workpiece is coated with a dielectric precursor or the like. After being coated, the workpiece is continuously fed to a bake station and a cure station to complete the formation of the dielectric material surrounding the interconnect metallization and post metallization. The workpiece is then provided to an etchback station, where the upper surface of the dielectric layer is etched back, exposing the upper connection areas of the post-metallization.

Referring to FIG. 8, a processing tool set can also be used to implement the manufacturing process procedures described below in connection with FIG. 11 with a minimum number of workpiece movements between the tool sets. . Processing steps 1215, 1225, 1237 and 1 in FIG.
260 can also be implemented within the film deposition tool set 1020. Processing stage 12
70 and 1308 may also be implemented within the pattern processing tool set 1025. Processing steps 1277, 1280 and 1039-1380 may also be performed within wet processing tool set 1030. Processing steps 1400-1425 are performed within dielectric processing tool set 1035. Processing step 1261 may be performed in hard mask forming tool set 1023, and processing step 1273 may be performed in hard mask etching tool set 1027.

As a result of the use of each processing stage and the distribution of the processing stages among the various tool sets,
If a hard mask is used to pattern only the interconnect lines, a single interconnect metallization level can also be formed with only seven movements of the workpiece between the tool sets. If a hard mask is used to pattern both the interconnect lines and the posts, only 9 as shown in FIG.
A single interconnect metallization level may be created by multiple workpiece movements between the tool sets.

For this purpose, the transfer of the workpiece between the film deposition tool set 1020 and the hard mask forming tool set 1023 requires only a one-time workpiece transfer indicated by arrow 1500 in FIG. Movement is used. Hard mask forming tool set 10
A one-time movement of the workpiece, indicated by arrow 1505, is used to transfer the workpiece between 23 and the pattern processing tool set 1025. Two workpiece movements 1510 and 1512 are used to transfer the workpiece between the pattern processing tool set 1025 and the wet processing tool set 1030. A one-time workpiece transfer 1515 is used to transfer the workpiece between the pattern processing tool set 1025 and the hard mask etching tool set 1027.
Similarly, a one-time workpiece transfer 1515 is used to transfer the workpiece between the hard mask etching tool set 1027 and the wet processing tool set 1030. Finally, the wet processing tool set 1030 and the dielectric processing tool set 1
A one-time work transfer 1520 is used to transfer the work piece to and from 035. Thus, when compared to the traditional dual damascene processing architecture and tool configuration of FIGS. 1 and 2, the number of movements of the workpiece between the tool sets is greatly reduced.

In step 1261 of FIG. 11, a hard mask dielectric layer 1263 is deposited on the seed layer 1265 in the hard mask forming tool set 1023. Step 1 in FIG.
At 270, well established procedures in photolithography may be employed, for example, to deposit an interconnect line pattern on a hardmask dielectric layer using photoresist as an intermediate mask. Hard mask dielectric layer 1263 is selectively etched through open portions of photoresist layer 1272 as indicated by 1273. Step 1273 is performed at a hard mask etching station 1027. With respect to step 1277 of FIG. 11, the photoresist layer 1272 is removed at a wet chemical processing station in the tool set 1030, thereby forming a patterned hard with substantially vertical walls for forming an interconnect metallization pattern. The mask dielectric layer 1263 will be left.

With respect to step 1280 of FIG. 11, an interconnect line metallization is formed, for example, by selectively electrochemically depositing copper into the hard mask interconnect pattern. Preferably, an acidic electrochemical bath is employed for electrochemical deposition. This chemical bath can be prepared by adding copper sulfate and sulfuric acid to deionized water. Materials that affect metal grain size and film compatibility can optionally be included in the chemical bath at low concentrations, as is known in the metal plating art.

The resulting structure after electrochemical deposition of copper is shown in FIG. In FIG. 12, the generally flat surface of the workpiece is shown at 1210, the conditioned portion of the workpiece is shown at 1230, the barrier layer is shown at 1240, and the hard mark layer is shown at 1210.
At 63, the seed layer is shown at 1265, and an exemplary interconnect metallization line is shown at 1285 in cross section.

After the interconnect metallization has been deposited in the patterned hardmask dielectric layer, the workpiece can also be returned to the patterning tool set 1025, where:
For example, a pattern for post-metallization is formed using a photoresist layer applied and patterned by conventional photoresist patterning techniques. In step 1308, the additional photoresist pattern is applied to the workpiece to form openings for electrochemically depositing the post-metallization. FIG. 13 shows the structure that results after patterning of the photoresist layer 1305 and electrochemical deposition of the post metallization 1307 in step 1309 of FIG.

After the post metallization has been deposited in step 1309, the photoresist pattern is removed in step 1310 and the hard mask dielectric layer is removed in step 1310.
Remove at 13. Removal of the hardmask dielectric layer is preferably performed by tool set 1
030, but can also be performed in the hard mask etching tool set 1027 with the addition of two additional wafer movements.

The hard mask dielectric layer 1263 can be removed before forming the patterned photoresist layer. FIG. 14 shows the structure that results after the patterning of the photoresist layer 1305 and the electrochemical deposition of the post-metallization 1307. To form a layer that promotes adhesion between the photoresist and the copper seed layer 265, the HM
Processing in DS can also be adopted. Additionally or alternatively, a thin layer of copper oxide (less than 100 °) may be formed on the top surface of the seed layer 1265, thereby promoting adhesion between the seed layer and the photoresist.

Next, according to steps 1315, 1320 and 1325 of FIGS. 5H and 4, for example,
Part or all of the seed layer 265 is removed by an electrochemical etching method. Electrochemical etching can also be performed by exposing the seed layer to a suitable electrolyte, such as a solution containing phosphoric acid, while the seed layer 1265 is maintained at a positive potential with respect to the electrode immersed in the electrolyte. Dripping.

In step 1320, the exposed surfaces of copper structures 1285, 1307, and 1265 and barrier layer 1240 are oxidized by exposure to dissolved air, oxygen, or water containing ozone. Alternatively, the exposed surface can be oxidized by heating in an oxygen-containing atmosphere. As shown in step 1325, the resulting copper oxide may also be removed by exposure to sulfuric acid, hydrochloric acid, or a solution containing both sulfuric acid and hydrochloric acid. According to FIG. 3, the removal of copper oxide is performed by the tool set 30.
At the etching station 145 of FIG.

A protective coating 370 is preferably provided over the remaining interconnect structure. Such a protective coating, as in step 1375, is preferably formed by a metal chemistry method that deposits the material on exposed copper but not on the oxide coated exposed barrier material. The protective coating material is preferably a material that prevents migration of copper to the dielectric and also prevents oxidation of the coated copper.
Such materials are nickel, nickel alloys and chromium. The preferred thickness of the protective coating ranges from 50 ° to 500 °.

According to step 1380 of FIG. 11, the barrier layer 1240 and the oxide layer thereon may be removed by a wet chemical etchant if not covered by copper. If the barrier removal procedure does not cause excessive destructive chemistry to the copper function of the interconnect structure or the dielectric 1210 underneath the barrier layer 1240, the wet chemical etchant may be 1% to 5% hydrofluoric acid. % Aqueous solution.

In step 1400 of FIG. 11, another dielectric layer is formed to a thickness sufficient to cover the top surface of the interconnect structure post. This additional dielectric layer is preferably formed by spinning or spraying one or several precursors, followed by curing in an anaerobic or oxygen-containing atmosphere at a temperature below 450 ° C. The composition of the dielectric layer may be different from or the same as the composition of the dielectric layer 1210.

After the additional dielectric layer has cured, the exposed surface of the layer is etched back to expose the upper contact area 420 of the post structure 1307. For example, the post structure 130
A blanket plasma etch can also be employed to reduce the thickness of the layer until all upper surfaces of 7 are exposed. The etching of BCB can be performed, for example, in a plasma containing oxygen and fluorine ions.

In some cases, it may be desirable to use a hard mask for patterning the posts and interconnect lines. One embodiment of the use of a hard mask for patterning post structures is illustrated in FIG. The corresponding movement of the wafer between the tool sets is shown in FIG.

In this embodiment, the processing of the workpiece is almost the same as the processing shown in FIG. The main difference in terms of processing is after the electrochemical deposition stage 1280. In this latter embodiment, the workpiece is removed from the wet processing tool set 1030 and returned to the hard mask forming tool set 1023, where the workpiece is removed as shown in step 1427 of FIG.
Another hard mask dielectric layer 1422 (FIG. 17) is deposited on the surface of the workpiece. After the formation of this additional hardmask dielectric layer, the workpiece is transferred to the patterning tool set 102.
5, where, for example, another photoresist layer 1432 is deposited on this another hardmask dielectric layer 1422 and patterned, as in step 1249, according to the desired post-metallization pattern. In step 1443, a hard mask dielectric layer 1422 is formed to form openings for forming post structures therein.
Is etched according to this pattern. The workpiece is then returned to the wet chemical processing tool set 1030, where the photoresist layer 1432 is stripped in step 1310 and the copper post structure is electrochemically deposited in step 1309 through the hard mask dielectric layer 1422. Referring to FIG. 18, after deposition of the post-metallization, the hard mask layer is removed and processing proceeds in the same manner as shown in connection with FIG. As shown in FIG. 16, nine movements of the wafer between the illustrated tool sets can form an entire metallization level.

A further enhancement of each of the above methods and toolset wafer movements is shown in FIG.
9 and 20. The tool configurations of FIGS. 19 and 20 each include a set of inspection tools used to check the workpiece in the middle of applying a single metallization level. Intermediate checks are performed, for example, to ensure proper registration of various photoresist patterns and / or hard mask patterns with corresponding metallization, and to perform proper dielectric etchback. As shown in FIG. 19, processing steps 1270, 1270 shown in FIG.
After 290, 1300, 1380 and 1425, each workpiece may also be provided to the inspection tool set 1600. Similarly, as shown in FIG. 20, each workpiece may be provided to the inspection tool set 1600 after the processing steps 1270, 1290, 1300, 1380, and 1425 shown in FIG. In the embodiment shown in FIG. 19, the workpiece is transferred between various tools of the tool processing architecture,
Workpiece is moved 12 times to form a single interconnect metallization level. In the embodiment shown in FIG. 15, the workpiece is moved 14 times to transfer the workpiece between the various tools of the tool processing architecture and to form a single interconnect metallization level. The inspection tool set 600 is, for example, a KLA
-It can also be constituted by an inspection device available from Tencor.

Many modifications can be made without violating the basic teachings of the system described above. While the invention has been described with respect to one or more specific embodiments, those skilled in the art will recognize that changes may be made without departing from the scope and spirit of the invention as set forth in the appended claims.

[Brief description of the drawings]

FIG. 1 is a process flow chart illustrating one method of implementing a double-wave pattern interconnect architecture.

FIG. 2 shows a tool set for implementing the process shown in FIG.
Figure 2 illustrates an architecture and corresponding workpiece movement.

FIG. 3 illustrates one method of configuring a tool set for the tool set architecture of the present invention.

FIG. 4 is a process flow chart illustrating one method of achieving an interconnect metallization structure with a minimum number of workpiece movements between the tool sets of FIG. 3;

5A-5K show interconnect metallization structures formed using the process of FIG. 4 at various metallization level generation stages.

FIG. 6 shows a tool set for implementing the process shown in FIG.
Figure 2 illustrates an architecture and corresponding workpiece movement.

FIG. 7 shows a tool set for implementing the process shown in FIG.
FIG. 4 shows the architecture and the corresponding workpiece movement,
FIG. 3 is a diagram illustrating a state where a semiconductor workpiece is being inspected at an intermediate stage of a metal coating process using a set.

FIG. 8 illustrates one method of constructing a tool set for implementing another process architecture of the present invention that uses a hard mask for interconnect patterning.

9 and 10 show a special embodiment of a tool set that can be used in the tool set structure of FIG.

FIG. 11 is a process flowchart illustrating one method of forming an interconnect metallization structure while minimizing the number of workpiece movements between the tool sets shown in FIG.

FIGS. 12 to 14 show a selection stage for metal coating generation in FIG.
2 shows an interconnect metallization structure formed using the process of FIG.

FIG. 15 is a process flowchart illustrating yet another method of minimizing the number of workpiece movements and implementing an interconnect metallization structure using hardmask patterning.

FIG. 16 shows a tool set structure and corresponding workpiece movement for performing the process shown in FIG.

FIG. 17 illustrates an interconnect metallization structure formed using the process of FIG. 15 at selected stages of metallization generation.

FIG. 18 illustrates an interconnect metallization structure formed using the process of FIG. 15 at a selected stage of metallization generation.

19 shows, respectively, a tool set structure and a corresponding workpiece movement for performing the process shown in each of FIGS. 11 and 15, using an inspection tool set to perform a metallization intermediate. It is a figure showing the state where a work piece is inspected in a stage.

FIG. 20 shows a tool set structure and corresponding workpiece movement, respectively, for performing the process shown in each of FIGS. 11 and 15, using an inspection tool set to perform a metallization process It is a figure showing the state where a work piece is inspected in a stage.

[Explanation of symbols]

 Reference Signs List 20 Film deposition tool set 25 Pattern processing tool set 30 Wet processing tool set 35 Dielectric processing tool set 40 Input station 45 Conditioning station 50 Bonding film application station 55 Barrier layer application station 60 Seed layer application station 62 Output station .

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number 09 / 128,238 (32) Priority date August 3, 1998 (August 1998) (33) Priority claim country United States (US) ( 81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), CN, JP, KR , SG F term (reference) 5F004 AA14 BD01 DA00 DA26 DB07 DB26 EA23 EB02 EB03 5F033 HH07 HH08 HH11 HH17 HH18 HH21 HH23 HH32 HH33 HH34 HH35 JJ07 JJ11 JJ17 KK07 KK11 KK11 KK18 KK11 KK18 PP27 QQ08 QQ09 QQ12 QQ19 QQ31 RR21 SS22 5F043 AA26 AA29 BB18 BB21 DD16 GG03

Claims (198)

[Claims] 1. A manufacturing tool arrangement for providing one or more interconnect metallization levels to a generally planar dielectric surface of a workpiece, wherein a barrier layer is deposited outside the planar dielectric surface. And a film deposition tool set for depositing a seed layer outside the barrier layer; providing an interconnect line pattern on the seed layer; and an interconnect line formed using the interconnect line pattern. A patterning tool set for providing a post pattern on the metallized portion, and at least the following wet processing operation, i.e., an electrochemical deposition process for the interconnect line pattern and the post pattern formed by the patterning tool set. To provide copper metallization and remove material deposited by the patterning toolset described above to provide interconnect line patterns and Forming a post pattern and removing portions of the seed and barrier layers not covered by the interconnect line metallization; a wet processing tool set for performing the operations of: A dielectric processing tool set for depositing a dielectric layer over the post metallization and etching the deposited dielectric layer to expose the upper connection area of the post metallization; Manufacturing tool characterized in that a single metallization level comprising interconnect line metallization, post metallization and dielectric layer is formed using less than 10 workpiece movements between tool sets. Construct. 2. The manufacturing tool arrangement according to claim 1, wherein the wet processing tool set includes at least one processing station for applying a protective coating that is electrochemically applied to the exterior of the copper metallization. . 3. The manufacturing tool according to claim 1, wherein the wet processing tool set includes at least one processing station for conditioning a surface of a workpiece prior to further processing within the wet processing tool set. Construct. 4. The manufacturing tool arrangement according to claim 1, wherein the wet processing tool set includes at least one processing station for oxidizing exposed metallized portions of the workpiece. 5. The manufacturing tool arrangement according to claim 4, wherein the wet processing tool set includes at least one processing station for removing oxidized metal portions of the workpiece. 6. The manufacturing tool arrangement according to claim 5, wherein the at least one processing station for removing oxidized metal parts is also used for conditioning a surface prior to subsequent processing. 7. The manufacturing tool assembly according to claim 1, wherein the film deposition tool set is a vacuum deposition tool set. 8. The manufacturing tool arrangement according to claim 1, wherein said film deposition tool set deposits a substantially flat bonding layer, and said barrier layer is deposited over said bonding layer by a film deposition tool set. . 9. The manufacturing tool arrangement according to claim 1, wherein said film deposition tool set deposits a substantially planar bonding layer directly on a dielectric layer. 10. The manufacturing tool structure according to claim 1, wherein the pattern processing tool set is a photoresist processing tool set. 11. The manufacturing tool arrangement according to claim 1, wherein said dielectric deposition tool set deposits low K dielectric material. 12. The manufacturing tool arrangement according to claim 1, wherein said film deposition tool set is a single integrated tool. 13. The manufacturing tool arrangement according to claim 1, wherein the pattern processing tool set is a single integrated tool. 14. The manufacturing tool arrangement according to claim 1, wherein said dielectric deposition tool set is a single integrated tool. 15. The manufacturing tool arrangement according to claim 1, further comprising an inspection tool set for inspecting a workpiece in one or more processing states during formation of a single metallization level. 16. The manufacturing tool arrangement according to claim 15, wherein the wet processing tool set includes at least one processing station for applying a protective coating that is electrochemically applied to the exterior of the copper metallization. . 17. The manufacturing tool according to claim 15, wherein the wet processing tool set includes at least one processing station for conditioning a surface of a workpiece prior to further processing within the wet processing tool set. Construct. 18. The manufacturing tool arrangement according to claim 15, wherein the wet processing tool set includes at least one processing station for oxidizing exposed metallized portions of the workpiece. 19. The manufacturing tool arrangement according to claim 18, wherein the wet processing tool set includes at least one processing station for removing oxidized metal portions of the workpiece. 20. At least one processing station for said oxidation;
At least one processing station for removing oxidized metal parts;
20. The manufacturing tool arrangement of claim 19, being the same processing station. 21. The manufacturing tool assembly according to claim 15, wherein the film deposition tool set is a vacuum deposition tool set. 22. The production tool arrangement according to claim 15, wherein said film deposition tool set deposits a substantially planar bonding layer, and said barrier layer is deposited over said bonding layer by a film deposition tool set. . 23. The manufacturing tool arrangement of claim 15, wherein the film deposition tool set deposits a substantially planar bonding layer directly on a dielectric layer. 24. The manufacturing tool structure according to claim 15, wherein the pattern processing tool set is a photoresist processing tool set. 25. The manufacturing tool arrangement according to claim 15, wherein the dielectric deposition tool set deposits low K dielectric material. 26. The manufacturing tool arrangement according to claim 15, wherein the film deposition tool set is a single integrated tool. 27. The manufacturing tool arrangement according to claim 15, wherein the pattern processing tool set is a single integrated tool. 28. The manufacturing tool arrangement according to claim 15, wherein the dielectric deposition tool set is a single integrated tool. 29. The method of claim 15, wherein the inspection tool set inspects a workpiece to ensure proper alignment of an interconnect line pattern and a post pattern formed by the pattern processing tool set. Tool construct. 30. The manufacturing tool assembly of claim 15, wherein the inspection tool set inspects a workpiece to ensure proper dielectric etching by the dielectric processing tool set. 31. A manufacturing tool arrangement for providing one or more interconnect metallization levels on a generally planar dielectric surface of a workpiece, comprising: depositing a barrier layer outside the planar dielectric surface; And a film deposition tool set for depositing a seed layer outside the barrier layer; providing an interconnect line pattern on the seed layer; and interconnect line metallization formed using the interconnect line pattern. A patterning toolset for providing a post pattern on the portion, and at least the following wet processing operations: an interconnect line pattern and a post pattern formed by the patterning toolset, using an electrochemical deposition process. Providing copper metallization, removing material deposited by the patterning tool set, and providing interconnect line patterns and A wet processing toolset for performing the operations of forming a strike pattern and removing portions of the seed and barrier layers not covered by the interconnect line metallization; A dielectric processing tool set for depositing a dielectric layer over the post metallization and etching the deposited dielectric layer to expose the upper connection area of the post metallization; A manufacturing tool characterized in that a single metallization level comprising interconnect line metallization, post metallization and a dielectric layer is formed using no more than five workpiece movements between tool sets. Construct. 32. The manufacturing tool arrangement of claim 30, wherein the wet processing tool set includes at least one processing station for applying a protective coating that is electrochemically applied to an exterior of the copper metallization. . 33. The manufacturing tool according to claim 31, wherein the wet processing tool set includes at least one processing station for conditioning a surface of a workpiece prior to further processing in the wet processing tool set. Construct. 34. The manufacturing tool arrangement according to claim 31, wherein the wet processing tool set includes at least one processing station for oxidizing exposed metallized portions of the workpiece. 35. The manufacturing tool arrangement according to claim 34, wherein the wet processing tool set includes at least one processing station for removing oxidized metal portions of the workpiece. 36. The manufacturing tool arrangement according to claim 35, wherein the at least one processing station for removing oxidized metal parts is also used to condition a surface prior to subsequent processing. 37. The manufacturing tool assembly according to claim 31, wherein the film deposition tool set is a vacuum deposition tool set. 38. The production tool arrangement according to claim 31, wherein said film deposition tool set deposits a substantially flat bonding layer, and said barrier layer is deposited over said bonding layer by a film deposition tool set. . 39. The manufacturing tool arrangement according to claim 31, wherein the film deposition tool set deposits a substantially planar bonding layer directly on a dielectric layer. 40. The manufacturing tool structure according to claim 31, wherein the pattern processing tool set is a photoresist processing tool set. 41. The manufacturing tool arrangement according to claim 31, wherein the dielectric deposition tool set deposits low K dielectric material. 42. The manufacturing tool arrangement according to claim 31, wherein the film deposition tool set is a single integrated tool. 43. The manufacturing tool arrangement according to claim 31, wherein the pattern processing tool set is a single integrated tool. 44. The manufacturing tool arrangement according to claim 31, wherein the dielectric deposition tool set is a single integrated tool. 45. A fabrication structure for providing one or more interconnect metallization levels on a generally planar dielectric surface of a workpiece, comprising: depositing a barrier layer external to the planar dielectric surface; And first means for depositing a seed layer external to the barrier layer; providing an interconnect line pattern on the seed layer; and an interconnect line metallization formed using the interconnect line pattern. A second means for providing a post pattern thereon, and at least the following wet processing operation, namely the interconnect line pattern and the post pattern formed by said second means,
Providing a metallization of copper using an electrochemical deposition process to remove material deposited by the second means to form an interconnect line pattern and post pattern; Removing a portion of the uncovered seed and barrier layers, depositing a dielectric layer over the interconnect line metallization and post metallization; and Fourth means for etching the deposited dielectric layer to expose the upper connection area of the post-metallization portion, no more than 10 times between said first, second, third and fourth means. Using the workpiece movement of
A fabrication structure, wherein a single metallization level is formed comprising an interconnect line metallization, a post metallization and a dielectric layer. 46. The fabrication structure of claim 45, wherein said third means includes means for applying a protective coating that is electrochemically applied to the exterior of the copper metallization. 47. The manufacturing structure of claim 45, wherein said third means includes at least one processing station for conditioning a surface of a workpiece before further processing by said third means. 48. The manufacturing structure according to claim 45, wherein said third means includes at least one processing station for oxidizing exposed metallized portions of the workpiece. 49. The manufacturing structure according to claim 48, wherein said third means includes at least one processing station for removing oxidized metal portions of the workpiece. 50. The manufacturing component of claim 49, wherein said at least one processing station for removing oxidized metal portions is also used to condition a surface prior to subsequent processing. 51. A method comprising a single piece of interconnect line metallization, a post metallization and a dielectric layer using up to five workpiece movements between said first, second, third and fourth means. 46. The manufacturing structure of claim 45, wherein a single metallization level is formed. 52. The first means is a vacuum evaporation tool set.
3. The production structure according to claim 1. 53. The fabrication structure of claim 45, wherein said first means deposits a substantially planar bonding layer and said barrier layer is deposited on said bonding layer by said first means. 54. The fabrication structure of claim 45, wherein said first means applies a substantially planar bonding layer directly to the dielectric layer. 55. The manufacturing structure according to claim 45, wherein said second means is a photoresist processing tool set. 56. The fabrication structure of claim 45, wherein said fourth means deposits a low K dielectric material. 57. The fabrication structure of claim 45, further comprising: fifth means for inspecting the workpiece in one or more processing states during formation of the single metallization level. 58. The first means is a vacuum deposition tool set.
3. The production structure according to claim 1. 59. The fabrication structure of claim 51, wherein said first means deposits a substantially planar bonding layer, and said barrier layer is deposited on said bonding layer by said first means. 60. The manufacturing structure of claim 51, wherein said film deposition tool set deposits a substantially planar bonding layer directly on a dielectric layer. 61. The manufacturing structure according to claim 51, wherein said second means is a photoresist processing tool set. 62. The fabrication structure of claim 51, wherein said fourth means deposits a low K dielectric material. 63. The fabrication structure of claim 51, further comprising: fifth means for inspecting the workpiece in one or more processing states during formation of the single metallization level. 64. A manufacturing tool arrangement for providing one or more interconnect metallization levels on a generally planar dielectric surface of a workpiece, wherein a barrier layer is deposited outside the planar dielectric surface. A film deposition tool set for providing an interconnect line pattern external to the barrier layer, and pattern processing for providing a post pattern on the interconnect line metallization formed using the interconnect line pattern Providing a metallization of copper to the toolset and at least the following wet processing operations: an interconnect line pattern and a post pattern formed by the patterning toolset using an electrochemical deposition process; Removing material deposited by the tool set to form interconnect line patterns and post patterns; A wet processing toolset for performing the operation of removing portions of the barrier layer not covered by the line metallization, and depositing a dielectric layer over the interconnect line metallization and post metallization And a set of dielectric treatment tools for exposing the deposited dielectric layer to expose the upper connection area of the post metallization, wherein no more than 10 workpiece movements between said tool sets A manufacturing tool arrangement characterized in that a single metallization level comprising an interconnect line metallization, a post metallization and a dielectric layer is formed using the method. 65. A single metallization level comprising an interconnect line metallization, a post metallization and a dielectric layer using no more than five workpiece movements between the tool sets. Item 65. The processing tool structure according to Item 64. 66. A fabrication tool arrangement for providing one or more interconnect metallization levels on a generally planar dielectric surface of a workpiece, comprising: depositing a barrier layer outside the planar dielectric surface. A film deposition tool set for depositing a seed layer outside of the barrier layer; and providing an interconnect line pattern on the seed layer, and an interconnect line metal formed using the interconnect line pattern. A patterning toolset for providing a post pattern on the patterned portion, and at least the following wet processing operations: an interconnect line pattern and a post pattern formed by the patterning toolset using an electrochemical deposition process. To provide copper metallization, remove material deposited by the patterning tool set, Forming a post pattern and removing portions of the seed and barrier layers not covered by the interconnect line metallization; a wet processing tool set for performing the operations of: A dielectric processing tool set for depositing a dielectric layer over the post metallization and etching the deposited dielectric layer to expose the upper connection area of the post metallization; A manufacturing tool arrangement characterized in that a single metallization level comprising interconnect line metallization, post metallization and a dielectric layer is formed using a plurality of workpiece movements between tool sets. . 67. A method of forming one or more protected copper elements on a surface of a workpiece, depositing a barrier layer on the workpiece, depositing a seed layer on the barrier layer, selecting a seed layer. Electroplating one or more copper elements on the exposed portion, substantially removing the seed layer, rendering at least a portion of the surface of the barrier layer unplateable, and providing a protective layer on the surface of the one or more copper elements. Electroplating. 68. The method of claim 67, further comprising depositing a dielectric layer on at least a portion of the one or more copper devices. 69. The step of substantially removing the seed layer includes subjecting the seed layer to an electrolytic bath treatment while maintaining the seed layer at a positive potential with respect to an electrode immersed in an electrolytic bath containing phosphoric acid. 68. The method of claim 67, comprising the steps. 70. Deposit a dielectric layer to substantially cover one or more copper elements, and remove a surface portion of the dielectric layer to remove one or more of the one or more copper elements. 68. The method of claim 67, further comprising: exposing a region. 71. The method of claim 67, wherein said step of rendering at least a portion of the surface of the barrier layer non-plateable comprises oxidizing an exposed surface of the barrier layer material. 72. Electroplating one or more copper elements on selected portions of the seed layer; electroplating one or more copper wires on selected portions of the seed layer; 68. The method of claim 67, comprising: electroplating one or more copper posts on selected portions of the lines. 73. The step of rendering at least a portion of the surface of the barrier layer unplatable comprises simultaneously oxidizing the exposed surface of the barrier layer material and the one or more copper elements, and removing the resulting copper oxide. 68. The method of claim 67, comprising removing from one or more copper devices. 74. The step of substantially removing the seed layer is performed simultaneously during the step of removing the resulting copper oxide layer from one or more copper devices.
3. The method according to 3. 75. Electroplating one or more copper elements on a selected portion of the seed layer; electroplating one or more copper lines on the selected portion of the seed layer; 74. The method of claim 73, comprising: electroplating one or more copper posts on selected portions of the. 76. The method of claim 67, further comprising removing the barrier layer after electroplating the protective layer. 77. The method of claim 67, wherein the barrier layer and the seed layer are deposited with a first set of processing tools. 78. The method of claim 77, wherein said electroplating and said non-plating steps are performed on a second processing toolset. 79. The method of claim 78, wherein the first processing toolset is a vacuum deposition toolset. 80. The method of claim 79, wherein the second processing toolset is a wet processing toolset. 81. The method of claim 77, wherein the first processing toolset is a vacuum deposition toolset. 82. The method of claim 67, wherein said barrier layer comprises tantalum. 83. The method of claim 67, wherein said seed layer comprises copper. 84. The method of claim 67, wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. 85. The step of electroplating one or more copper devices comprises depositing a pattern mask layer on the seed layer so that selected portions of the seed layer are exposed, and 68. The method of claim 67, comprising: electroplating one or more copper devices on the seed layer through selected portions. 86. A method of forming one or more protected copper elements on a surface of a work piece, comprising: depositing a conductive barrier layer on the work piece; Electroplating one or more copper elements, rendering at least a portion of the surface of the conductive barrier layer unplatable, and electroplating a protective layer on the surface of the one or more copper elements. And how. 87. The method of claim 86, further comprising depositing a dielectric layer on at least a portion of the one or more copper devices. 88. Deposit a dielectric layer to substantially cover one or more copper elements, and remove a surface portion of the dielectric layer to remove one or more copper elements over one or more copper elements. 87. The method of claim 86, further comprising: exposing an area. 89. The method of claim 86, wherein the step of rendering at least a portion of the surface of the barrier layer non-plateable comprises oxidizing an exposed surface of the barrier layer material. 90. Electroplating one or more copper elements on selected portions of the conductive barrier layer comprises: electroplating one or more copper wires on selected portions of the conductive barrier layer; 87. The method of claim 86, further comprising: electroplating one or more copper posts on selected portions of the copper wire. 91. The step of rendering at least a portion of the surface of the barrier layer unplatable comprises simultaneously oxidizing the exposed surface of the barrier layer material and the one or more copper elements, and removing the resulting copper oxide. 87. The method of claim 86, comprising removing from one or more copper devices. 92. The method of claim 86, further comprising removing the barrier layer after electroplating the protective layer. 93. The method of claim 86, wherein said barrier layer is applied with a first processing tool set. 94. The method of claim 93, wherein said electroplating and said non-plating are performed in a second processing tool set. 95. The method of claim 94, wherein said first processing toolset is a vacuum deposition toolset. 96. The method of claim 95, wherein said second processing toolset is a wet processing toolset. 97. The method of claim 93, wherein said first processing toolset is a vacuum deposition toolset. 98. The method according to claim 86, wherein said barrier layer comprises titanium nitride. 99. The method according to claim 86, wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. 100. The method of claim 86, wherein said barrier layer comprises titanium nitride overlying tantalum nitride, and wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. . 101. The step of electroplating one or more copper elements comprises depositing a pattern mask layer on the barrier layer so that selected portions of the conductive barrier layer are exposed, and 87. The method of claim 86, comprising: electroplating one or more copper devices on the conductive barrier layer through the selected portions. 102. A method of forming one or more metallization layers on a surface of a semiconductor workpiece, comprising: attaching a barrier layer to the semiconductor workpiece; attaching a seed layer to the barrier layer; Electroplating one or more copper interconnect lines on selected portions of the copper, electroplate one or more copper posts on selected portions of the copper interconnect lines, substantially removing the seed layer Simultaneously oxidizing the exposed surface of the one or more copper interconnect lines, the exposed surface of the one or more copper posts, and the exposed surface of the barrier layer, thereby converting the resulting copper oxide layer to the one or more copper Removing the interconnect lines and one or more copper posts while leaving the surface of the oxidized barrier layer substantially unchanged while keeping the surface of the barrier layer non-plateable; Electroplate a protective layer on the exposed surfaces of the interconnect lines, A method comprising the steps of: 103. The method of claim 102, further comprising depositing a dielectric layer on at least a portion of the one or more copper devices. 104. Depositing a dielectric layer to substantially cover one or more copper interconnect lines and one or more copper posts, and removing a surface portion of the dielectric layer, 103. The method of claim 102, further comprising exposing an upper region of one or more copper posts. 105. The method of claim 102, further comprising removing the barrier layer after electroplating the protective layer. 106. The method of claim 102, wherein the barrier layer and the seed layer are deposited with a first set of processing tools. 107. The method of claim 106, wherein said electroplating and oxidation steps are performed in a second set of processing tools. 108. The method of claim 107, wherein the first processing toolset is a vacuum deposition toolset. 109. The method of claim 108, wherein the second set of processing tools is a wet processing toolset. 110. The method of claim 106, wherein the first processing toolset is a vacuum deposition toolset. 111. The step of electroplating one or more copper interconnect lines comprises: depositing a pattern mask layer on the seed layer so that selected portions of the seed layer are exposed; 103. The method of claim 102, comprising: electroplating one or more copper interconnect lines on the seed layer through the selected portions. 112. The step of electroplating one or more copper posts comprises: depositing a pattern mask layer over the seed layer and the one or more interconnect lines, exposing selected upper portions of the copper interconnect lines. 112. The method of claim 111, including the steps of: electroplating one or more copper posts through the exposed portions of the copper interconnect lines. 113. The method of claim 102, wherein said barrier layer comprises tantalum. 114. The method of claim 102, wherein said seed layer comprises copper. 115. The method of claim 102, wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. 116. The step of substantially removing the seed layer is performed simultaneously during the step of removing the resulting copper oxide layer from one or more copper interconnect lines and one or more copper posts. 103. The method of claim 102. 117. The step of substantially removing the seed layer includes subjecting the seed layer to an electrolytic bath treatment while maintaining the seed layer at a positive potential with respect to the electrode immersed in the electrolytic bath containing phosphoric acid. 103. The method of claim 102, comprising the step of causing. 118. A method of forming one or more protected copper elements on a surface of a workpiece, comprising: attaching a barrier layer to the workpiece; attaching a seed layer to the barrier layer; Electroplating one or more copper elements on selected portions, substantially removing the seed layer, rendering at least a portion of the barrier layer surface non-plateable, and protecting the surface of the one or more copper elements Electroplating a layer. 119. The method of claim 118, further comprising depositing a dielectric layer on at least a portion of the one or more copper devices. 120. The step of substantially removing the seed layer includes subjecting the seed layer to an electrolytic bath treatment while maintaining the seed layer at a positive potential with respect to the electrode immersed in the electrolytic bath containing phosphoric acid. 119. The method of claim 118, comprising the step of causing. 121. Depositing a dielectric layer to substantially cover one or more copper elements, and removing a surface portion of the dielectric layer to remove one or more of the one or more copper elements 119. The method of claim 118, further comprising: exposing an area. 122. The method of claim 118, wherein said step of rendering at least a portion of the surface of the barrier layer non-plateable comprises oxidizing an exposed surface of the barrier layer material. 123. Electroplating one or more copper elements on selected portions of the seed layer; electroplating one or more copper wires on selected portions of the seed layer; 120. The method of claim 118, comprising: electroplating one or more copper posts on selected portions of the lines. 124. The step of rendering at least a portion of the surface of the barrier layer unplatable comprises simultaneously oxidizing the barrier layer material and the exposed surface of the one or more copper elements, and removing the resulting copper oxide. 119. The method of claim 118, comprising: removing from one or more copper devices. 125. The method of claim 124, wherein said step of substantially removing a seed layer is performed simultaneously during said step of removing said resulting copper oxide layer from one or more copper devices. 126. Electroplating one or more copper elements on selected portions of the seed layer; electroplating one or more copper wires on selected portions of the seed layer; 125. The method of claim 124, comprising: electroplating one or more copper posts on selected portions of the. 127. The method of claim 118, further comprising removing the barrier layer after electroplating the protective layer. 128. The method of claim 118, wherein said barrier layer and seed layer are deposited with a first processing tool set. 129. The method of claim 128, wherein the electroplating step and the non-plating step are performed with a second processing toolset. 130. The method of claim 129, wherein the first processing toolset is a vacuum deposition toolset. 131. The method of claim 130, wherein the second processing toolset is a wet processing toolset. 132. The method of claim 128, wherein the first processing toolset is a vacuum deposition toolset. 133. The method of claim 118, wherein said barrier layer comprises tantalum. 134. The method of claim 118, wherein said seed layer comprises copper. 135. The method of claim 118, wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. 136. The step of electroplating one or more copper devices comprises depositing a pattern mask layer on the seed layer so that selected portions of the seed layer are exposed, and 119. The method of claim 118, comprising: electroplating one or more copper devices on the seed layer through selected portions. 137. A method of forming one or more protected copper elements on a surface of a workpiece, comprising: attaching a conductive barrier layer to the workpiece; and applying one or more conductive barrier layers to selected portions of the conductive barrier layer. Electroplating one or more copper devices, rendering at least a portion of the surface of the conductive barrier layer unplatable, and electroplating a protective layer on the surface of the one or more copper devices. And how to. 138. The method of claim 137, further comprising depositing a dielectric layer on at least a portion of the one or more copper devices. 139. A dielectric layer is deposited to substantially cover the one or more copper elements, and a surface portion of the dielectric layer is removed to remove one or more of the one or more copper elements. 138. The method of claim 137, further comprising: exposing an area. 140. The method of claim 137, wherein the step of rendering at least a portion of the surface of the barrier layer non-plateable comprises oxidizing an exposed surface of the barrier layer material. 141. The step of electroplating one or more copper elements on selected portions of the conductive barrier layer comprises: electroplating one or more copper wires on selected portions of the conductive barrier layer. 138. The method of claim 137, comprising: and electroplating one or more copper posts on selected portions of the copper wire. 142. The step of rendering at least a portion of the surface of the barrier layer unplatable comprises simultaneously oxidizing the barrier layer material and the exposed surface of the one or more copper elements, and removing the resulting copper oxide. 138. The method of claim 137, comprising: removing from one or more copper devices. 143. The method of claim 137, further comprising removing the barrier layer after electroplating the protective layer. 144. The method of claim 137, wherein said barrier layer is applied with a first processing tool set. 145. The method of claim 144, wherein the electroplating step and the non-plating step are performed with a second processing toolset. 146. The method of claim 145, wherein the first processing toolset is a vacuum deposition toolset. 147. The method of claim 146, wherein the second processing toolset is a wet processing toolset. 148. The method of claim 144, wherein the first processing toolset is a vacuum deposition toolset. 149. The method according to claim 137, wherein said barrier layer comprises titanium nitride. 150. The method of claim 137, wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. 151. The method of claim 137, wherein said barrier layer comprises titanium nitride overlying tantalum nitride, and said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. . 152. The step of electroplating one or more copper devices comprises depositing a pattern mask layer on the barrier layer so that selected portions of the conductive barrier layer are exposed, and 138. The method of claim 137, comprising: electroplating one or more copper devices on the conductive barrier layer through the selected portions. 153. A method of forming one or more copper metallization layers on a surface of a semiconductor workpiece comprising: attaching a barrier layer to the semiconductor workpiece; attaching a seed layer to the barrier layer; Electroplating one or more copper interconnect lines on selected portions of the layer, electroplating one or more copper posts on selected portions of the copper interconnect lines, and substantially disposing the seed layer. Removing, simultaneously oxidizing the exposed surface of the one or more copper interconnect lines, the exposed surface of the one or more copper posts, and the exposed surface of the barrier layer, thereby removing the resulting copper oxide layer to the one or more copper Removing one or more of the interconnect lines and one or more copper posts while leaving the surface of the barrier layer non-plateable while leaving the surface of the oxidized barrier layer substantially unchanged; and Electroplating a protective layer on the exposed surfaces of the interconnect lines, and A method comprising the steps of: 154. The method of claim 153, further comprising depositing a dielectric layer on at least a portion of the one or more copper devices. 155. A dielectric layer is deposited to substantially cover one or more copper interconnect lines and one or more copper posts, and a surface portion of the dielectric layer is removed. 154. The method of claim 153, further comprising exposing an upper region of the one or more copper posts. 156. The method of claim 153, further comprising removing the barrier layer after electroplating the protective layer. 157. The step of electroplating one or more copper interconnect lines comprises: depositing a pattern mask layer on the seed layer so that selected portions of the seed layer are exposed; 154. The method of claim 153, comprising: electroplating one or more copper interconnect lines on the seed layer through the selected portions. 158. The step of electroplating one or more copper posts includes depositing a pattern mask layer over the seed layer and the one or more interconnect lines, exposing selected upper portions of the copper interconnect lines. 154. The method of claim 153, including the steps of: electroplating one or more copper posts through the exposed portions of the copper interconnect lines. 159. The method according to claim 153, wherein said barrier layer comprises tantalum. 160. The method of claim 153, wherein said seed layer comprises copper. 161. The method of claim 153, wherein said protective layer comprises a material selected from the group consisting of nickel, nickel alloy and chromium. 162. The step of substantially removing the seed layer is performed simultaneously during the step of removing the resulting copper oxide layer from one or more copper interconnect lines and one or more copper posts. 154. The method of claim 153. 163. The step of substantially removing the seed layer includes subjecting the seed layer to an electrolytic bath treatment while maintaining the seed layer at a positive potential with respect to the electrode immersed in the electrolytic bath containing phosphoric acid. 153. The method of claim 153, comprising the step of causing. 164. A manufacturing tool arrangement for providing one or more interconnect metallization levels to a generally planar dielectric surface of a workpiece, wherein a barrier layer is deposited outside the planar dielectric surface. A film deposition tool set for depositing a seed layer outside the barrier layer, a hard mask forming tool set for forming a hard mask dielectric layer outside the seed layer, and on the hard mask dielectric layer A pattern processing tool set for providing an interconnect line pattern on the interconnect line pattern and providing a post pattern on the interconnect line metallization formed using the interconnect line pattern; and A hard mask etching toolset for etching exposed areas of the mask dielectric layer, and at least the following wet processing operations; Providing an interconnect line pattern defined by the hard mask and a post pattern defined by the pattern material used in the pattern processing toolset to a metallization of copper using an electrochemical deposition process; Remove material deposited by patterning tool set to form interconnect line patterns and post patterns, remove hard mask dielectric layer, and seed layer and barrier not covered by interconnect line metallization A wet processing toolset for performing an operation of removing a portion of a layer; depositing a dielectric layer over the interconnect line metallization and post metallization; and depositing the deposited dielectric layer A dielectric processing tool set for etching the upper contact area of the post metallization portion, To use the work piece moves below 12 times, interconnect line metallization, manufacturing tool structure, wherein a single metallization level is formed consisting of the post-metallization and dielectric layers. 165. The manufacturing tool arrangement of claim 164, wherein the wet processing tool set includes at least one processing station for applying a protective coating that is electrochemically applied to an exterior of the copper metallization. . 166. The manufacturing tool according to claim 164, wherein the wet processing tool set includes at least one processing station for conditioning a surface of a workpiece prior to further processing within the wet processing tool set. Construct. 167. The wet processing tool set includes at least one processing station for oxidizing exposed metallized portions of the workpiece.
5. The manufacturing tool structure according to 4. 168. The wet processing tool set includes at least one processing station for removing oxidized metal portions of a workpiece.
3. The manufacturing tool structure according to claim 1. 169. at least one for removing said oxidized metal portion;
169. The manufacturing tool arrangement of claim 168, wherein one processing station is also used to condition the surface prior to subsequent processing. 170. The manufacturing tool assembly of claim 164, wherein said film deposition tool set is a vacuum deposition tool set. 171. The manufacturing tool arrangement of claim 164, wherein the film deposition tool set deposits a substantially planar bonding layer, and wherein the barrier layer is deposited over the bonding layer by a film deposition tool set. . 172. The manufacturing tool arrangement of claim 164, wherein the film deposition tool set deposits a substantially planar bonding layer directly on a dielectric layer. 173. The manufacturing tool assembly of claim 164, wherein said pattern processing tool set is a photoresist processing tool set. 174. The manufacturing tool arrangement of claim 164, wherein the dielectric deposition tool set deposits a low K dielectric material. 175. The manufacturing tool arrangement of claim 164, wherein the film deposition tool set is a single integrated tool. 176. The manufacturing tool arrangement of claim 164, wherein the pattern processing tool set is a single integrated tool. 177. The manufacturing tool construction of claim 164, wherein the dielectric deposition tool set is a single integrated tool. 178. The manufacturing tool arrangement of claim 164, wherein the electrochemical / wet processing tool set is a single integrated tool. 179. The manufacturing tool arrangement of claim 164, further comprising an inspection tool set for inspecting a workpiece in one or more processing states during formation of a single metallization level. 180. The manufacturing tool arrangement of claim 179, wherein the wet processing tool set includes at least one processing station for applying a protective coating that is electrochemically applied to the exterior of the copper metallization. . 181. The manufacturing tool of claim 179, wherein the wet processing tool set includes at least one processing station for conditioning a surface of a workpiece prior to further processing within the wet processing tool set. Construct. 182. The wet processing tool set includes at least one processing station for oxidizing exposed metallized portions of a workpiece.
10. The manufacturing tool structure according to 9. 183. The wet processing tool set includes at least one processing station for removing oxidized metal portions of a workpiece.
3. The manufacturing tool structure according to claim 1. 184. At least one processing station for said oxidation and at least one processing station for removing oxidized metal parts,
183. The manufacturing tool arrangement of claim 183, being the same processing station. 185. A manufacturing tool arrangement for providing one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece, wherein a barrier layer is deposited outside the planar dielectric surface. A film deposition tool set for depositing a seed layer outside the barrier layer, a hard mask forming tool set for forming a hard mask dielectric layer outside the seed layer, and on the hard mask dielectric layer A pattern processing tool set for providing an interconnect line pattern on the interconnect line pattern and providing a post pattern on the interconnect line metallization formed using the interconnect line pattern; and A hard mask etching toolset for etching exposed areas of the mask dielectric layer, and at least the following wet processing operations, The interconnect line patterns and post patterns formed using the patterning toolset are provided with a copper metallization using an electrochemical deposition process to remove material deposited by the patterning toolset. Forming interconnect line patterns and post patterns, removing the hard mask dielectric layer, and removing portions of the seed and barrier layers not covered by the interconnect line metallization. A wet processing tool set for depositing a dielectric layer over the interconnect line metallization and post metallization, and etching the deposited dielectric layer to connect the post metallization over A dielectric processing tool set for exposing regions, and using no more than seven workpiece movements between said tool sets, Manufacturing tool structure, characterized in that the connection line metallization, single metallization level composed of post metallization and dielectric layers are formed. 186. The manufacturing tool arrangement of claim 185, wherein the wet processing tool set includes at least one processing station for applying a protective coating that is electrochemically applied to an exterior of the copper metallization. . 187. The manufacturing tool of claim 185, wherein the wet processing tool set includes at least one processing station for conditioning a surface of a workpiece prior to further processing within the wet processing tool set. Construct. 188. The wet processing tool set includes at least one processing station for oxidizing exposed metallized portions of the workpiece.
6. The manufacturing tool structure according to 5. 189. The manufacturing tool assembly of claim 185, wherein said film deposition tool set is a vacuum deposition tool set. 190. The manufacturing tool arrangement of claim 185, wherein the film deposition tool set deposits a substantially planar bonding layer, and wherein the barrier layer is deposited over the bonding layer by a film deposition tool set. . 191. The manufacturing tool arrangement of claim 185, wherein said film deposition tool set deposits a substantially planar bonding layer directly on a dielectric layer. 192. The manufacturing tool assembly of claim 185, wherein said pattern processing tool set is a photoresist processing tool set. 193. The manufacturing tool arrangement of claim 185, wherein the dielectric deposition tool set deposits a low K dielectric material. 194. The manufacturing tool arrangement of claim 185, wherein said film deposition tool set is a single integrated tool. 195. The manufacturing tool arrangement of claim 185, wherein the pattern processing tool set is a single integrated tool. 196. The manufacturing tool arrangement of claim 185, wherein said dielectric deposition tool set is a single integrated tool. 197. The manufacturing tool arrangement of claim 185, wherein the electrochemical / wet processing tool set is a single integrated tool. 198. A manufacturing tool arrangement for providing one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece, wherein a barrier layer is deposited outside the planar dielectric surface. And a film deposition tool set for depositing a seed layer outside the barrier layer; forming a first hardmask dielectric layer outside the seed layer;
A hard mask forming tool set for forming a second hard mask dielectric layer outside the hard mask dielectric layer; and providing an interconnect line pattern on the first hard mask dielectric layer;
A pattern processing tool set for providing a post pattern on the hard mask dielectric layer, and an exposed area of the first hard mask dielectric layer after forming the interconnect line pattern and a second after forming the post pattern. A hard mask etching tool set for etching the hard mask dielectric layer; and at least the following wet processing operations: an interconnect line pattern defined by the first hard mask and a post defined by the second hard mask. The pattern is provided with a copper metallization using an electrochemical deposition process to remove material deposited by the patterning toolset and to provide interconnect line and post patterns to the hardmask dielectric layer. Form, remove the hard mask dielectric layer, and cover with interconnect line metallization Removing a portion of the seed layer and barrier layer that have not been removed; depositing a dielectric layer over the interconnect line metallization and post metallization; and A dielectric processing tool set for etching the deposited dielectric layer to expose the upper connection area of the post metallization, using no more than nine workpiece movements between said tool sets. A single metallization level comprising interconnect line metallization, post metallization and a dielectric layer is formed.