TW426979B - Fabrication method of dual damascene copper interconnects - Google Patents

Abstract

This invention provides the fabrication method of dual damascene copper interconnects and includes the followings. At first, a dielectric layer and a separation layer are formed globally on top of the semiconductor substrate. The separation layer and the dielectric layer stated above are selectively etched to form a contact via. A layer of copper crystal seed is formed on the sidewall and bottom face of contact via stated above. Then, a layer of high resistance material is globally formed on top of the copper crystal seed layer. The high resistance material layer is selectively etched until the copper crystal seed layer is exposed such that the high resistance material model is remained and the dual damascene structure is defined. The electrochemical deposition method is used to form copper metal inside the model stated above to form dual damascene copper interconnects. Finally, the high resistance material model and the copper crystal seed layer which is under the high resistance material model are stripped off. Based on the fabrication method of this invention, the application of chemical mechanical polishing method to perform the planarization of copper interconnects is not necessary such that the possibility of copper metal contamination is greatly reduced.

Description

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The present invention relates to a manufacturing process for conducting a bulk circuit in a manufacturing process capable of preventing interconnections, and a special copper / defective copper metal interconnect (Cu is indispensable for any electronic component) The same applies to the metal wire 'semiconductor integrated circuit of telecom, and each component must be electrically connected by an appropriate interconnect to achieve the desired function. In today's multi-layer interconnect process In addition to the production of various layers of wire patterns, contact vias must be used as the communication channel between the component contact area disk wires or the multilayer wires. In terms of the material of the interconnect, copper metal The high conductivity, high ductility, and other advantages have become one of the materials that have attracted much attention. The following uses the dual inlay (dual 仏 ㈣ "⑽ ... copper cross-section process cross-section diagram of Figure 1A ~ 1B to illustrate the practice The symbol 10 shown in FIG. 1A indicates a semiconductor substrate on which elements such as transistors T1, T2, and T3 are formed. The symbols 11 and 16 represent dielectric layers, and the symbols I and 14 represent conducting crystals. The copper interconnects of the components T1, T2, and T3. The symbol M represents a diffusion barrier layer and the symbol 20 represents a copper metal interconnect formed, for example, by an electrochemical deposition method. Please refer to FIG. The polishing method (chemica 1 mechanical polishing; CMP) planarizes the steel metal interconnects to obtain a double damascene copper interconnects 20a, 20b with a flat surface. Although the copper interconnects are easily formed using the conventional techniques described above, However, after the copper metal is processed by CMP, a complicated cleaning step must be performed, or serious copper metal pollution will be caused.

426979_______ 5. Description of the invention (2) In view of the problems of the above-mentioned conventional technologies, an object of the present invention is to provide a method for manufacturing a dual-inlaid copper interconnect, without the need to use chemical mechanical polishing to planarize steel interconnects. Therefore, the possibility of copper metal contamination can be greatly reduced. According to the above object, the present invention provides a method for manufacturing a dual damascene copper interconnect, which is applicable to a semiconductor substrate having conductive blocks formed therein. The method includes the following steps: (a) forming a dielectric layer over the semiconductor substrate Layer and a barrier layer; (b) selectively etching the barrier layer and the dielectric layer to form a contact hole exposing the conductive block; (c) forming a copper seed layer on a side wall and a bottom surface of the contact hole; And extended on the surface of the barrier layer; (d) forming a high-resistance material layer on the steel seed layer; (e) selectively engraving the high-resistance material layer until the copper seed layer is exposed; A double-inlay structure is defined by leaving a high-resistance material model; (f) forming a copper metal in the above model by using an electrochemical deposition method to form a double-inlay copper interconnect; and (g) removing the high-resistance Material model and the copper seed layer below it. In the above-mentioned manufacturing method of the dual damascene steel interconnect, the dielectric layer is a silicon layer or a low dielectric constant organic material layer. In addition, the barrier layer system is a vermiculite layer. The above conductive blocks are copper interconnects. The positive seed layer is formed by chemical vapor deposition. To the above, in the method for manufacturing the dual damascene copper interconnect, the step of forming the seed layer of tantalum steel further includes a step of forming a diffusion barrier layer (nitride). And ’the above-mentioned high-resistance material layer-based oxide layer has a thickness between

Page 5 ^^ 6979 V. Description of the invention (3) Between 6000 and 8000 Angstroms. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: Figure 1B is a cross-sectional view of the manufacturing process of the double-inlaid copper interconnects of the conventional technology. Figures 2A to 2H are schematic cross-sectional views of a manufacturing process of a dual-inlaid copper interconnect according to an embodiment of the present invention. Explanation of symbols 100 to semiconductor (silicon) substrate. 102, 104 ~ conductive block (copper interconnect). 106 ~ Intermetal dielectric layer. 108, 122 ~ barrier layer. 11 0 a, 11 0 b, 11 0 c to contact holes. 112 ~ Diffusion barrier layer / copper seed layer. 11 4 ~ High resistance material layer. 11 4a ~ High resistance material model. DD1, DD2 ~ Dual mosaic structure. 11 6 to copper interconnects. 120 ~ Intermetal dielectric layer with uneven surface. 120a ~ Intermetal dielectric layer with flat surface. Example The following uses the process cross-sectional schematic diagrams shown in Figures 2A to 2H for more details.

V. Description of the invention (4) The invention will be described in detail. First, please refer to FIG. 2A, which shows, for example, a semiconductor substrate 100 'composed of a monocrystalline stone, which has formed several semiconductor elements (transistors Ti, T2, T3, etc.), an inter-layer dielectric layer (inter-iayer dielectric; ILD) 101, such as conductive blocks 102 and 104 of copper interconnects, inter-metal dielectric (IMD) 106, and barrier layers to prevent copper metal from diffusing to other components ( resist layer) 108. The above interlayer dielectric layer 101 and the intermetallic dielectric layer 106 are, for example, a silicon dioxide layer or a low dielectric constant organic material layer. A specific example thereof is a PAE-2 layer manufactured by Schumacher Company. FLARE layer, HOSP layer and LOSP layer manufactured by Allied Signal can be used as the organic low dielectric constant material layer. The above-mentioned barrier layer 108 is, for example, a silicon nitride or oxynitride layer formed by a chemical vapor deposition (CVD) method, which also has an anti-reflection function. Then 'Please refer to FIG. 2B, using a series of steps of coating photoresist, baking, exposure, and development using a traditional lithographic process to form a photoresist pattern (not shown), and then use this photoresist pattern as The mask is etched, and the barrier layer 108 and the intermetal dielectric layer 106 are selectively etched to form a contact hole 110a, 110b, 110c that exposes the conductive blocks 102, 104. Next, remove the photoresist pattern. Then, please refer to FIG. 2C. Symbol 11 in the figure represents a diffusion barrier layer and a copper seed layer 112 which are sequentially formed. The diffusion barrier layer is formed by a CVD method, for example. Tantalum nitride (TaN) / giant layer formed on the side of the above-mentioned contact holes 1 10a, 1 10b '110c

Page 7 Five 'Explanation of Invention (5)' — Wall and bottom. The purpose of the steel seed layer is to establish the basic structure for subsequent electrochemical formation of copper and metal. Next, a high-resistance material layer i 丨 4 composed of silicon dioxide is comprehensively formed by using a chemical vapor deposition method or the like. This layer is also referred to as a self-aligned layer. Between 6000 and 8000 angstroms, it must be a non-conductive material in order to prevent subsequent electro-chemical deposition (ECD) steps from forming metals such as copper. Furthermore, please refer to Figure 2D. Use a traditional lithography process to perform a series of steps of coating photoresist, baking, exposure, and development to form a photoresist pattern (not shown), and then use this photoresist pattern. As an etching mask, the above-mentioned high-resistance material layer 丨 4 is selectively etched until the above-mentioned diffusion barrier layer / copper seed layer 11 2 is exposed, so as to leave a high-resistance material model 〖4a, and define double Mosaic structure DD1, DD2. * After ', please refer to FIG. 2E, using the electrochemical deposition method and controlling the appropriate reaction conditions to form copper metal in the above-mentioned model 114a to form a double-inlaid copper interconnect 116'116. Then, referring to FIG. 2F, the dry resist or fish etching method is used to remove the above-mentioned high-resistance material model; 1 丨 4a ', and then the diffusion barrier layer / copper seed layer 112 under the above-mentioned high-resistance material model 114a is removed. Then, please refer to Figure 2G and Figure 2Η. These two diagrams are schematic diagrams of the subsequent steps of forming the interconnect 116. The symbol 丨 2〇 represents the metal interposer covering the double-inlaid copper interconnect 116, 116. The electric layer 'symbol 丨 2 〇a represents an intermetal dielectric layer after planarization by a chemical mechanical polishing method, and the symbol 丨 2 2 represents a barrier layer for preventing copper metal from diffusing to other elements.

Features and Effects of the Invention The present invention is characterized by being separated from the Φ by the city, and the secret nm nm field resistance material model 114a to define the dual mosaic structure DD1, DD2. Next, the weight 11 1 r%% s ^ ^ After the copper interconnect 116 is formed by electroplating using the ECD method, the plutonium resistor material model is removed. V. Description of the invention (6) According to the manufacturing method of the present invention, ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Although the present invention has been disclosed in a preferred embodiment, the above is the definition of the present invention. Anyone who is familiar with the art will not take off :: smoke: it can be modified and retouched. Therefore: :::: =: Although It is subject to the definition in the appended patent scope.

Claims (1)

"4 coffee" ————— 六 '应用 专 # ίΐϊϊ ~ "'-^ 1, a manufacturing method of dual-inlaid copper interconnects, suitable for forming a semiconductor substrate of an electrical block, the above method includes the following steps: (a) comprehensively forming a dielectric-barrier layer above the semiconductor substrate: (b) selectively etching the barrier layer and the dielectric layer to form a contact hole exposing the conductive block; (c) above the above A copper seed layer is formed on the side wall and the bottom surface of the contact hole and extends on the surface of the barrier layer; (d) A high-resistance material is comprehensively formed above the copper seed layer (e) Selectively etching the high Resistive material layer 'until the above-mentioned copper: seed layer is exposed to leave a model of high-resistance material and define a dual damascene structure; X (0) A steel metal is formed in the above model by electrochemical deposition to form a dual damascene copper And (g) removing the above-mentioned high-resistance material model and the steel seed layer below it. 2. The method for making a double-inlaid copper interconnect as described in the first item of the scope of patent application, wherein Dielectric layer system Silicon dioxide layer. ^ 3, the manufacturing method of the dual damascene copper interconnect as described in item 1 of the scope of the patent application, wherein the above dielectric layer is a low dielectric constant organic material layer. The method of manufacturing / removing the double-inlaid copper interconnects as described in the above item, wherein the above-mentioned barrier layer is a nitrided nitride layer or an oxynitride layer. 5 'The double-inlaid copper as described in item 1 of the patent application scope A method for manufacturing a connection, wherein the conductive block is a copper interconnection. Page i〇 4 ^ 69 7 9 'VI. Patent application scope 6. The manufacturing method of the dual-inlaid copper interconnects as described in item 1 of the patent application scope, wherein the above copper seed layer uses a chemical vapor phase Formed by deposition. * 7. The method for manufacturing a dual-inlaid copper interconnect as described in item 1 of the scope of patent application, wherein step (c) further includes a step of forming a diffusion barrier layer before forming the copper seed layer. 8. The manufacturing method of the dual damascene copper interconnects as described in item 7 of the scope of the patent application, wherein the diffusion barrier layer is a nitride group / group layer. 9. The manufacturing method of the dual-inlaid copper interconnects as described in item 1 of the scope of the patent application, wherein the high-resistance material layer is an oxide layer. 10. The method for manufacturing a double-inlaid copper interconnect as described in item 1 of the scope of patent application, wherein the thickness of the high-resistance material is between 6 000 and 8000 Angstroms. Page 11