JP2012064953A - Method of forming interconnection and method of forming display device having the interconnection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the following problems: manufacturing process is complicated and manufacturing cost is high when interconnections or electrodes are formed using a conventional damascene method involving CMP; highly accurate planarity, or the like, is required for forming interconnections on the large substrate of a display device, or the like; and a large amount of interconnection material is removed or wasted due to polishing.SOLUTION: In the method of forming interconnections and the method of forming a display device, a metal seed layer is formed by CVD on a first metal diffusion prevention film provided on a substrate or a circuit element, a metal interconnection layer is formed selectively using a photoresist mask by electroless plating or electrolytic plating, unnecessary regions of the metal seed layer and the first diffusion prevention film are removed, and then a second metal diffusion prevention film is formed selectively by electroless plating to cover a surface including the side surfaces of the metal seed layer and the metal interconnection layer and the first metal diffusion prevention film thus forming interconnections and electrodes.

Description

  The present invention relates to a method for forming a wiring used in a display device represented by a liquid crystal display device, a semiconductor device such as ULSI, and the like, and a method for forming a display device having the wiring.

  In general, wiring and electrodes using aluminum (Al) or an alloy thereof are mainly used as wiring materials in semiconductor devices represented by LSI and ULSI. However, due to the progress of miniaturization due to the recent improvement in integration and the improvement of the operation speed, the next generation of copper (Cu), which has lower resistance than Al and higher resistance to electromigration and stress migration, etc. It has been studied to adopt as a material for wiring and electrodes.

  Furthermore, in the field of display devices represented by liquid crystal display devices, etc., there is an increase in wiring length due to an increase in display area, and due to demands for monolithic mounting with various additional functions such as a driver circuit for driving and a memory in a pixel. As with the semiconductor field, there is an increasing demand for low resistance wiring.

For fine copper wiring processing, masking technology by PEP (Photo Engraving Process, so-called photolithography), RIE (Reactive Ion Etching) method, etc., as well as Al wiring formation technology Even if this etching technique is simply combined, it has been difficult to realize. In other words, the vapor pressure of the copper halide is very low (that is, it is difficult to evaporate) as compared with the halide of Al, and when an etching technique such as RIE is used, the process temperature is 200 to 300 ° C. There are many problems such as the necessity of the etching process. Further, it is necessary to use a mask made of SiO ₂ or SiNx instead of a normal photoresist mask.

  Therefore, for example, a so-called damascene method disclosed in Patent Document 1 and Patent Document 2 can be used. In this damascene method, a wiring groove having a desired wiring pattern is first formed in advance on an insulating layer on a substrate. Next, various methods such as a PVD (Physical Vapor Deposition) method such as a sputtering method, a plating method, or a CVD (Chemical Vapor Deposition) method using an organic metal material so as to fill the wiring trench are used. A thin copper layer is embedded in the groove and formed over the entire surface of the insulating layer. Thereafter, the copper thin layer is removed by using a polishing method such as CMP (Chemical Mechanical Polishing) or an etch back until the lower insulating layer is exposed from the substrate surface side (open end surface of the groove portion). Then, a wiring pattern made only of copper embedded in the groove is formed.

JP 2001-189295 A Japanese Patent Laid-Open No. 11-135504

However, the conventional techniques including the techniques disclosed in Patent Document 1 and Patent Document 2 described above have the following problems.
In the damascene method, at least a groove processing step for forming a groove for embedding a wiring, a film formation step for forming a wiring pattern and a via (plug) connecting upper and lower electrodes, a photolithography step, an etching step, and a polishing A stop film forming process is required, which complicates the manufacturing process and increases the manufacturing cost.

  In order to reduce the wiring resistance, it is necessary to increase the cross-sectional area of the wiring. However, due to the limitation of integration, if a groove or via hole with a high aspect ratio (that is, a narrow width and diameter) is used, Copper embedding is reduced. In addition, a CMP process or the like of removing unnecessary portions after forming a thin copper layer on the entire surface of the substrate takes a long time and has a low throughput.

  Further, a large-sized CMP apparatus corresponding to a large-diameter semiconductor wafer size such as 12 inches in diameter has been developed. However, a display apparatus using a glass substrate that has a larger area than the semiconductor wafer and accuracy such as flatness is not good. The manufacturing apparatus for this purpose has not been put into practical use.

  Further, in the case of a large substrate (display screen) mounted on a display device, for example, a large liquid crystal display device, a copper thin layer used as a wiring even if the entire surface polishing by CMP and removal by an etching method are possible Since the portion is very small compared to the area of the glass substrate, most of the deposited copper thin layer is removed and discarded. As a result, the utilization efficiency of expensive copper as a material becomes very poor, and the product price increases due to the high cost.

  Therefore, the present invention can realize the formation of metal wiring made of a low-resistance material on a large-area substrate, can eliminate the waste of wiring material in the wiring formation, and can reduce the manufacturing cost by reducing the number of manufacturing processes. An object is to provide a wiring, a display device, and a method for forming them.

  In order to achieve the above object, an embodiment according to the present invention includes a step of forming a first metal diffusion prevention layer on a substrate, and following the step, the first metal diffusion prevention layer using a resist pattern. A step of sequentially forming a metal seed layer having a predetermined pattern on the metal seed layer using a CVD method and a metal wiring layer on the metal seed layer using an electroless plating method or an electrolytic plating method; Etching the first metal diffusion prevention layer other than the region overlapping the metal wiring layer in a plane, and covering the exposed surface including at least the metal seed layer and the side surface of the metal wiring layer. And forming a metal diffusion prevention layer. 2. A wiring forming method comprising:

  Furthermore, another embodiment is a method for forming a display device having electrodes of pixel driving elements arranged in a matrix, scanning lines connected to the driving elements, and signal lines, A step of forming a metal diffusion preventing layer; and following the step, the electrode having a predetermined pattern so as to fill the resist pattern on the first metal diffusion preventing layer using a resist pattern, the scanning A step of sequentially forming a metal seed layer to be one of the line and the signal line using a CVD method, and forming a metal wiring layer on the metal seed layer using an electroless plating method or an electrolytic plating method; and at least the metal wiring layer A step of removing the first metal diffusion prevention layer other than that bonded to the substrate by etching, and covering an exposed surface including side surfaces of the metal seed layer and the metal wiring layer. Sea urchin forming a second metal diffusion barrier layer, the formation method of a display device having a wiring having a.

  The present invention realizes the formation of metal wiring and electrodes made of a highly reliable low-resistance material surrounded by a metal diffusion prevention layer on a large-area substrate, and eliminates waste of wiring material in wiring formation and manufacture. It is possible to provide a wiring, an electrode, a display device, and a method for forming them that can reduce the manufacturing cost by reducing the number of steps.

It is a figure which shows the cross-sectional structure of the wiring which concerns on the 1st Embodiment of this invention. It is the first half part of the process diagram for demonstrating the formation method of the wiring in 1st Embodiment. FIG. 6 is a second half of a process diagram for explaining a wiring forming method according to the first embodiment. It is the first half part of the process figure for demonstrating the formation method of the wiring in 2nd Embodiment. It is the latter half part of the process figure for demonstrating the formation method of the wiring in 2nd Embodiment. It is a figure which shows the cross-sectional structure of the wiring which concerns on 3rd Embodiment. It is the first half part of the process diagram for demonstrating the formation method of the wiring in 3rd Embodiment. It is the second half part of the process figure for demonstrating the formation method of the wiring in 3rd Embodiment. It is a figure which shows an example of the equivalent circuit of active matrix LCD which can apply the wiring structure of this invention. It is the first half part of the process figure for demonstrating formation of MOS structure p-type TFT used as the 1st application example which can apply the wiring structure of this invention. It is the latter half part of the process figure for demonstrating formation of MOS structure p-type TFT which can apply the wiring of this invention. It is a figure which shows the cross-sectional structure of the wiring in which the ITO film | membrane was formed. It is process drawing for demonstrating the 1st modification of the formation method of the wiring of this invention. It is a figure which shows the cross-sectional structure of the wiring which concerns on the 2nd modification of the formation method of the wiring of this invention. It is the first half part of the process figure for demonstrating formation of MOS structure p-type TFT used as the 2nd application example which can apply the wiring structure of this invention. It is the latter half part of the process figure for demonstrating formation of MOS structure p-type TFT used as the 2nd application example which can apply the wiring structure of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a cross-sectional configuration of wirings and electrodes according to the first embodiment of the present invention. Here, a configuration in which wiring is directly provided on a substrate will be described as an example. Of course, these wirings and electrodes are already formed on a circuit element or a part of the circuit element on the substrate, and can also be formed thereon.
In the wiring 1, a base insulating layer 3 is provided on a substrate 2 made of glass or the like. A first copper diffusion prevention layer 4 along the wiring pattern is provided on the base insulating layer 3, and a copper seed layer 5 and a copper wiring layer 6 that are slightly narrower than the width of the first copper diffusion prevention layer 4. Are sequentially stacked.

  A second metal diffusion prevention layer 7 is provided so as to cover the surfaces of the copper seed layer 5 and the copper wiring layer 6. In the wiring 1 having such a four-layer structure, the copper seed layer 5 and the copper wiring layer 6 which are substantially copper wirings are surrounded by the first copper diffusion prevention layer 4 and the second copper diffusion prevention layer 7. It is an enclosed structure. When this wiring is incorporated in the circuit, it is possible to prevent the influence of deterioration of the characteristics of adjacent circuit elements such as TFTs due to copper diffusion. The electrodes according to this embodiment can be applied to, for example, low resistance gate electrodes and source / drain electrodes for amorphous silicon TFTs and polysilicon TFTs.

  The thickness of each layer of the wiring 1 is, for example, 400 nm for the base insulating layer 3, 50 nm for the first copper diffusion prevention layer 4, 50 nm for the copper seed layer 5, and 400 nm for the copper wiring layer 6 formed by electrolytic plating. The second copper diffusion prevention layer 7 formed by electroless plating is 50 nm. The metal seed layer and the metal wiring layer in the present invention are, for example, copper or a metal containing copper, and copper has been described as an example, but other metals such as silver and gold can also be used. .

Next, with reference to the process diagrams shown in FIGS. 2A to 2D and FIGS. 3A to 3D, the method for forming the wiring and the electrodes in the first embodiment will be specifically described. To do. Here, wiring formation will be described.
The formation method of this embodiment includes metal wiring layer formation using a selective electroless plating method using a photosensitive resin mask (so-called photoresist mask), and metal seed layer etching by wet etching, electrolytic etching, or the like. In combination, the wiring 1 described above is formed. A predetermined pattern (wiring pattern) of the wiring 1 is determined by the photoresist mask or the like, and the pattern is drawn by a portion where a base that is not masked is exposed. The mask material is not limited to the photosensitive resin, and any material that can be removed and does not electrically and chemically affect the base and the wiring to be formed can be used. The same applies to the following embodiments.

  First, as shown in FIG. 2 (a), a silicon nitride layer (PE (Plasma-Enhanced) -CVD method) is used on the entire surface of a substrate 2 made of glass having a thickness of 0.7 mm, for example. After the base insulating layer 3 made of a SiN layer is deposited to a thickness of 400 nm, for example, a first copper diffusion prevention layer 4 is further formed to a thickness of, for example, 50 nm by sputtering. Of course, these film forming methods are not limited, and other film forming methods such as an evaporation method may be used.

  The first copper diffusion prevention layer 4 includes a Ta layer, a TaN layer, a TiN layer, a TaSiN layer, a WSiN layer, a Mo layer, a Co alloy layer (for example, Co-B or Co-WB), a Ni alloy. (For example, Ni-B), a Mo alloy layer, or the like can be used. Also, it is not a single layer film, but has high adhesion to the underlying insulating layer, low resistance, and high diffusion blocking ability such as Ta / TaN / Ta, TiN / Ti, Co-B / Co, or Ni-B / Ni. The illustrated multilayer film may be used. In each of the following embodiments, a multilayer film may be used as the copper diffusion prevention layer. The substrate 2 is not limited to ordinary glass, and quartz glass, ceramics, and resin members can be applied. Of course, it is also possible to apply to a semiconductor wafer.

  Next, as shown in FIG. 2B, a seed layer 5 made of copper is formed on the first copper diffusion preventing layer 4, for example, a thickness of, for example, 50 nm is formed by sputtering. The copper seed layer 5 is for forming the copper wiring layer 6 by a plating method. Thereafter, a photoresist layer (photosensitive resin layer) 11 as shown in FIG. 2C is formed on the copper seed layer 5 using PEP. In this photoresist layer 11, in order to form a forward tapered copper wiring layer, a reverse tapered groove 12 is formed which is wider on the bottom side than on the opening side.

  In other words, the cross-sectional shape of the copper wiring layer formed in the subsequent process may be rectangular, but it is a forward tapered shape from the viewpoint of coverage of the interlayer insulating layer laminated after wiring formation and reduction of short circuit defects with the wiring provided in the upper layer. It is desirable to do. For this reason, it is desirable to form the groove 12 in a reverse taper shape. This shape is realized by appropriately adjusting the resist material, exposure conditions, and development conditions.

  Next, as shown in FIG. 2D, the copper wiring layer 6 is formed so as to fill the groove 12 (on the copper seed layer) of the photoresist layer 11 by using an electroless plating method. Note that the copper wiring layer 6 can be similarly formed by using an electrolytic plating method instead of the electroless plating method. The electroless plating method in this case does not require a catalyst treatment because it is deposited on the copper seed layer 5, and also suppresses the non-uniformity of the film thickness distribution which becomes a problem when applied to a large area substrate. Can do.

  Next, as shown in FIG. 3A, the photoresist layer 11 is removed using a stripping solution or the like. In this removal, an ashing process which is a dry process may be used in combination. In addition, when this ashing process is performed, the exposed surfaces of the copper wiring layer 6 and the copper seed layer 5 may be oxidized, and it is desirable to include a step of removing in the immediately following step.

  Next, as shown in FIG. 3B, the copper layer (copper seed layer 5 and copper wiring layer 6) formed on the first copper diffusion prevention layer 3 is etched to at least form the copper seed layer 5. Etch away. As an etching method, it is desirable to use wet etching or electrolytic etching.

  Examples of the wet etching solution for the copper seed layer include an iron chloride etching agent, a copper chloride-hydrochloric acid etching agent, a phosphoric acid-acetic acid-nitric acid etching agent, a hydrofluoric acid-ammonium persulfate-hydrochloric acid, and a sulfuric acid-hydrogen peroxide aqueous etching. A solution such as an agent, peroxosulfate-hydrofluoric acid or the like can be used. Note that when the thick copper wiring layer 6 is wet-etched using a resist mask, side etching is a problem at the edge of the pattern because it is generally isotropic etching. Since it is a thin thin film and is etched at the same time as the metal wiring layer 6, there is almost no problem.

  Note that the copper wiring layer 6 is also etched at the same time as the etching of the copper seed layer 5, but the copper wiring layer 6 is previously formed in the step of FIG. Form thick. In the above embodiment, the copper seed layer is used as the metal seed layer, but instead of the copper seed layer, a group 8a metal seed layer capable of direct plating of copper such as a nickel seed layer or a cobalt seed layer is used. Needless to say. In the case where a nickel seed layer is also used, it is possible to etch the nickel seed layer almost without etching the copper wiring layer 6 by using a nitric acid-sulfuric acid-hydrogen peroxide-ammonium chloride etching agent or the like. There is an advantage of being. Needless to say, a copper seed layer may be formed thereon using a nickel layer as an adhesion layer.

  In the case of using not only the wet etching method but also the electrolytic etching method, the first copper diffusion prevention layer 3 is formed by applying a predetermined voltage between the first copper diffusion prevention film and the cathode plate (cathode). The copper layer (copper seed layer 5 and copper wiring layer 6) formed thereon is etched. The control of the selectivity between the copper diffusion preventing layer 3, the copper seed layer 5, and the copper wiring layer 6 is easy, and the etching rate is relatively high. At this time, it is desirable that the voltage to be applied is set to a voltage value at which the first copper diffusion prevention layer 3 is not electrolytically etched, for example, about 10 V, although electrolytic etching of the copper layer occurs. As an etching base bath, acids such as sulfuric acid, phosphoric acid, and hydrochloric acid may be used. However, the present invention is not limited to these. Of course, the etching rate ratio between the copper seed layer 5 and the copper wiring layer 6 and the copper wiring layer 6 An additive for controlling the taper shape may be used, or the liquid temperature and applied current waveform may be controlled.

  Next, as shown in FIG. 3 (c), for example, to cover the entire exposed surface of the copper wiring layer 6 and the copper seed layer 5 (the entire periphery other than the bonding surface with the first copper diffusion prevention layer 4), The second copper diffusion prevention layer 7 made of Co-WB is formed to a thickness of, for example, 50 nm by using, for example, an electroless plating method. Since the second copper diffusion preventing layer 7 is formed on the copper wiring layer 6 by a plating method, a material suitable for plating is selected. For example, by using dimethylamine borane as a reducing agent, it is desirable to form the second copper diffusion prevention layer 7 such as Co—WB, which does not require Pd catalyst treatment, by an electroless plating method. Alternatively, a copper diffusion prevention layer such as Co-B, Co-P, Co-WB, Ni-B, Ni-P, or Ni-WP can be selectively electrolessly plated.

  Next, as shown in FIG. 3 (d), the copper wiring layer portion covered with the second copper diffusion preventing layer 7 is made to function as a self-aligned mask, and etching is performed, so that the first portion other than the lower portion of the copper wiring is formed. The copper diffusion prevention layer 4 is removed to form the wiring 1.

  As described above, in the present embodiment, a step of forming a polishing stop film for CMP, which is necessary in the above-described conventional damascene method, before forming the copper diffusion prevention layer, and a groove for embedding the copper wiring are formed. The etching process to form is unnecessary. Further, since CMP in the damascene method uses an abrasive (slurry), it is necessary to clean the abrasive and the object to be polished (including metal ions), but this cleaning step is also unnecessary in this embodiment. . In addition, it is possible to reduce the cause of foreign matter contamination during polishing in the CPM process.

  Therefore, in the present embodiment, a highly reliable metal wiring surrounded by the metal diffusion preventing layer can be formed, and the number of processes can be reduced as compared with the damascene method, and the manufacturing cost can be reduced. Furthermore, the present embodiment can be easily applied to a large-area substrate where it is difficult to use CMP. In the present embodiment described above, copper is described as an example of a wiring material, but of course, the present invention is not limited to this. For example, an alloy containing copper or other metal (gold or metal) that can be formed by a plating method is used. Silver, etc.) can be applied.

Next, wirings and electrodes according to the second embodiment of the present invention will be described.
The wiring and electrodes according to the second embodiment have a structure in which a seed layer is provided similarly to the structure of the wiring and electrodes shown in FIG. 1 described above, and the formation method is different. In the constituent parts and manufacturing steps of the present embodiment, the same reference numerals are assigned to the same parts or the same manufacturing steps as the constituent parts of the first embodiment (FIGS. 1 to 3D) described above, Detailed description thereof is omitted. Moreover, the film thickness of each part which comprises wiring is the same as that of 1st Embodiment mentioned above. Here, a configuration in which wiring is directly provided on a substrate will be described as an example. Of course, these wirings and electrodes are already formed on a circuit element or a part of the circuit element on the substrate, and can also be formed thereon.

With reference to the process diagrams shown in FIGS. 4A to 4D and FIGS. 5A to 5C, the first method for forming the wiring (electrode) in the second embodiment is specifically described. explain.
The process shown in FIG. 4A is the same as the process shown in FIG. 2A. First, a base insulating layer 3 made of a silicon nitride layer (SiN layer) is deposited on the entire surface of the substrate 2, and then the process shown in FIG. A first copper diffusion preventing layer 4 is formed thereon by a sputtering method. Of course, it is not limited to these film forming methods, and other film forming methods such as an evaporation method may be used. As the first copper diffusion preventing layer 4, a Ta layer, a TaN layer, a WN layer, a TaSiN layer, a WSiN layer, a Co alloy layer, a Ni alloy layer, or the like can be used. The substrate 2 and the base insulating layer 3 are collectively referred to as an insulating substrate 10.

The process shown in FIG. 4B is the same as the process shown in FIG. 2C, and the photoresist layer 11 is formed. A groove 12 having a rectangular cross section (vertical side surface) is formed in the photoresist layer 11. Of course, as described above, the groove 12 may have an inversely tapered shape.
In the step shown in FIG. 4C, after removing the oxide film (natural oxide film or the like) on the surface of the first copper diffusion prevention layer 4 exposed at the bottom of the groove 12 of the photoresist layer, an electroless plating method is performed. The copper seed layer 5 is formed on the first copper diffusion preventing layer 4 by using the above method.

In the step shown in FIG. 4 (d), the electrolytic seeding method is further used only on the copper seed layer 5 in the groove 12 of the photoresist layer 11 using the copper seed layer 5 and the first copper diffusion prevention layer 4 as electrodes. A copper wiring layer 6 is formed. Of course, the electroless plating method can be used as it is without changing to the electrolytic plating method.
As shown in FIG. 5A, the photoresist layer 11 is removed using a stripping solution or the like. For this removal, as described above, an ashing process may be used together. However, when this is used together, it is necessary to add an oxide film removing step.

The process shown in FIG. 5B is the same as the process in FIG. 3G, and the entire exposed surface of the copper wiring layer 6 and the copper seed layer 5 (other than the bonding surface with the first copper diffusion prevention layer 4). The second copper diffusion prevention layer 7 made of, for example, Co-WB is formed by using an electroless plating method.
In the step shown in FIG. 5C, the copper wiring layer portion covered with the second copper diffusion preventing layer 7 is made to function as a self-aligned mask, and etching is performed, so that the first copper other than the lower portion of the copper wiring is formed. The diffusion preventing layer 4 is removed.

A second forming method, which is a modified example of the second embodiment, will be described.
In the process shown in FIG. 4C described above, a copper seed layer is formed using an electroless plating method. Further, in FIG. 4D, the seed layer and the first copper diffusion prevention layer 4 are used as electrodes. The copper wiring layer 6 is formed using an electrolytic plating method. Instead of this electroless plating method, a solution for removing the oxide film on the surface of the first copper diffusion prevention layer 4 exposed at the bottom of the groove 12 of the photoresist layer, for example, copper ions, hydrofluoric acid, ammonium fluoride or nitric acid An ultrathin copper seed layer 5 may be formed on the first copper diffusion prevention layer 4 by a displacement plating method using a solution containing the like. Further, the copper seed layer 5 may be formed with copper nuclei to the extent that the electroless plating method in the next step can be applied.

A third forming method, which is a modification of the second embodiment, will be described.
In the process shown in FIG. 4C described above, the copper seed layer 5 is formed by the displacement plating method. Alternatively, a CVD method using an organometallic material may be used. As an organic metal raw material of copper (Cu), for example, trimethylvinylsilyl hexafluoroacetylacetonato copper (Cu (hfac) TMVS), which is a monovalent complex raw material of copper, is used, for example, at a low temperature of about 140 ° C. By forming a film, it is possible to achieve film formation selectivity between a conductive material such as a copper diffusion prevention layer and an insulating material such as a photoresist or an oxide film at the beginning of film formation. In other words, the film thickness on the conductive material is proportional to the film formation time, but on the insulating material, there is a latent period in which no film is formed at the beginning of film formation. Selectivity occurs without being proportional to. However, after a copper layer is formed by nucleus growth on the insulating material, that is, after the incubation time has elapsed (for example, after 2 to 60 minutes), the film is formed at almost the same film formation speed as that on the conductive material. Is done. For this reason, it is desirable to selectively form a copper seed layer within a latent period in which the degree of progress of nucleus growth is low.

  Also in the second embodiment, it is possible to obtain the same effects as those of the first embodiment described above. In addition, since the present embodiment can be selectively formed in the region where the copper seed layer and the copper wiring layer are to be formed, the etching process step in the copper seed layer can be omitted, and the manufacturing cost can be reduced. Useful for reduction.

Next, wirings and electrodes according to the third embodiment of the present invention will be described.
FIG. 6 shows a cross-sectional configuration of wirings and electrodes according to the third embodiment. The wiring and electrodes according to the third embodiment have a structure in which the copper seed layer in the first embodiment described above is not provided. Here, a configuration in which wiring is directly provided on a substrate will be described as an example. Of course, these wirings and electrodes are already formed on a circuit element or a part of the circuit element on the substrate, and can also be formed thereon.

  In the wiring 21, a base insulating layer 23 is provided on a substrate 22 made of glass or the like. A first copper diffusion prevention layer 24 along the wiring pattern is provided on the base insulating layer 23, and a copper wiring layer 25 slightly narrower than the width of the first copper diffusion prevention layer 24 is laminated on the upper surface. Next, a second copper diffusion prevention layer 26 is provided so as to cover the entire surface of the copper wiring layer 25.

In such a configuration, the wiring 21 has a three-layer structure in which the copper wiring layer 25 is surrounded by the first copper diffusion prevention layer 24 and the second copper diffusion prevention layer 26 (enclosed or encapsulated). For this reason, when incorporated in a circuit, it is possible to prevent the influence of deterioration of characteristics of other circuit elements such as TFTs due to copper diffusion. The electrodes according to the present embodiment can be applied to, for example, low resistance gate electrodes and source / drain electrodes of amorphous silicon TFTs and polysilicon TFTs.
The thickness of each layer of the wiring 21 is, for example, 400 nm for the base insulating layer 23, 50 nm for the first copper diffusion prevention layer 24, 400 nm for the copper wiring layer 25, and 50 nm for the second copper diffusion prevention layer 26.

Next, with reference to the process diagrams shown in FIGS. 7A to 7D and FIGS. 8A to 8C, a method for forming the wiring 21 in the third embodiment will be specifically described. .
In the present embodiment, a metal wiring layer is selectively formed on the first copper diffusion prevention layer using an electroless plating method using a photosensitive resin or an inorganic insulating layer as a mask. This is a method of forming a wiring formed so as to be covered with a second copper diffusion preventing layer.

  First, in the step shown in FIG. 7A, after a base insulating layer 23 made of a silicon nitride layer (SiN layer) is deposited on the entire surface of the substrate 22 by PE (Plasma-Enhanced) -CVD, As shown in FIG. 7B, the first copper diffusion prevention layer 24 is formed by sputtering or the like. As the first copper diffusion preventing layer 24, a Ta layer, a TaN layer, a TiN layer, a TaSiN layer, a WSiN layer, a Co alloy layer, a Ni alloy layer, or the like can be used. The substrate 22 and the base insulating layer 23 are collectively referred to as an insulating substrate 30.

  In the step shown in FIG. 7C, a photoresist layer 31 is formed on the first copper diffusion preventing layer 24 by using the PEP method. The photoresist layer 31 is formed with a reverse-tapered groove 32. Of course, the groove 32 may have a vertical shape, but a reverse taper shape is preferred. This is because, as described above, the metal wiring layer preferably has a forward taper shape from the viewpoint of the coverage of the interlayer insulating layer formed in the upper layer and the reduction of short-circuit defects with the upper layer wiring.

  In the step of FIG. 7D, the copper wiring layer 25 is formed on the bottom of the groove 32 of the photoresist layer 31 by using an electroless plating method. When a direct plating film is formed on the first copper diffusion prevention layer 24 by the electroless plating method, a Pd catalyst treatment is usually performed. However, it is desirable to avoid the problem that Pd diffuses in the copper wiring and degrades the specific resistance value in the heat treatment performed in the subsequent process. Therefore, instead of the Pd catalyst treatment, it is desirable to perform the electroless plating treatment after performing the treatment for removing the oxide film on the extreme surface on the first copper diffusion preventing layer. For the removal treatment of the oxide film, a solution containing hydrofluoric acid or the like may be used. Alternatively, the copper wiring layer 25 may be formed using an electroless plating method after copper ions are contained in a solution containing hydrofluoric acid and ammonium fluoride or nitric acid to form a thin copper seed layer or copper nucleus. Good. Of course, as the first copper diffusion prevention layer 24, a Co alloy (for example, Co-B or Co-WB, or Co-B / Co), a Ni alloy (for example, Ni-B or Ni-B / Ni), or the like. If is used, direct plating is possible.

In the step shown in FIG. 8A, the photoresist layer 31 is removed using a stripping solution or the like. For this removal, an ashing process may be used in combination.
In the step shown in FIG. 8B, the second copper diffusion made of, for example, Co—W—B, Co—B or the like is used so as to cover the entire exposed surface of the copper wiring layer 25 using an electroless plating method. The prevention layer 26 is formed. Here, it is desirable to form a copper diffusion prevention layer made of Co—WB, Co—B, or the like that does not require Pd catalyst treatment by an electroless plating method, but the copper wiring layer is selectively plated. What can be formed and becomes a copper diffusion prevention layer is good.

  In the step shown in FIG. 8C, etching is performed using the second copper diffusion prevention layer 26 that covers the copper wiring layer portion as a mask, and the first copper diffusion prevention layer 24 other than the lower part of the copper wiring is exposed. The wiring 21 is formed by removing the existing region by etching. As the first copper diffusion prevention layer 24, a Co alloy (for example, Co—B or Co—WB, or Co—B / Co), a Ni alloy (for example, Ni—B or Ni—B / Ni), or the like is used. In this case, as shown in FIG. 13C, the second copper diffusion prevention layer 26 may be formed after etching the first copper diffusion prevention layer 24 using the copper wiring layer as a mask.

  As the electroless plating bath for forming the copper wiring layer 25 described above, formaldehyde may be used as a reducing agent. However, since formaldehyde is harmful to the human body and the plating pH conditions are 12 to 13, it is necessary to use an alkali metal such as sodium when considering application to the TFT process, such as using sodium hydroxide as a pH adjuster. It is desirable to use those not present. Therefore, as a plating bath that does not contain harmful substances and does not use an alkali metal, a glyoxylic acid bath using glyoxylic acid as a reducing agent and an organic alkali (eg, TMAH) as a pH adjusting agent, a cobalt salt as a reducing agent, It is desirable to use a cobalt salt bath or a tin salt bath using a tin salt.

However, organic alkali (TMAH), the pH adjuster of the glyoxylic acid bath, dissolves the photoresist mask, so that a photosensitive resin resistant to organic alkali is used, or an inorganic insulating film mask such as silicon nitride or silicon oxide. It is desirable to use. A cobalt salt bath using a cobalt salt as a reducing agent is desirable as an optimum plating bath for the TFT process because the plating pH condition is in a neutral region of 6 to 7 and damage to the photoresist mask is small. . In addition, cobalt salt baths and tin salt baths do not generate hydrogen due to decomposition of the reducing agent during the plating reaction process, unlike formaldehyde baths and glyoxylic acid baths. It is a plating bath that can be suppressed.

  The third embodiment described above can obtain the same effects as those of the first embodiment described above, and can form a wiring using copper as a wiring layer material without using the CMP method. In addition, the present invention can be applied to a large-area substrate that is difficult to perform by CMP. Therefore, the number of manufacturing steps can be reduced as compared with the conventional case, and the manufacturing cost can be reduced.

  It should be noted that the present embodiment is not limited to the above described items, and it is needless to say that various modifications can be made without departing from the spirit of the present embodiment. For example, although an example in which copper is used as a wiring material has been described, an alloy containing copper and other metals can be easily applied.

  The wirings and electrodes in the first to third embodiments described above can be applied to a display device, for example, an active matrix liquid crystal display device (LCD). Of course, the present invention can be applied not only to this liquid crystal display device but also to wirings in inorganic ELDs and organic ELDs.

  FIG. 9 shows an example of an equivalent circuit of a general active matrix LCD (an auxiliary capacitor is not shown). The wiring of the present invention can be applied to a plurality of signal lines formed on an array substrate, a plurality of scanning lines, and gate electrodes, source / drain electrodes, etc. in TFTs arranged in a matrix.

  Here, a first application example in which the wiring structure of the present invention is applied to a polysilicon TFT will be described. 10 (a) to 10 (d) and FIGS. 11 (a) to 11 (c) show the formation of a MOS structure p-type TFT using the metal (copper) wiring layer of the present invention for the gate electrode and the source / drain electrodes. A method will be described.

  After the base insulating layer 41 is deposited on the substrate 40, an amorphous silicon layer 42 serving as an active layer is deposited thereon. After these are deposited, annealing is performed in an atmosphere at a temperature of 500 ° C. to desorb hydrogen in the amorphous silicon layer 42.

  Further, after the amorphous silicon layer 42 is crystallized into a polysilicon layer 42a by ELA (Excimer Laser Anneal) method and a resist mask is formed by PEP, the polysilicon layer 42a is formed into an island shape by CDE (Chemical Dry Etching) method. To process. Thereafter, a gate insulating layer 43 is deposited on the entire surface by PE-CVD. The gate insulating layer may be a single silicon oxide layer, but it is desirable to use a multilayer structure including an insulating layer such as a silicon nitride layer having a diffusion blocking capability against copper diffusion.

  In the step shown in FIG. 10B, after the first copper diffusion prevention layer 44 is formed by the formation method in each of the embodiments described above, a photoresist layer (mask) 45 is formed by PEP. A copper wiring layer 47 is selectively formed in the opening 46 of the photoresist layer 45 by using an electroless plating method or an electrolytic plating method. In the case of forming a film by electrolytic plating, a seed layer is formed in advance as in the first and second embodiments described above.

In the step shown in FIG. 10C, after the photoresist layer 45 is removed, the second copper diffusion prevention layer 48 is formed so as to cover the entire surface of the copper wiring layer 47 by using an electroless plating method.
In the step shown in FIG. 10D, the gate electrode 49 is formed by etching the unnecessary first copper diffusion preventing layer using the second copper diffusion preventing layer 48 as an etching mask.

  In the step shown in FIG. 11A, using the copper wiring layer 47 surrounded by the second copper diffusion preventing layer 48 as a mask, boron is ion-doped into the polysilicon layer 42a to form impurity regions (source / drain regions) 42b. Form.

  In the step shown in FIG. 11B, the interlayer insulating layer 50 is formed using the PE-CVD method. Of course, the interlayer insulating layer may be a single layer of silicon oxide layer, but it is desirable to use a multilayer structure including an insulating layer such as a silicon nitride layer having a diffusion blocking capability against copper diffusion. Further, a mask (not shown) made of a PEP photoresist layer is formed on the interlayer insulating layer 50, and the interlayer insulating layer 50 is etched to form contact holes 51 that open to the surface of the source and drain regions 42b. .

  In the step shown in FIG. 11C, after the formation of the contact hole 51 of the interlayer insulating layer 50, the third metal diffusion prevention layer 52 is formed in the same manner as in the third embodiment, and a mask using a photoresist layer is further formed. Then, the copper wiring layer 53 is selectively formed in the groove portion of the photoresist layer by using an electroless plating method. Further, after the fourth copper diffusion prevention layer 54 is selectively formed so as to surround the copper wiring layer 53 by using an electroless plating method, the third metal diffusion prevention layer 52 is etched, so that the source / drain is formed. An electrode is formed.

  Through the steps as described above, a MOS structure p-type TFT including the gate electrode 49 and the source / drain electrodes 58 using the copper wiring of the present invention can be formed. The wiring formation method has been described in the third embodiment, but the first or second embodiment may be used.

  Although not shown, after the formation of the source / drain electrodes, for example, an interlayer insulating layer 82 such as silicon nitride is formed, and then a contact hole 83 for connection to the pixel electrode is opened to form the second The metal diffusion preventing layer 84 is exposed. Next, a transparent conductor layer 86 made of ITO (indium tin oxide), tin oxide or the like is formed by using, for example, a sputtering method and patterned to form an array substrate for a transmissive liquid crystal display device or the like. can do.

At this time, as shown in FIG. 12, the copper wiring layer 85 and the second wiring layer 85 are also formed on the copper wiring layer 85 covered with the display device and the second metal diffusion prevention layer 84 of the external connection terminal portion. It is preferable to function as a protective film for the metal diffusion prevention layer 84. In FIG. 12, a single copper wiring layer is shown as an example, but a two-layer structure of scanning lines and signal lines may be used.

Further, instead of a transparent metal oxide film such as ITO, a reflective metal used in a reflective liquid crystal display device or the like, for example, a metal layer containing aluminum (Al) or silver (Ag) may be stacked.
The wirings and electrodes of the present invention are not limited to the LCD as described above, but also include organic ELDs, such as signal lines, power supply lines, scanning lines, and TFT electrodes formed on an active matrix organic ELD substrate. It can be easily applied to peripheral wiring and wiring in a peripheral driving circuit formed on the same substrate.

  According to the wiring and electrode forming method of the present invention, it is possible to form a metal wiring made of a highly reliable low-resistance material surrounded by a metal diffusion prevention layer, and further, as in the conventional damascene method, CMP (chemical Metal wiring can be selectively formed on a substrate without using a mechanical mechanical polishing method, and metal wiring made of copper or the like of low resistance wiring can be formed even on a large area substrate where CMP is difficult. Can be realized. Further, the wiring can be selectively formed on the substrate without using CMP, and the removal / discarding of the wiring material is suppressed, and the resource of the wiring material can be saved.

  In each of the above-described embodiments, the second copper diffusion prevention layer is used to prevent the surface of the copper wiring layer formed on the upper layer from being damaged when the first copper diffusion prevention layer is etched. Is used as a mask (protective layer), but it is not limited to the order of this manufacturing process. That is, as shown in FIGS. 13A to 13C, etching (wet etching or dry etching) that does not damage the copper wiring layer is performed during the etching process for removing the first copper diffusion prevention layer. If it is adopted, it is not necessary to function the second copper diffusion prevention layer as a mask, and therefore, it may be a manufacturing process for forming the second copper diffusion prevention layer after the etching of the first copper diffusion prevention layer. .

  That is, following the step shown in FIG. 7D, after the copper wiring layer 25 is formed on the first copper diffusion prevention layer 24 as shown in FIG. 13A, as shown in FIG. 13B. Etching that does not damage the copper wiring layer 25 is performed to remove the first copper diffusion prevention layer 24 other than that in contact with the copper wiring layer 25. Thereafter, a second copper diffusion prevention layer 26 is formed so as to cover the first copper diffusion prevention layer 24 and the copper wiring layer 25 as shown in FIG.

Further, instead of forming the copper wiring in the mask opening of the photoresist layer, a manufacturing process may be performed in which the copper wiring is formed and the photoresist layer is left only in a desired region and etched. FIG. 13 which is the first modification example is a configuration example in which the seed layer is not used, but as a second modification example, FIG. 14 shows a gap between the first copper diffusion prevention layer 24 and the copper wiring layer 25. 2 shows a configuration example in which a seed layer 27 is provided.
In FIG. 2 described above, copper (Cu) is used for the seed layer 27, but cobalt (Co) or nickel (Ni) may be used.
The technology for forming the wiring according to the first and second embodiments as described above can be easily applied to electrodes and display devices.
Such a wiring structure provided with a metal seed layer can be applied to a display device such as an active matrix liquid crystal display device (LCD). Of course, this wiring structure can also be applied to wiring in inorganic ELD and organic ELD. An example of this LCD is equivalent to the equivalent circuit shown in FIG. 9 described above, and is omitted here. Such a wiring structure can be applied to a plurality of signal lines, a plurality of scanning lines formed on the array substrate, a gate electrode, a source / drain electrode, etc. in a TFT arranged in a matrix.

  Here, a second application example in which the wiring structure of the present invention is applied to a polysilicon TFT will be described. 15 (a) to 15 (e) and FIGS. 16 (a) and 16 (b), a MOS structure p-type TFT using the metal (copper) wiring layer of the present invention for the source / drain electrodes is described. A forming method will be described.

  In the step shown in FIG. 15A, after depositing a base insulating layer 92 on a substrate 91, an amorphous silicon layer 93 'serving as an active layer is deposited thereon. After these are deposited, annealing is performed in an atmosphere at a temperature of 500 ° C. to desorb hydrogen in the amorphous silicon layer 93 ′.

  Further, the amorphous silicon layer 93 ′ is crystallized into a polysilicon layer 93 by an ELA (Excimer Laser Anneal) method, a mask (not shown) made of a photoresist is formed by PEP, and a CDE (Chemical Dry Etching) method is performed. Using this, the polysilicon layer 93 is processed into an island shape. Thereafter, a gate insulating layer 94 is deposited on the entire surface by PE-CVD.

  In the step shown in FIG. 15B, a gate electrode layer 95 (for example, MoW) is formed on the entire surface of the gate insulating layer 94, and a mask (not shown) made of a PEP photoresist is provided thereon. A gate electrode is formed by etching the gate insulating layer 94 exposed from the mask using a CDE method or the like. The gate electrode 95 may be made of copper, and a barrier layer and a Cu seed layer may be provided under the electrode.

  In FIG. 15C, impurity regions (source / drain regions) 93a are formed by ion doping boron into the polysilicon layer 93 using the gate electrode 95 as a mask to activate the impurities.

  In the step shown in FIG. 15D, an interlayer insulating layer 96 is formed on the entire surface by PE-CVD. Further, a mask (not shown) made of a PEP photoresist is formed on the interlayer insulating layer 96, and the exposed interlayer insulating layer 96 is etched to form contact holes 97 that open to the surface of the source and drain regions 93a. Form.

  In the step shown in FIG. 15 (e), a stack composed of a Co layer 98 (thickness 20 nm) and a Co—B layer 99 (thickness 50 nm) functioning as the first copper diffusion prevention layer 100 is formed by sputtering and non-sputtering, respectively. It is formed by electrolytic plating.

  In the step shown in FIG. 16A, a Cu seed layer 102 (with a thickness of 50 nm) is formed on the entire surface, and a mask 103 made of a photoresist is formed by PEP. A copper wiring layer 104 (thickness 500 nm) is selectively formed on the region where the mask 103 is opened by using an electroless plating method or an electrolytic plating method.

  In the step shown in FIG. 16B, after the mask 103 is removed, the Cu seed layer 102 and the Co layer 98 and the Co—B layer 99 as the first copper diffusion prevention layer 100 are etched using the copper wiring layer 104 as a mask. To do. Further, by using an electroless plating method, a first layer made of Co-B, Co-WB, or the like is formed so as to cover the entire exposed surface including the side surfaces of the Cu seed 102, the copper wiring layer 47, and the first copper diffusion prevention layer 100. By forming the second copper diffusion prevention layer 105, the source / drain electrodes 106 are formed. Then, the Co silicide layer 101 is formed at the interface between the Co layer 98 and the source and drain regions 93a by the heat treatment process, thereby realizing a reduction in resistance of the source / drain and an improvement in diffusion preventing ability.

  Although not shown, in the above process, after forming the Cu seed layer 102 on the Co-B layer 99, the copper wiring layer 104 is formed on the Cu seed layer 102 using a mask made of a photoresist. The copper wiring layer 104 may be formed directly on the Co—B layer 99 using a mask made of a photoresist. Then, after etching the Co layer 98 and the Co-B layer 99 which are the first copper diffusion prevention layer 100 using the copper wiring layer 104 as a mask, the copper wiring layer 47 and the first copper diffusion prevention layer 100 are etched. A second copper diffusion prevention layer 105 made of Co-B or the like may be formed so as to cover the entire exposed surface including the side surfaces.

  Further, instead of the Co layer 98 and the Co—B layer 99 of the above-described embodiment, a Ni layer and a Ni—B layer may be used. Further, the second copper diffusion prevention layer 105 is made of Ni—B or the like. An alloy may be used. When a Ni layer is used as a part of the first copper diffusion prevention layer 100, the silicide layer formed by the heat treatment process becomes a Ni silicide layer. As the silicide layer, a Ta silicide layer, a Ti silicide layer, or the like may be used.

Although not shown, after forming the source / drain electrodes 106, an interlayer insulating layer such as silicon nitride or benzocyclobutene resin is formed, and then contact holes for connection to the pixel electrodes are opened. Then, the second metal diffusion preventing layer is exposed. Further, for example, by using a sputtering method, a transparent conductor layer such as ITO (indium tin oxide) or tin oxide is formed and patterned to form an array substrate for a transmissive liquid crystal display device or the like. Can do.

  DESCRIPTION OF SYMBOLS 1,21 ... Wiring, 2,22 ... Substrate, 3,23 ... Underlying insulating layer, 4, 24 ... First copper diffusion prevention layer, 5 ... Copper seed layer, 6, 25 ... Copper wiring layer, 7, 26 ... 2nd copper diffusion prevention layer, 11, 31 ... Photoresist layer (photosensitive resin layer), 12, 32 ... Groove.

Claims (8)

Forming a first metal diffusion prevention layer on the substrate;
Subsequent to the step, using a resist pattern, a metal seed layer having a predetermined pattern so as to fill the resist pattern on the first metal diffusion prevention layer is formed using a CVD method, and on the metal seed layer. Sequentially forming a metal wiring layer using an electroless plating method or an electrolytic plating method;
Etching the first metal diffusion prevention layer other than the region overlapping the metal wiring layer in a plane;
Forming a second metal diffusion prevention layer so as to cover an exposed surface including at least the metal seed layer and the side surface of the metal wiring layer;
A method of forming a wiring comprising the steps of: In the method for forming the wiring,
The step of forming the first metal diffusion prevention layer includes:
The method of forming a wiring according to claim 1, which is performed after a step in which another circuit element or a part of another circuit element is formed on the substrate. In the method for forming the wiring,
The wiring forming method according to claim 1, wherein the cross-sectional shape of the opening of the pattern that defines the cross-sectional shape of the metal wiring layer is formed in a rectangular shape or an inversely tapered shape. In the method for forming the wiring,
2. The method of forming a wiring according to claim 1, wherein the metal wiring layer is formed by an electroless plating bath containing no alkali metal using cobalt salt, tin salt or glyoxylic acid as a reducing agent. In the method for forming the wiring,
The method of forming a wiring according to claim 1, wherein the metal seed layer is selectively formed on the first metal diffusion prevention layer exposed from the resist pattern. In the method for forming the wiring,
The wiring formation method according to claim 5, wherein trimethylvinylsilylhexafluoroacetylacetonate copper is used for the metal seed layer. A method of forming a display device having electrodes of pixel driving elements arranged in a matrix, scanning lines connected to the driving elements, and signal lines,
Forming a first metal diffusion prevention layer;
Following the step, a metal to be one of the electrode, the scanning line, and the signal line having a predetermined pattern so as to fill the resist pattern on the first metal diffusion prevention layer using a resist pattern A step of sequentially forming a seed layer using a CVD method and a metal wiring layer on the metal seed layer using an electroless plating method or an electrolytic plating method;
Removing at least the first metal diffusion prevention layer other than being bonded to the metal wiring layer by etching;
Forming a second metal diffusion prevention layer so as to cover an exposed surface including at least the metal seed layer and a side surface of the metal wiring layer;
A method for forming a display device having wiring, comprising:   8. The method for forming a display device having a wiring according to claim 7, further comprising the step of siliciding at least a part of the first metal diffusion preventing layer.

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