JP2005012012A - Thin film transistor, display apparatus, and method for forming them - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor the electrodes of which are selectively formed. <P>SOLUTION: The thin film transistor 10 is provided with a semiconductor layer 22, a gate insulation film 21, a gate electrode 20, a source electrode 23, and a drain electrode 24 on the precondition that the thin film transistor 10 is provided above an organic resin layer 15 which a substrate 14 to be processed includes. The gate electrode 20 is provided with: a seed layer 31 formed by reducing at least parts of selectively introduced metal ions to at least part of the organic resin layer 15, and provided to the substrate 14 to be processed in a way of including an exposed part exposed from the organic resin layer 15; and a metallic layer 32 provided to at least part on the seed layer 31. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor, a display device such as a liquid crystal display device, and a method for forming them.
[0002]
[Prior art]
In recent years, in the field of display devices typified by liquid crystal display devices and the like, a gate electrode, a source electrode, or a drain electrode included in a thin film transistor (hereinafter referred to as TFT) has a lower resistance than aluminum (Al) and Formation of copper (Cu) excellent in migration resistance, silver (Ag), which has a lower resistance than aluminum, and the like has been studied.
[0003]
However, a conventionally known method for forming an aluminum thin film, that is, a PEP (Photo Engraving Process) so-called photolithography masking technique and an etching technique such as a reactive ion etching method are simply combined. With this method, it is difficult to realize a copper thin film.
[0004]
That is, the vapor pressure of copper halide is very low compared to the vapor pressure of aluminum. That is, copper halides are less likely to evaporate than aluminum. Therefore, when an etching technique such as a reactive ion etching method is used as a method for forming a copper thin film, an etching process is required in an atmosphere of 200 to 300 ° C. as a process temperature. In this case, it is necessary to use a mask made of silicon oxide, silicon nitride or the like instead of a normal photoresist mask. As described above, there is a problem when a conventionally known method for forming an aluminum thin film is applied to the formation of a copper thin film.
[0005]
For this reason, a so-called damascene method is conventionally known as a method for forming a copper thin film. In this method, first, a groove having a desired pattern is formed in advance on an insulating film formed on a substrate. Next, copper is formed over the entire surface of the groove and on the insulating film so as to fill the groove. At this time, as a method of forming copper over the entire surface of the groove and on the insulating film, a PVD (Physical Vapor Deposition) method such as a sputtering method, a plating method, a CVD method using an organic metal material, or the like. There are various methods. Thereafter, the copper on the substrate surface is removed from the substrate surface side until the insulating film is exposed (up to the opening end face of the buried groove portion). As a method for removing copper from the substrate surface, there are polishing methods such as chemical mechanical polishing (CMP), etch back, and the like. In this way, a thin film made of copper embedded in the groove is formed (see, for example, Patent Document 1 and Patent Document 2).
[0006]
Many display devices are currently formed by forming an amorphous silicon TFT using amorphous silicon as a semiconductor film or a polysilicon TFT using polysilicon as a semiconductor film on a glass substrate. On the other hand, in recent years, efforts have been made to form a flexible display device by forming an organic TFT using an organic semiconductor film on a flexible organic resin substrate.
[0007]
The organic TFT is generally composed of a substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and an organic semiconductor film. As such an organic TFT, one using a soluble polythiophene as an organic semiconductor and a polyimide coating film as a gate insulating film is known (for example, see Patent Document 3).
[0008]
In addition, the electrode has an inverted stagger structure and a material having a large work function as an electrode material (for example, gold (Au), platinum (Pt), silver (Ag), copper (Cu), palladium (Pd), etc. ) Can be formed at a low temperature. Utilizing this fact, an organic TFT formed on a flexible organic resin substrate such as a plastic substrate having a heat resistant temperature lower than that of glass is known (see, for example, Patent Document 4).
[0009]
However, when the structure of the electrode is an inverted staggered structure, there is a problem that the conventional processing process cannot be applied to the process of forming the electrode on the semiconductor film. For this reason, it is necessary to form electrodes by a mask vapor deposition method using a metal mask or the like, and it is difficult to realize miniaturization of TFT, improvement of pattern accuracy, reduction of variation, and the like.
[0010]
Therefore, a method of forming a copper thin film on a polyimide substrate is known as a method of forming a metal thin film having a large work function on an organic resin substrate. In this method, first, the surface of the polyimide substrate is subjected to ion exchange group introduction treatment with potassium hydroxide (KOH). Further, copper ions are introduced into the surface of the polyimide substrate subjected to the ion exchange group introduction treatment using a copper ion-containing liquid. Then, a copper thin film is formed on a polyimide substrate by reducing the introduced copper ions (see, for example, Patent Document 5).
[0011]
[Patent Document 1]
JP 11-135504 A (paragraphs 0014 to 0029, FIGS. 1 and 2)
[0012]
[Patent Document 2]
Japanese Unexamined Patent Publication No. 2001-189295 (paragraphs 0004 to 0009, FIG. 1)
[0013]
[Patent Document 3]
JP-A-10-190001 (paragraphs 0014 to 0021, FIGS. 1 to 4)
[0014]
[Patent Document 4]
JP 2000-269515 A (paragraphs 0008 to 0017, FIGS. 2 to 6)
[0015]
[Patent Document 5]
JP 2002-192648 A (paragraph 0042 to paragraph 0056)
[0016]
[Problems to be solved by the invention]
However, when forming the electrode of TFT by the prior art disclosed in Patent Document 1 and Patent Document 2 described above, there are the following problems.
[0017]
In the damascene method as described above, the process such as CMP for removing unnecessary portions after forming copper on the entire surface of the substrate has a problem that the process throughput is poor. In addition, a large-sized CMP apparatus corresponding to a large-diameter wafer size of about 12 inches in diameter has been developed. However, a CMP apparatus corresponding to a glass substrate having a larger area and inferior in flatness or the like than the wafer is put into practical use. It has not been. Further, even if it is possible to apply the whole surface polishing by CMP or the etching method to a large glass substrate for manufacturing a display device, for example, a large liquid crystal display device, the copper portion used as an electrode is equal to the area of the substrate. Since it is very small in comparison, most of the deposited copper is removed and discarded. As a result, the utilization efficiency of copper as a raw material becomes very poor, and the product price increases due to the high cost.
[0018]
Moreover, a groove processing step for forming a groove for embedding a metal, a film formation step for forming a via (plug), a photolithography step, an etching step, and a film formation step for a polishing stopper film are necessary. The manufacturing process is complicated.
[0019]
On the other hand, when a TFT electrode is formed by the technique disclosed in Patent Document 5 described above, there are the following problems.
[0020]
The technique of Patent Document 5 requires a step of removing copper ions remaining on the polyimide substrate without being reduced. Moreover, when removing copper ions remaining on the polyimide substrate without being reduced, the utilization efficiency of copper ions as a raw material is deteriorated.
[0021]
Further, potassium hydroxide (KOH) used for ion-exchange group introduction treatment on the polyimide substrate surface is not completely removed even if it is replaced with copper ions. For this reason, residual potassium ions may diffuse into the copper thin film forming the electrode.
[0022]
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a thin film transistor, a display device, and a method for forming the same that can selectively form a wiring structure such as an electrode or a wiring.
[0023]
[Means for Solving the Problems]
A thin film transistor of the present invention based on the first aspect is a thin film transistor provided above the organic resin portion of a substrate to be processed having an organic resin portion in at least a part of a portion exposed to the outside, and includes a semiconductor layer A gate insulating film, a gate electrode, a source electrode, and a drain electrode, and at least one of the gate electrode, the source electrode, and the drain electrode is the organic resin portion. A seed layer provided on the substrate to be processed so as to have an exposed portion exposed from the organic resin portion, wherein at least a portion of metal ions selectively introduced into at least a portion of the organic resin portion is reduced; And a metal layer provided on at least a part of the seed layer.
[0024]
“Processed substrate having an organic resin part in at least a part of a portion exposed to the outside” means a substrate to be processed and an organic resin material having an organic resin layer laminated on at least a part of the substrate. The to-be-processed substrate etc. which consist of can be used. When the substrate to be processed is a substrate to be processed having a base and an organic resin layer laminated on at least a part of the base, the “organic resin portion” refers to the organic resin layer. When the substrate to be processed is a substrate to be processed made of an organic resin material, the “organic resin portion” refers to the substrate to be processed itself made of an organic resin material.
[0025]
According to the present invention, the seed layer can be selectively provided on the substrate to be processed by reducing the metal ions selectively introduced into at least a part of the organic resin portion. Further, since the seed layer can be selectively provided on the substrate to be processed, the metal layer can be selectively provided on the substrate to be processed using the seed layer as a nucleus.
[0026]
Therefore, according to the present invention, at least one of the gate electrode, the source electrode, and the drain electrode is selectively provided on the organic resin portion of the substrate to be processed having the organic resin portion at least in part. it can.
[0027]
According to a second aspect of the present invention, there is provided a method for forming a thin film transistor, comprising: preparing a substrate to be processed having an organic resin portion in at least a part of a portion exposed to the outside; and gate insulation on one side of the gate electrode. Forming a semiconductor layer through a film, forming a source electrode so as to be in contact with the semiconductor layer, and forming a drain electrode so as to be in contact with the semiconductor layer. The step of forming a gate electrode on the processing substrate is performed by selectively introducing metal ions into at least a part of the organic resin portion, so that the metal ions are formed on the substrate to be exposed so as to have an exposed portion exposed to the outside. A step of forming an introduction portion, a step of reducing at least a portion of the exposed portion of the metal ion introduction portion to form a seed layer, and a step of forming a metal layer on at least a portion of the seed layer. When, characterized by comprising comprises a.
[0028]
According to a third aspect of the present invention, there is provided a method for forming a thin film transistor, comprising: preparing a substrate to be processed having an organic resin portion at least in a portion exposed to the outside; and a source electrode on the substrate to be processed Forming a drain electrode on the substrate to be processed, forming a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating film on one side of the semiconductor layer Forming a gate electrode via the at least one of the step of forming a source electrode on the substrate to be processed and the step of forming a drain electrode on the substrate to be processed. A process of forming a metal ion introduction portion on the substrate to be processed so as to have an exposed portion exposed to the outside by selectively introducing metal ions into at least a part of the organic resin portion. And forming a seed layer by reducing at least a part of the exposed part of the metal ion introduction part, and forming a metal layer on at least a part of the seed layer. Features.
[0029]
According to these inventions, the seed layer is formed on the substrate to be processed by reducing at least a portion of the exposed portion of the metal ion introduction portion selectively formed on at least a portion of the organic resin portion of the substrate to be processed. It can be formed selectively. In addition, since the seed layer can be selectively formed on the substrate to be processed, the metal layer can be selectively formed on the substrate to be processed using the seed layer as a nucleus.
[0030]
Thus, according to these inventions, at least one of the gate electrode, the source electrode, and the drain electrode is selectively formed on the organic resin portion of the substrate to be processed having at least a portion of the organic resin portion. Can be formed.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. Hereinafter, in the first to fourth embodiments, an example in which the present invention is applied to a liquid crystal display device as a display device is shown.
[0032]
1 and 2 show an active matrix type liquid crystal display device 1. The liquid crystal display device 1 includes a pair of transparent substrates 2 and 3 as a pair of substrates, a liquid crystal layer 4, a base insulating layer 5, a pixel electrode 6, a scanning wiring 7, a signal wiring 8, a counter electrode 9, a thin film transistor (Thin Film Transistor). (Hereinafter, referred to as TFT) 10, a scanning line driving circuit 11, a signal line driving circuit 12, a liquid crystal controller 13, and the like.
[0033]
As the pair of transparent bases 2 and 3, for example, a pair of glass plates, an insulating substrate such as an organic resin substrate can be used. These bases 2 and 3 are joined via a frame-shaped sealing material (not shown). The liquid crystal layer 4 is provided in a region surrounded by the sealing material between the pair of transparent substrates 2 and 3.
[0034]
On the inner surface of one of the pair of transparent substrates 2 and 3, for example, the transparent substrate 3 on the rear side (lower side in FIG. 2), the base insulating layer 5 is provided in a matrix in the row and column directions. The plurality of pixel electrodes 6, the plurality of TFTs 10 electrically connected to the plurality of pixel electrodes 6, the scanning wiring 7 electrically connected to the plurality of TFTs 10, and the signal electrically connected to the plurality of TFTs 10 Wiring 8 and the like are provided.
[0035]
As the base insulating layer 5, for example, silicon nitride (SiNx) or the like can be used. In the case of a transmissive liquid crystal display device, the pixel electrode 6 may be a transparent electrode such as ITO (indium tin oxide). In the case of a reflective liquid crystal display device, the pixel electrode 6 may be an electrode made of a reflective metal such as aluminum (Al) or silver (Ag). The scanning wirings 7 are provided along the row direction of the pixel electrode 6 (left and right direction in FIG. 1). One end of each scanning line 7 is electrically connected to the scanning line driving circuit 11.
[0036]
The scanning wiring 7 is provided integrally with the gate electrode 20 provided in the TFT 10. The scanning wiring 7 and the gate electrode 20 have a seed layer 31, a metal layer 32, and a cover metal layer 34. The cover metal layer 34 may be omitted.
[0037]
The metal layer 32 has a specific resistance such as a conductor layer including at least one of copper, (Cu), silver (Ag), gold (Au), platinum (Pt), and palladium (Pd). By using a low conductor layer, a wiring designed in advance can be selectively formed. Note that including at least one of copper, silver, gold, platinum, and palladium means a simple substance of copper, silver, gold, platinum, and palladium, and at least one of copper, silver, gold, platinum, and palladium. Refers to an alloy containing two.
[0038]
The seed layer 31 may be a layer that becomes a nucleus (seed) of the metal layer 32 when the metal layer 32 is formed. The seed layer 31 includes, for example, at least one of copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), indium (In), and tin (Sn). By using a conductor layer, a wiring designed in advance can be selectively formed. Note that including at least one of copper, silver, gold, platinum, palladium, indium, and tin means that copper, silver, gold, platinum, palladium, indium, and tin alone, and copper, silver, An alloy containing at least two of gold, platinum, palladium, indium, and tin.
[0039]
In this embodiment, as the seed layer 31 and the metal layer 32, for example, copper (Cu) having a low specific resistance and high resistance to electromigration, stress migration, and the like is used.
[0040]
The cover metal layer 34 is provided so as to cover the exposed surface portion (the upper surface in the present embodiment) of the metal layer 32. The cover metal layer 34 is, for example, a diffusion suppression layer that suppresses diffusion of metal atoms (copper atoms in this embodiment) forming the metal layer 32 from the metal layer 32 to the cover metal layer 34.
[0041]
On the other hand, the signal wiring 8 is provided along the column direction of the pixel electrode 6 (vertical direction in FIG. 1). One end of each signal line 8 is electrically connected to the signal line drive circuit 12. The signal wiring 8 is made of, for example, aluminum.
[0042]
The scanning line driving circuit 11 and the signal line driving circuit 12 are respectively connected to the liquid crystal controller 13. The liquid crystal controller 13 receives an image signal and a synchronization signal supplied from the outside, for example, and generates a pixel video signal Vpix, a vertical scanning control signal YCT, and a horizontal scanning control signal XCT.
[0043]
On the inner surface of the transparent substrate 2 on the front side (upper side in FIG. 2) which is the other transparent substrate, a single film-shaped transparent counter electrode 9 which is opposed to the plurality of pixel electrodes 6 is provided. The counter electrode 9 is made of a transparent electrode such as ITO. A color filter is provided on the inner surface of the transparent substrate 2 on the front side so as to correspond to a plurality of pixel regions in which the plurality of pixel electrodes 6 and the counter electrode 9 face each other, and to correspond to a region between the pixel regions. A light shielding film may be provided.
[0044]
A polarizing plate (not shown) is provided outside the pair of transparent substrates 2 and 3. When the liquid crystal display device 1 is a transmissive type, a surface light source (not shown) is provided behind the transparent substrate 3 on the rear side. The liquid crystal display device 1 may be a reflective type or a transflective type.
[0045]
Next, the TFT 10 will be described. The TFT 10 is provided above the organic resin portion of the substrate 14 to be processed. In the present embodiment, a substrate in which the base insulating layer 5 and the organic resin layer 15 are laminated in this order on the inner surface of the rear transparent substrate 3 is used as the substrate to be processed. That is, in this embodiment, the organic resin layer 15 becomes an organic resin portion.
[0046]
In this embodiment, for example, a channel etch type (bottom gate type) TFT 10 is used. That is, as shown in FIG. 2, the TFT 10 includes a semiconductor layer 22, a gate electrode 20 provided on one side, for example, the lower side of the semiconductor layer 22 via a gate insulating film 21, and a part of the semiconductor layer 22. A source electrode 23 and a drain electrode 24 provided so as to be in contact with each other.
[0047]
The scanning wiring 7 and the gate electrode 20 are selectively provided on a part of the organic resin layer 15. Specifically, a seed layer 31 is provided on a part of the organic resin layer 15. An insulating layer 33 having an opening 33a through which the entire seed layer 31 is exposed is provided on the substrate to be processed 14 (on the organic resin layer 15). The metal layer 32 is provided on the seed layer 31 so as to be embedded in the opening 33a. The exposed surface of the metal layer 32 is covered with a cover metal layer 34.
[0048]
The gate insulating film 21 is provided so as to cover the scanning wiring 7, the gate electrode 20, and the insulating layer 33. As the gate insulating film 21, for example, silicon nitride can be used. On the gate insulating film 21, a non-doped a-Si film 22a serving as a channel region 28 is provided above the gate electrode 20. On the non-doped a-Si film 22a, n as a contact layer is formed. ⁺ A mold a-Si film 22b is provided. This n ⁺ The mold a-Si film 22b has a groove for partially exposing the non-doped a-Si film 22a. This n ⁺ Of the type a-Si film 22b, one side divided by the groove serves as a source region 26 and the other side serves as a drain region 27. These non-doped a-Si films 22a and n ⁺ The type a-Si film 22 b constitutes the semiconductor layer 22. The source electrode 23 and the drain electrode 24 are n ⁺ The n-type a-Si film 22b is in contact with the source region 26 and the drain region 27, respectively. ⁺ It is provided on the mold a-Si film 22b.
[0049]
The pixel electrode 6 is provided on the gate insulating film 21 so as to be in contact with the source electrode 23. The signal wiring 8 is formed integrally with the drain electrode 24. Further, a passivation layer 25 having an opening for exposing the pixel electrode 6 is provided thereon.
[0050]
The film forming process on the substrate to be processed 14 will be described with reference to FIGS.
[0051]
First, a substrate 14 to be processed as shown in FIG. In addition, the to-be-processed substrate 14 can be formed as follows, for example. First, the base insulating layer 5 made of silicon nitride is formed on the transparent substrate 3 so as to have a thickness of about 300 nm. On the base insulating layer 5, polyimide, which is an organic resin material, is applied and thermally cured to form the organic resin layer 15 so that the layer thickness becomes, for example, about 300 nm.
[0052]
Next, a process of forming the TFT 10, the scanning wiring 7, the signal wiring 8, and the pixel electrode 6 on the substrate 14 on which the organic resin layer 15 is formed will be described.
[0053]
Specifically, as shown in FIG. 3B, an insulating layer 33 is formed on the substrate to be processed 14 (on the organic resin layer 15). The insulating layer 33 has an opening 33a in a region corresponding to a predetermined formation position of the gate electrode 20 and the scanning wiring 7 (hereinafter referred to as a selection region). The insulating layer 33 is obtained, for example, by forming silicon nitride on the organic resin layer 15 so as to have a layer thickness of 500 nm, and then performing PEP and etching on the silicon nitride layer to form the opening 33a. . As the insulating layer 33, it is preferable to use an insulating material that can suppress diffusion of copper atoms forming the seed layer 31 and the metal layer 32 into the insulating layer 33, such as silicon nitride. Of course, an organic insulating layer such as BCB (benzocyclobutene) may be used.
[0054]
The to-be-processed substrate 14 in which the opening 33a is formed is surface-treated in plasma containing oxygen. By this surface treatment, as shown in FIG. 3C, an ion introduction processing portion 15a is formed on the surface exposed by the opening 33a of the organic resin layer 15. In the case where the organic resin layer 15 is polyimide, the ion introduction treatment unit 15a has a imide ring cleaved to form a polyamic acid having an amide bond and a carboxyl group. That is, in the ion introduction processing unit 15a, the bond cleavage process of the imide ring is performed. The bond cleavage process of the imide ring can be achieved by performing an ashing process using oxygen-containing plasma for removing the resist after the insulating layer 33 is etched, but may be performed in a separate process.
[0055]
Note that the ion introduction processing unit 15 a may be provided at least on the surface layer of the organic resin layer 15. That is, as shown in FIG. 3C, the ion introduction treatment may be performed only on the surface layer portion of the organic resin layer 15, or may be performed over substantially the entire region in the thickness direction of the organic resin layer 15. Furthermore, the bond cleavage treatment is not limited to the plasma treatment, and for example, the imide ring may be cleaved by bringing potassium hydroxide (KOH) into contact with a selected region of the organic resin layer 15.
[0056]
Next, a solution containing copper ions, for example, a solution containing copper sulfate is prepared. And the to-be-processed substrate 14 which has the said iontophoresis process part 15a is immersed and processed in the said acid solution. By doing in this way, the copper ion in the said solution is adsorb | sucked by the carboxyl group currently formed in the ion introduction process part 15a, and is fixed to the organic resin layer 15. FIG. Thereby, as shown in FIG. 4D, the metal ion introduction part 31a is formed in the selected region exposed from the opening 33a of the organic resin layer 15.
[0057]
The to-be-processed substrate 14 in which the film-forming process was advanced to the state of FIG. 4D is heated at a predetermined temperature, for example, 210 ° C. in a reducing atmosphere, for example, an atmosphere containing hydrogen. As a result, the copper ions introduced into the metal ion introduction part 31 a are reduced, and the metal ion introduction part 31 a of the organic resin layer 15 is converted into the seed layer 31 as shown in FIG. The seed layer 31 serves as a nucleus for selectively forming the gate electrode 20 and the scanning wiring 7. In this way, since the seed layer 31 is selectively formed, the resource of the material of the seed layer 31 can be saved. In order to improve the adhesion of the seed layer 31, an annealing process may be performed after the seed layer 31 is formed.
[0058]
Further, in FIG. 4E, copper ions in almost the entire thickness direction of the metal ion introduction portion 31a are reduced, but the reduction treatment need not necessarily be performed in the entire thickness direction of the metal ion introduction portion 31a. The seed layer 31 may be reduced by reducing at least the surface layer portion of the metal ion introducing portion 31a.
[0059]
That is, the gate electrode 20 and the scanning wiring 7 have an exposed portion that is formed by reducing at least part of the metal ions selectively introduced into at least part of the organic resin layer 15 and exposed from the organic resin layer 15. Further, a seed layer 31 provided on the substrate to be processed 14 and a metal layer 32 provided on at least a part of the seed layer 31 may be provided. Further, a metal ion introduction part 31a provided on the substrate to be processed 14 so as to have an exposed part exposed from the organic resin layer 15 by selectively introducing metal ions into at least a part of the organic resin layer 15; The seed layer 31 formed by reducing at least a part of the exposed part of the metal ion introduction part 31a and the metal layer 32 provided on at least a part of the seed layer 31 may be provided.
[0060]
Next, as shown in FIG. 4F, a metal layer 32 made of copper is formed on the seed layer 31 so as to fill the opening 33a of the insulating layer 33. With this metal layer 32, the gate electrode 20 and the scanning wiring 7 are formed to have a desired layer thickness. This layer thickness may be determined from the required resistance value.
[0061]
In the present embodiment, the insulating layer 33 is formed to be 500 nm, and the metal layer 32 is formed to be 400 nm. Therefore, as shown in the drawing, the metal layer 32 is recessed inside the insulating layer 33 rather than the end face of the opening 33a. If the metal layer 32 has a layer thickness that does not significantly protrude from the surface (opening 33a) of the insulating layer 33, the metal layer 32 may have a layer thickness that is substantially flush with the surface of the insulating layer 33, or a layer thickness that is thinner than that. Also good.
[0062]
The metal layer 32 is formed only on the seed layer 31 by, for example, an electroless plating method using the seed layer 31 as a nucleus. Since the metal layer 32 is formed only on the seed layer 31, it is possible to save resources of the material of the metal layer 32.
[0063]
By the way, as a plating bath for performing the electroless plating, a formaldehyde bath using formaldehyde as a reducing agent may be used. However, when a formaldehyde bath is used, since the plating pH condition is about pH 12 to pH 13, it is necessary to use sodium hydroxide or the like as a pH adjuster. When application to the manufacturing process of the TFT 10 is considered, it is preferable that the alkali metal is not included in the process.
[0064]
Therefore, as a plating bath for performing the electroless plating, it is preferable to use a cobalt salt bath using a cobalt salt as a reducing agent, a tin salt bath using a tin salt, or the like. That is, the cobalt salt bath not only does not contain an alkali metal but also has a plating pH condition in a neutral region of about pH 6 to pH 7, so that the insulating layer 33 is less damaged and suitable for the manufacturing process of the TFT 10. is there.
[0065]
Further, unlike the formaldehyde bath and the glyoxylic acid bath, the cobalt salt bath and the tin salt bath do not generate hydrogen due to decomposition of the reducing agent during the plating reaction process. Therefore, when a cobalt salt bath or a tin salt bath is used as a plating bath for performing the electroless plating, the metal layer 32 having good surface flatness can be formed. In addition, generation of voids (holes) in the metal layer 32 can be suppressed.
[0066]
Next, as shown in FIG. 5G, a cover metal layer 34 is formed so as to cover the upper surface, which is the exposed surface portion of the metal layer 32, and to fill the opening 33a. The cover metal layer 34 is formed so as to have a layer thickness of, for example, about 50 nm. Note that the cover metal layer 34 may be formed so that the surface thereof is flush with the surface of the insulating layer 33.
[0067]
The cover metal layer 34 is made of, for example, a cobalt (Co) -tungsten (W) -boron (B) alloy, a cobalt (Co) -boron (B) alloy, a cobalt (Co) -phosphorus (P) alloy, nickel (Ni ) -Phosphorus (P) alloy, nickel (Ni) -tungsten (W) -phosphorus (P) alloy, etc., and the surface of the metal layer 32 (copper surface) can be selectively electrolessly plated. Moreover, it is preferable to use a metal that can suppress diffusion of metal atoms (copper atoms) forming the metal layer 32 from the metal layer 32 to the cover metal layer 34.
[0068]
In this way, by using the cover metal layer 34 as a diffusion suppressing layer, not only can the oxidation and corrosion of the surface of the metal layer 32 generated in the subsequent step of forming the gate insulating film 21 (for example, the CVD step) be suppressed. The diffusion of metal atoms forming the seed layer 31 and the metal layer 32 into the gate insulating film 21 can be suppressed. As a result, the gate electrode 20 and the scanning wiring 7 are selectively formed on the substrate 14 to be processed.
[0069]
Next, as shown in FIG. 5H, a gate insulating film 21, a semiconductor layer 22, a source electrode 23, and a drain electrode 24 are formed. Specifically, a gate insulating film 21 made of, for example, silicon nitride is formed so as to cover the gate electrode 20. A non-doped a-Si film 22a is formed on the gate insulating film 21, and an n-type film is formed on the non-doped a-Si film 22a. ⁺ A mold a-Si film 22b is formed. After patterning the non-doped a-Si film 22a and the n + type a-Si film 22b, n ⁺ An aluminum thin film to be the source electrode 23 and the drain electrode 24 is formed and patterned on the mold a-Si film 22b. Thereafter, the source electrode 23 and the drain electrode 24 are masked, and the n + type a-Si film 22b between these electrodes is etched. Thus, the TFT 10 is formed.
[0070]
Further, the signal wiring 8 and the pixel electrode 6 are formed and patterned, respectively. Subsequently, a passivation layer 25 is formed, and an opening for exposing the pixel electrode 6 is formed in the passivation layer 25. Thus, the film forming process on the substrate to be processed 14 is completed.
[0071]
Further, in the present embodiment, the step of forming the metal ion introduction portion 31a on the substrate to be processed 14 so as to have an exposed portion exposed to the outside by introducing metal ions into at least a part of the organic resin layer 15 is performed. The step of forming the insulating layer 33 on the substrate 14 to be processed, the step of forming an opening 33a in which at least a part of the organic resin layer 15 is exposed in the insulating layer 33, and the organic resin layer 15 exposed from the opening 33a. A step of cleaving at least a portion of the chemical bond, and a step of introducing a metal ion into the portion where the chemical bond is cleaved, and adsorbing the metal ion to a terminal group formed by cleaving the chemical bond. By doing in this way, the metal ion introduction part 31a can be selectively formed so that it may have the exposed part exposed to the exterior in at least one part in the organic resin layer 15. FIG.
[0072]
In the present embodiment, the step of cleaving at least a part of the chemical bonds of the organic resin layer 15 is a step of cleaving at least a part of the bonds of the organic resin layer 15 by plasma treatment in an atmosphere containing oxygen. Therefore, the metal ion introduction part 31a can be formed in the organic resin layer 15 so as to have an exposed part exposed to the outside without using potassium hydroxide or the like. Therefore, the remaining potassium ions do not diffuse into the copper thin film that forms the electrode, which is suitable for forming the TFT 10.
[0073]
Moreover, in the present embodiment, it is possible to form the metal layer 32 having good surface properties, few voids, and low specific resistance.
[0074]
That is, for example, in a method of selectively forming a wiring by combining a resist mask and an electroless plating method, a palladium catalyst treatment is required. In this embodiment, the seed layer 31 made of copper is made of copper. In order to form the metal layer 32, the metal layer 32 can be formed by electroless plating using a cobalt salt bath or a tin salt bath as a plating bath. The cobalt salt bath and the tin salt bath do not generate hydrogen by decomposition of the reducing agent during the plating reaction, unlike the formaldehyde bath and glyoxylic acid bath. Therefore, in this embodiment, it is possible to perform film formation with good surface properties and less voids.
[0075]
Further, in the method of selectively forming the wiring by combining the resist mask and the electroless plating method, the palladium catalyst treatment is necessary as described above. However, palladium diffuses into the copper plating layer in the heat treatment step, which is a subsequent step, and tends to increase the specific resistance value of the copper plating layer. On the other hand, since this embodiment does not require a palladium catalyst, the metal layer 32 with a low specific resistance can be obtained.
[0076]
In addition, in the conventional TFT 10, the liquid crystal display device 1, and the method for forming them, the gate electrode 20 is processed into a forward taper or wiring (scanning wiring) in consideration of the coverage of the gate insulating film 21 and the occurrence of the short-circuit defect. Etc.) to reduce the aspect ratio. On the other hand, the TFT 10, the liquid crystal display device 1, and the formation method thereof according to this embodiment can have a structure in which the gate electrode 20 and the scanning wiring 7 are embedded in the opening 33 a of the insulating layer 33. For this reason, it is not necessary to consider the coverage of the gate insulating film 21 and the occurrence of the short circuit, and therefore, it is not necessary to process the gate electrode 20 on a forward taper or to reduce the wiring aspect ratio. Thus, in this embodiment, it is possible to reduce the wiring resistance by increasing the aspect ratio and to increase the aperture ratio of the pixel portion by reducing the wiring width. The present embodiment can also be applied to a large-sized substrate 14 that is difficult to use CMP. In the above embodiment, an example in which amorphous silicon is used for the semiconductor layer of the thin film transistor has been described, but polycrystalline silicon or the like may be used.
[0077]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
[0078]
In the present embodiment, the organic resin layer 15 is patterned so as to have a shape corresponding to the selected region. The size of the organic resin layer 15 after patterning may be larger than the opening of the insulating layer 33 as shown in FIG. 6, or may be smaller than the opening as shown in FIG. The seed layer 31 is formed on the surface layer portion of the organic resin layer 15 in the same manner as in the first embodiment, and then the metal layer 32 is formed so as to fill the opening 33a.
[0079]
Since other configurations and processes are the same as those in the first embodiment described above, including portions not shown, redundant description will be omitted by attaching the same reference numerals to the drawings.
[0080]
According to the present embodiment, the step of preparing a substrate to be processed having an organic resin portion formed of an organic resin at least in a part exposed to the outside forms the organic resin layer 15 on the transparent substrate 3. And a step of patterning the organic resin layer 15 into a predetermined shape. Even if it does in this way, the effect similar to 1st Embodiment is acquired. Further, by patterning, for example, when applied to a transmissive liquid crystal display device, it can be formed only in a wiring region and not in a pixel region portion through which light is transmitted. Therefore, problems such as transmittance loss and optical interference can be avoided.
[0081]
As the organic resin layer 15, patterning may be performed using a photosensitive polyimide resin, or a polyimide resin having no photosensitivity may be patterned using a resist film. When using a polyimide resin that does not have photosensitivity, the removal of the resist film and the bond-cleavage treatment of the imide ring are continuously performed by ashing with oxygen-containing plasma when removing the resist film on the polyimide resin. It can be carried out.
[0082]
Hereinafter, a third embodiment of the present invention will be described with reference to FIG.
[0083]
In the present embodiment, the gate electrode 20 and the scanning wiring 7 are formed on the substrate 14 to be processed as follows.
[0084]
First, a substrate to be processed 14 similar to that of the first embodiment is prepared. The organic resin layer 15 is patterned so as to have a shape corresponding to the selected region. Thereafter, the seed layer 31 and the metal layer 32 are formed in the same manner as in the first embodiment. Then, the cover metal layer 34 is formed so as to cover the exposed surface portion (upper surface and peripheral surface) of the metal layer 32. Since other configurations and processes are the same as those in the first embodiment described above, including portions not shown, redundant description will be omitted by attaching the same reference numerals to the drawings.
[0085]
According to the present embodiment, the wiring structure such as the gate electrode 20 and the scanning wiring 7 can be selectively formed without forming the insulating layer 33. Further, since the peripheral surface of the metal layer 32 is covered with the cover metal layer 34, diffusion of metal atoms forming the metal layer 32 into the gate insulating film 21 can be suppressed even without the insulating layer 33.
[0086]
In the first to third embodiments, a substrate having the transparent substrate 3 and the organic resin layer 15 laminated on at least a part of the transparent substrate 3 is used as the substrate to be processed 14. A substrate made of an organic resin material such as polyimide may be used.
[0087]
The fourth embodiment of the present invention will be described below with reference to FIGS.
[0088]
In the present embodiment, a flexible substrate made of an organic resin material such as polyimide is used as the substrate 14 to be processed. That is, the transparent substrate 3 on the rear side becomes the substrate 14 to be processed. The front transparent substrate 2 is a transparent and flexible substrate such as a plastic substrate made of polyimide or the like, as with the rear transparent substrate 3. The TFT 10 is a top gate type organic TFT.
[0089]
The TFT 10 includes an organic semiconductor layer 29, a gate electrode 20 provided on one side, for example, an upper side of the organic semiconductor layer 29 via a gate insulating film 21, and a source provided in contact with a part of the semiconductor layer 22. An electrode 23 and a drain electrode 24 are provided.
[0090]
Specifically, the source electrode 23 and the drain electrode 24 are provided so as to be embedded in the opening 33 a of the insulating layer 33. The signal wiring 8 is provided integrally with the drain electrode 24. The source electrode 23, the drain electrode 24, and the signal wiring 8 are made of, for example, silver (Ag). An organic semiconductor layer 29 is provided on the insulating layer 33 so as to be connected to the source electrode 23 and the drain electrode 24. As the organic semiconductor layer 29, pentacene or the like can be used.
[0091]
The gate insulating film 21 is provided on the organic semiconductor layer 29 so as to cover the organic semiconductor layer 29. A gate electrode 20 is provided on the gate insulating film 21 so as to be located above the organic semiconductor layer 29. In the figure, reference numeral 50 denotes an interlayer insulating film, and reference numeral 25 denotes a passivation layer. The interlayer insulating film 50 is provided on the gate electrode 20 so as to cover the gate electrode 20 and the gate insulating film 21. The gate insulating film 21 and the interlayer insulating film 50 are provided with contact holes 51 and 52, respectively, and the pixel electrode 6 is formed on the interlayer insulating film 50 so as to be in contact with the source electrode 23 through the contact holes 51 and 52. Is provided.
[0092]
Next, a film forming process on the substrate to be processed will be described.
[0093]
First, as shown in FIG. 10A, a substrate to be processed 40 is prepared. On this substrate 40, for example, silicon oxide (SiO ₂ ) Is formed so that the layer thickness is 400 nm. Thereafter, an opening 33 a that exposes the organic resin layer 15 is formed in the insulating layer 33 so as to correspond to a region corresponding to the source electrode 23, the drain electrode 24, and the signal wiring 8 (hereinafter referred to as a selection region).
[0094]
The substrate to be processed 14 on which the insulating layer 33 is formed is subjected to surface treatment in a plasma containing oxygen. As a result, as shown in FIG. 10B, the ion introduction processing unit 40a is formed in the selected region that is the surface layer portion of the substrate to be processed 40 and is exposed from the opening 33a.
[0095]
A solution containing silver ions, for example, a solution containing silver nitrate is prepared. And the to-be-processed substrate 40 is immersed and processed in the said acid solution. By doing in this way, the silver ion in the said solution is adsorb | sucked by the carboxyl group formed in the ion introduction processing part 40a, and is fixed to the surface layer part of the to-be-processed substrate 40. Thereby, as shown in FIG. 10C, the metal ion introduction part 31a is formed in the selected region exposed from the opening 33a of the substrate 40 to be processed.
[0096]
The target substrate 14 is irradiated with ultraviolet light (for example, light having a wavelength of 365 nm). As a result, the silver ions introduced into the metal ion introduction part 31a are reduced, and the seed layer 31 is formed in the substrate to be processed 14 as shown in FIG. The seed layer 31 serves as a nucleus for selectively forming the source electrode 23, the drain electrode 24, and the signal wiring 8.
[0097]
Further, as shown in FIG. 11E, a metal layer 32 made of silver is formed on the seed layer 31 so as to fill the opening 33 a of the insulating layer 33. With this metal layer 32, the source electrode 23, the drain electrode 24, and the signal wiring 8 are thickened to a desired layer thickness. In the present embodiment, the insulating layer 33 is formed to be 400 nm, and the metal layer 32 is formed to be 400 nm. That is, the upper surface of the metal layer 32 is formed to be flush with the upper surface of the insulating layer 33.
[0098]
Then, as shown in FIG. 11F, an organic semiconductor layer 29 is formed on the insulating layer 33 so as to be connected to the source electrode 23 and the drain electrode 24. The organic semiconductor layer 29 is formed to have a layer thickness of 50 nm, for example. The organic semiconductor layer 29 can be formed by vapor deposition using a metal mask.
[0099]
Then, the gate insulating film 21 is formed so as to cover the organic semiconductor layer 29, and the gate electrode 20 is formed on the gate insulating film 21. An interlayer insulating film 50 is formed so as to cover the gate electrode 20. Further, contact holes 51 and 52 are formed in the gate insulating film 21 and the interlayer insulating film 50, and the pixel electrode 6 is formed on the interlayer insulating film 50 so as to be in contact with the source electrode 23 through the contact holes 51 and 52. Further, a passivation layer 25 is formed on the interlayer insulating film 50. An opening for exposing the pixel electrode 6 is formed in the passivation layer 25. Since other configurations and processes are the same as those in the first embodiment described above, including portions not shown, redundant description will be omitted by attaching the same reference numerals to the drawings.
[0100]
As described above, according to the present embodiment, a step of preparing a substrate to be processed having an organic resin portion in at least a part of the portion exposed to the outside, for example, a substrate to be processed 40 made of an organic resin material, A step of forming the source electrode 23 on the processing substrate 40, a step of forming the drain electrode 24 on the substrate to be processed 40, a step of forming the semiconductor layer 29 in contact with the source electrode 23 and the drain electrode 24, Forming a gate electrode 20 on the upper side, which is one side of the semiconductor layer 29, with a gate insulating film 21 interposed therebetween. The step of forming the source electrode 23 and the step of forming the drain electrode 24 on the substrate 40 to be processed is an exposure that is exposed to the outside by selectively introducing metal ions into at least a part of the substrate 40 to be processed. A step of forming the metal ion introduction part 31a on the substrate to be processed 40 so as to have a part, a step of forming a seed layer 31 by reducing at least a part of the exposed part of the metal ion introduction part 31a, and a seed layer 31 Forming a metal layer 32 on at least a part of the upper surface.
[0101]
As described above, the seed layer 31 can be selectively formed on the substrate 40 to be processed by reducing the metal ions selectively introduced into at least a part of the substrate 40 to be processed. In addition, since the seed layer 31 can be selectively formed on the substrate 40 to be processed, the metal layer 32 can be selectively formed on the substrate 40 to be processed using the seed layer 31 as a nucleus. Therefore, wiring structures such as the source electrode 23 and the drain electrode 24 can be selectively formed on the substrate 14 to be processed.
[0102]
Thus, since the source electrode 23 and the drain electrode 24 can be selectively formed, the utilization efficiency of silver which is a raw material of the metal layer 32 can be improved. In addition, since the number of steps can be reduced as compared with the conventional damascene method or the like, the manufacturing cost can be reduced. Accordingly, a method for forming the top gate type TFT 10 and the liquid crystal display device 1 that can reduce the raw material cost and the manufacturing cost and can suppress the burden on the environment can be obtained.
[0103]
In the present embodiment, a wiring structure such as the source electrode 23, the drain electrode 24, and the signal wiring 8 is embedded in the opening 33 a of the insulating layer 33. Therefore, the organic TFT 10 can be flattened, and short-circuit defects and the like that occur between the source electrode 23, the drain electrode 24, the scanning wiring 7 provided above the signal wiring 8, and the like can be suppressed. In addition, since the shapes of the source electrode 23, the drain electrode 24, and the signal wiring 8 can be substantially matched with the shape of the opening 33a (can be controlled by the shape of the opening 33a), the wiring width accuracy is higher than that of the mask vapor deposition method. An organic TFT 10 with good quality can be obtained.
[0104]
Further, the electrode has an inverted stagger structure and a material having a large work function as an electrode material (for example, gold (Au), platinum (Pt), silver (Ag), copper (Cu), palladium (Pd), etc. ), The organic TFT 10 can be formed at a low temperature. By utilizing this, an organic TFT can be formed at a raw material cost and a manufacturing cost by using a flexible organic resin substrate such as a plastic substrate having a lower heat resistant temperature than glass as a substrate to be processed. Therefore, the flexible display apparatus 1 provided with TFT10 can be obtained by this.
[0105]
In the present embodiment, the case where the electrode is a reverse stagger type has been described as an example, but the present invention can also be applied to a case where the electrode is a normal stagger type or a coplanar type.
[0106]
In this embodiment, a substrate made of an organic resin material such as polyimide is used as the substrate to be processed 14, but the substrate to be processed 14 is an organic layer laminated on at least a part of the transparent substrate 3 and the transparent substrate 3. A substrate having the resin layer 15 may be used.
[0107]
Furthermore, in this embodiment, the source electrode 23, the drain electrode 24, and the signal wiring 8 are formed of gold. However, the source electrode 23, the drain electrode 24, and the signal wiring 8 are, for example, low resistance or migration resistant. It may be formed of a metal including at least one of copper having excellent properties and the like, copper having excellent low resistance, silver, gold, platinum, and palladium. By using ultraviolet irradiation as a method for forming the seed layer by reducing the metal ion introduction portion, a seed layer of not only silver but also gold, platinum, palladium, or the like can be formed.
[0108]
In the first to fourth embodiments, the method of reducing the metal ion introduction part to form the seed layer includes not only heat treatment in a reducing atmosphere and ultraviolet irradiation but also heating in a nitrogen atmosphere. It can also be performed by treatment or vacuum ultraviolet irradiation. For metals that oxidize easily, such as copper, heat treatment is desirable in a reducing atmosphere, and for metals that can be reduced by ultraviolet irradiation, such as silver, the temperature rise that is unnecessary for light irradiation can be suppressed, and the processing time can be shortened easily. It is.
[0109]
Furthermore, in the first to fourth embodiments, polyimide is used as the organic resin material, but not only polyimide but also a polar group such as a carboxyl group is formed at the terminal group by cleaving the chemical bond as the organic resin material. Any organic resin may be used as long as it is formed.
[0110]
The display device and the method for forming the same according to the present invention are not limited to the liquid crystal display device 1 and can be applied to a display device such as an organic EL device or an inorganic EL device. Further, the present invention is not limited to display devices, and can be widely applied to, for example, semiconductor devices.
[0111]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain a thin film transistor, a display device, and a method for forming them, which can selectively form a wiring structure such as an electrode or a wiring.
[Brief description of the drawings]
FIG. 1 is a plan view showing a liquid crystal display device according to a first embodiment of the present invention.
2 is a cross-sectional view showing a part of the liquid crystal display device of FIG. 1;
FIGS. 3A to 3C are cross-sectional views illustrating an initial process for forming a thin film transistor included in the liquid crystal display device of FIG.
FIGS. 4D to 4F are cross-sectional views illustrating steps in an intermediate stage for forming a thin film transistor included in the liquid crystal display device of FIG.
FIGS. 5G and 5H are cross-sectional views illustrating a final process of forming a thin film transistor included in the liquid crystal display device of FIG.
FIG. 6 is a cross-sectional view showing the vicinity of a gate electrode of a thin film transistor according to a second embodiment of the invention.
FIG. 7 is a cross-sectional view showing the vicinity of a gate electrode of another thin film transistor according to the second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing the vicinity of a gate electrode of a thin film transistor according to a third embodiment of the invention.
FIG. 9 is a plan view showing a part of a liquid crystal display device according to a fourth embodiment of the present invention.
10 is a cross-sectional view showing a part of the liquid crystal display device of FIG. 9;
11A to 11C are cross-sectional views illustrating the first half of a process for forming a thin film transistor included in the liquid crystal display device of FIG. 9;
12D to 12F are cross-sectional views illustrating a latter half process of forming a thin film transistor included in the liquid crystal display device of FIG. 9;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device (display apparatus), 3 ... Transparent base | substrate (base | substrate), 10 ... Thin-film transistor, 14, 40 ... Substrate to be processed, 15 ... Organic resin layer (organic resin part), 20 ... Gate electrode, 21 ... Gate insulation Membrane, 22 ... Semiconductor layer, 23 ... Source electrode, 24 ... Drain electrode, 29 ... Organic semiconductor layer (semiconductor layer), 31 ... Seed layer, 32 ... Metal layer, 33 ... Insulating layer, 33a ... Opening, 34 ... Cover metal layer

Claims (16)

A thin film transistor provided above the organic resin portion of the substrate to be processed having an organic resin portion made of an organic resin at least in a portion exposed to the outside,
A semiconductor layer, a gate insulating film, a gate electrode, a source electrode, and a drain electrode, and at least one of the gate electrode, the source electrode, and the drain electrode is
A seed provided on the substrate to be processed so as to have an exposed portion exposed from the organic resin portion by reducing at least a portion of metal ions selectively introduced into at least a portion of the organic resin portion. Layers,
And a metal layer provided on at least a part of the seed layer. At least one of the gate electrode, the source electrode, and the drain electrode further includes an insulating layer having an opening through which at least a part of the seed layer is exposed, and the metal layer has the opening. The thin film transistor according to claim 1, wherein the thin film transistor is provided so as to be embedded therein. The thin film transistor according to claim 2, wherein the insulating layer is a diffusion suppression layer that suppresses diffusion of metal atoms forming the metal layer from the metal layer to the insulating layer. The metal layer has a surface exposed portion, and at least one of the gate electrode, the source electrode, and the drain electrode is provided to cover at least the surface exposed portion of the metal layer The thin film transistor according to any one of claims 1 to 3, further comprising a metal layer. The thin film transistor according to claim 4, wherein the cover metal layer is a diffusion suppression layer that suppresses diffusion of metal atoms forming the metal layer from the metal layer to the cover metal layer. A display device comprising a plurality of thin film transistors provided in a matrix, wherein each of the plurality of thin film transistors is the thin film transistor according to claim 1. Preparing a substrate to be processed having an organic resin portion in at least a portion of the portion exposed to the outside;
Forming a gate electrode on the substrate to be processed;
Forming a semiconductor layer on one side of the gate electrode through a gate insulating film;
Forming a source electrode in contact with the semiconductor layer;
Forming a drain electrode in contact with the semiconductor layer,
Forming a gate electrode on the substrate to be processed;
Forming a metal ion introduction part on the substrate to be processed so as to have an exposed part exposed to the outside by selectively introducing metal ions into at least a part of the organic resin part;
Reducing at least a part of the exposed portion of the metal ion introduction portion to form a seed layer;
Forming a metal layer on at least a part of the seed layer. A method for forming a thin film transistor, comprising: Preparing a substrate to be processed having an organic resin portion in at least a portion of the portion exposed to the outside;
Forming a source electrode on the substrate to be processed;
Forming a drain electrode on the substrate to be processed;
Forming a semiconductor layer in contact with the source electrode and the drain electrode;
Forming a gate electrode on one side of the semiconductor layer through a gate insulating film,
At least one of the step of forming a source electrode on the substrate to be processed and the step of forming a drain electrode on the substrate to be processed includes:
Forming a metal ion introduction part on the substrate to be processed so as to have an exposed part exposed to the outside by selectively introducing metal ions into at least a part of the organic resin part;
Reducing at least a part of the exposed portion of the metal ion introduction portion to form a seed layer;
Forming a metal layer on at least a part of the seed layer. A method for forming a thin film transistor, comprising: The step of forming the metal ion introduction part on the substrate to be processed so as to have an exposed part exposed to the outside by introducing metal ions into at least a part of the organic resin part,
Cleaving at least some of the chemical bonds of the organic resin portion;
The method includes introducing a metal ion into a portion where the chemical bond is cleaved, and adsorbing the metal ion to a terminal group obtained by cleaving the chemical bond. A method for forming a thin film transistor. The step of forming the metal ion introduction part on the substrate to be processed so as to have an exposed part exposed to the outside by introducing metal ions into at least a part of the organic resin part,
Forming an insulating layer on the substrate to be processed;
Forming an opening in the insulating layer through which at least part of the organic resin portion is exposed;
Cleaving at least a portion of the chemical bond of the organic resin portion exposed from the opening;
The method includes introducing a metal ion into a portion where the chemical bond is cleaved, and adsorbing the metal ion to a terminal group obtained by cleaving the chemical bond. A method for forming a thin film transistor. The step of cleaving at least part of the chemical bond of the organic resin part is a step of cleaving at least part of the bond of the organic resin part by plasma treatment in an atmosphere containing oxygen. The method for forming a thin film transistor according to any one of 7 to 10. The step of reducing at least a part of the exposed part of the metal ion introduction part to form the seed layer is performed by a heat treatment in a nitrogen atmosphere or a reducing atmosphere, so that at least a part of the exposed part of the metal ion introduction part. The method of forming a thin film transistor according to claim 7, wherein the seed layer is formed by reducing the substrate. The step of reducing at least a part of the exposed part of the metal ion introduction part to form a seed layer includes reducing at least a part of the exposed part of the metal ion introduction part by irradiating with ultraviolet rays or vacuum ultraviolet rays. 12. The method for forming a thin film transistor according to claim 7, wherein the method is a step of forming a seed layer. Forming a metal layer on at least a portion of the seed layer,
Forming a metal layer on at least part of the seed layer so as to have a surface exposed portion;
14. The method of forming a thin film transistor according to claim 7, further comprising a step of forming a cover metal layer so as to cover at least a surface exposed portion of the metal layer after the formation of the metal layer. . 15. A method for forming a display device comprising a plurality of thin film transistors formed in a matrix, wherein each of the plurality of thin film transistors is formed by the method for forming a thin film transistor according to claim 7. A method for forming a display device, comprising: A thin film transistor provided above the organic resin portion of the substrate to be processed having an organic resin portion in at least a part of the portion exposed to the outside,
A thin film conductor layer, an insulating layer, and a conductor layer provided on the thin film conductor layer or the insulating layer and forming at least one of an electrode and a wiring;
The thin film transistor according to claim 1, wherein the conductor layer includes a seed layer in which at least a part of the organic resin portion is reduced, and a metal layer provided on the seed layer.

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