KR20150033407A - Forming method of metal line and array substrate applying the same and method of fabricating the array substrate - Google Patents

Abstract

The present invention relates to a method for forming a line, an array substrate applying the same and a method for manufacturing an array substrate. The method for forming a line includes the steps of: forming first photosensitive patterns having a type of being spaced apart from each other on a substrate; forming a first barrier pattern on an area exposed between the first photosensitive patterns by performing atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD) on the substrate on which the first photosensitive patterns are formed using a first metal organic precursor; forming a metal pattern on the top of the first barrier pattern by plating the substrate on which the first barrier pattern is formed; and removing the first photosensitive patterns and the first barrier pattern formed thereon by lifting off the first photosensitive patterns.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a metal line and an array substrate using the same,

The present invention relates to a metal wiring forming method and an array substrate to which the metal wiring is formed. More particularly, the present invention relates to a metal wiring having an oxide semiconductor layer excellent in stability of a device characteristic, Thermal instability, diffusion, and the like, and an array substrate using the same and a method of manufacturing the same.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

An active matrix liquid crystal display device including an array substrate including a thin film transistor Tr which is a switching element capable of controlling voltage on and off for each pixel in a liquid crystal display device has a resolution And the ability to implement video is the most attention.

In such a liquid crystal display device, an array substrate provided with a thin film transistor (Tr), which is a switching element, is essential in order to turn on / off each pixel region.

1 is a cross-sectional view of a portion of a conventional array substrate constituting a liquid crystal display device in which one pixel region is cut including a thin film transistor Tr.

As shown in the figure, in the switching region TrA in a plurality of pixel regions P in which a plurality of gate lines (not shown) and a plurality of data lines 33 are defined in the array substrate 11, gate electrodes 15 are formed.

A gate insulating layer 18 is formed on the entire surface of the gate electrode 15 and sequentially formed thereon an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon. (28) are formed.

A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. At this time, the gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute the thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45.

At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method, and the difference in thickness (t1? T2) of the active layer 22, more precisely the source and drain And the thickness of the exposed portion between the electrodes is reduced, thereby deteriorating the characteristics of the thin film transistor Tr.

Therefore, recently, as shown in Fig. 2 (sectional view of one pixel region of the array substrate provided with the thin film transistor Tr having the conventional oxide semiconductor layer), the ohmic contact layer 26 A thin film transistor Tr having an oxide semiconductor layer 77 of a single layer structure using an oxide semiconductor material has been developed.

The thin film transistor Tr having the conventional oxide semiconductor layer 77 includes a gate electrode 73, a gate insulating film 75, an oxide semiconductor layer 77, And the side ends of the oxide semiconductor layer 77 are separated from each other at an upper portion of the etch stopper 79 and an etch stopper 79 formed at the center of the oxide semiconductor layer 77, Source and drain electrodes 81 and 83, respectively.

And a drain contact hole 87 exposing the drain electrode 83 and covering the thin film transistor Tr having such a structure. The drain electrode 83 is formed on the protection layer 85, And the pixel electrode 89 is formed in contact with the drain electrode 83 through the contact hole 87. [

In the array substrate 71 having such a structure, since the oxide semiconductor layer 77 does not need to form the ohmic contact layer (26 in FIG. 1), the conventional semiconductor layer (28 in FIG. 1) It is not necessary to be exposed to the dry etching proceeding to form the mutually spaced ohmic contact layers (26 in Fig. 1) made of the impurity amorphous silicon which is similar in material to the array substrate (11 in Fig. 1) Tr) can be prevented from deteriorating.

On the other hand, in recent years, as the size of the display device has been increased, the area of the array substrate has been gradually increased, and the wiring and the like have become relatively long. As a result, signal delay due to internal resistance has become a problem. Copper (Cu), which is one of metal materials, is used.

However, when the wiring and the electrode, that is, the gate wiring, the electrode, the source and drain electrodes, and the data wiring are formed of copper, deterioration of characteristics of the thin film transistor in which the oxide semiconductor layer is exposed to the etchant for etching the copper occurs, Due to its high oxidation characteristics, there are restrictions on the process progress when forming wiring and electrodes using copper.

In addition, when copper is thermally unstable and is heated to a specific temperature or higher, diffusibility becomes very large, which causes problems such as diffusion into an oxide semiconductor layer or an insulating layer located in the upper part or the lower part. In this case, And the contact resistance between the oxide semiconductor layer and the source and drain electrodes is increased, thereby causing a problem of deteriorating the characteristics of the thin film transistor.

Disclosure of the Invention The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to prevent the adverse effects of an oxide semiconductor layer caused by an etchant, It is an object of the present invention to provide an array substrate and a method of manufacturing the same that can prevent a characteristic deterioration of a thin film transistor having a semiconductor layer.

According to an aspect of the present invention, there is provided a wiring forming method including forming a first photosensitive pattern on a substrate, the first photosensitive pattern being spaced apart from the first photosensitive pattern; (ALCVD) or metal organic chemical vapor deposition (MOCVD) using a first metal organic precursor on the substrate on which the first photosensitive pattern is formed, Forming a barrier pattern; Forming a metal pattern on the first barrier pattern by performing plating on the substrate on which the first barrier pattern is formed; And removing the first barrier pattern formed on top of the first photosensitive pattern by lifting off the first photosensitive pattern.

Forming a second photosensitive pattern spaced apart from the first metal pattern and spaced apart from each other by the metal pattern with a spacing of a first width after the step of removing the first photosensitive pattern; ; ALCVD (metal organic chemical vapor deposition) or MOCVD (metal organic chemical vapor deposition) using the first metal organic precursor is performed on the substrate on which the second photosensitive pattern is formed to correspond to a region exposed between the second photosensitive patterns Forming a second barrier pattern on both sides of the metal pattern and on the upper surface of the metal pattern; And removing the second barrier pattern formed on the second photosensitive pattern with the second photosensitive pattern by lifting off the second photosensitive pattern.

And performing a metal organic chemical vapor deposition (MOCVD) process using a second metal organic precursor (ALCVD) or a metal organic chemical vapor deposition (MOCVD) process to form a metal seed layer on the first barrier pattern Wherein the second metal organic precursor is a material having the following chemical structural formula.

Also. The metal pattern is formed of any one of copper, silver and gold.

And the first metal organic precursor is a material having the following chemical structural formula.

Also. The first barrier pattern and the second barrier pattern may have a single layer structure of Ta or TaN, a single layer structure of Ta and TaN, or a dual layer structure of Ta and TaN .

Meanwhile, an insulating layer or an oxide semiconductor layer may be further formed on the substrate before the first photosensitive pattern is formed.

An array substrate according to an embodiment of the present invention includes a gate and a data line crossing each other to define a pixel region, and a pixel electrode connected to the thin film transistor and the pixel region, wherein the gate line and the thin film The gate electrode of the transistor has a metal pattern, a first barrier pattern below the metal pattern, and a second barrier pattern on an upper surface and a side surface of the metal pattern, respectively, and the source and drain of the data line and the thin film transistor Each of the electrodes has a metal pattern and a first barrier pattern formed under the metal pattern.

At this time, the second barrier pattern is provided on the surface and the side surface of the metal pattern of the data wiring and the source and drain electrodes.

And a metal seed layer is further provided between each of the metal patterns of the gate wiring, the gate electrode, the data wiring, the source and drain electrodes, and the first barrier pattern.

The first and second barrier patterns may have a single layer structure of Ta or TaN, or may be a single layer of Ta and TaN. Alternatively, the metal pattern may be formed of any one of copper, gold, and silver. Or a double layer structure of Ta and TaN.

The thin film transistor includes an interlayer insulating film having a gate electrode, a gate insulating film, a semiconductor layer, and a semiconductor layer contact hole exposing both end surfaces of the semiconductor layer on the substrate, A gate insulating film and a gate electrode formed on the substrate so as to correspond to the semiconductor layer and a central portion of the semiconductor layer, the gate electrode and the gate electrode being in contact with the semiconductor layer and having a bottom gate structure in which the source electrode and the drain electrode, A source electrode and a drain electrode which are in contact with the semiconductor layer through the semiconductor layer contact hole and are spaced apart from each other and which are separated from each other through the semiconductor layer contact hole, And is characterized by forming a sequentially stacked coplanar structure.

At this time, the semiconductor layer is preferably an oxide semiconductor layer made of any one of IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), and ZIO (Zinc Indium Oxide).

A method of manufacturing an array substrate according to an embodiment of the present invention includes a gate and a data line crossing each other to define a pixel region and a pixel electrode connected to the thin film transistor and the pixel region, Wherein the gate wiring and the gate electrode of the thin film transistor each have a metal pattern, a first barrier pattern below the metal pattern, and a second barrier pattern on an upper surface and a side surface of the metal pattern, The source and drain electrodes of the thin film transistor are each formed to have a metal pattern and a first barrier pattern formed thereunder.

At this time, the data line, the source electrode, and the drain electrode are formed so that the second barrier pattern is formed on the surface and the side surface of the metal pattern.

A metal seed layer may be formed between each of the gate wirings, each metal pattern of the gate electrode, the data wirings, the source and drain electrodes, and the first barrier pattern.

In addition, the gate electrode and the gate wiring may be formed by: (a) forming a first photosensitive pattern having a shape apart from each other on the substrate; (ALCVD) or metal organic chemical vapor deposition (MOCVD) using a first metal organic precursor on the substrate on which the first photosensitive pattern is formed, (B) forming a barrier pattern; (C) forming a metal pattern on the first barrier pattern by performing plating on the substrate on which the first barrier pattern is formed; (D) removing a first barrier pattern formed on top of the first photosensitive pattern by lifting off the first photosensitive pattern; (E) forming a second photosensitive pattern spaced apart from the first metal pattern by a distance of a first width and spaced apart from each other by the metal pattern; ALCVD (metal organic chemical vapor deposition) or MOCVD (metal organic chemical vapor deposition) using the first metal organic precursor is performed on the substrate on which the second photosensitive pattern is formed to correspond to a region exposed between the second photosensitive patterns (F) forming a second barrier pattern on both sides of the metal pattern and on the upper surface of the metal pattern; (G) removing the second barrier pattern formed on the second photosensitive pattern by lifting off the second photosensitive pattern, wherein the step of forming the data line and the source and drain electrodes Is formed by performing the above-described steps (a) to (d).

In the step of forming the gate line, the gate electrode, the data line, the source and the drain electrode, before performing the plating, an atomic layer chemical vapor deposition (ALCVD) or a metal organic chemical vapor (MOCVD) using a second metal organic precursor forming a metal seed layer on the upper surface of the first barrier pattern by performing a deposition process on the second metal organic precursor. The second metal organic precursor is a material having the following chemical structural formula.

The data line and the source and drain electrodes may be formed by further performing the steps (e) to (g) after performing the steps (a) to (d) And the second barrier pattern is further formed on the side surface and the upper surface of each metal pattern.

And the first metal organic precursor is a material having the following chemical structural formula.

The present invention provides a wiring which is made of any one of copper, gold, and silver, which is a metal material having low resistance characteristics, and has such a structure that wiring of these materials can suppress diffusion to other layers, And the source and drain electrodes are made of a metal material having a low resistance characteristic, so that it has a low resistance characteristic, and the occurrence of signal delay and the like is suppressed even if the array substrate is made larger.

Furthermore, in the gate wiring, the electrode, the data wiring, and the source and drain electrodes, the metal pattern made of a metal material is in a state in which both the upper and lower surfaces are covered by the first and second barrier patterns, The metal pattern itself is prevented from diffusing into other components even if heat is supplied to each of the components.

Therefore, there is an effect of originally suppressing the characteristics of the thin film transistor resulting from the diffusion of the metal wiring or the electrode to the other constituent elements, more precisely the oxide semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device, in which one pixel region is cut including a thin film transistor; Fig.
2 is a cross-sectional view of a pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer.
FIGS. 3A through 3H are cross-sectional views illustrating steps of manufacturing a copper pattern on a substrate according to an embodiment of the present invention; FIG.
FIG. 4 is a graph comparing the signal delay constants of the copper wiring pattern according to the present invention and the copper wiring surrounded by the barrier pattern of Ta or TaN material and the wiring of the triple-layered structure of MoTi / Cu / MoTi according to the comparative example.
FIG. 5 is a cross-sectional view of a pixel region formed on an array substrate according to a first embodiment of the present invention, in which a thin film transistor and a pixel electrode connected thereto are formed. FIG.
FIG. 6 is a cross-sectional view of a pixel region formed on an array substrate according to a modification of the first embodiment of the present invention, in which a thin film transistor and pixel electrodes connected thereto are formed. FIG.
FIG. 7 is a cross-sectional view of a pixel region of an array substrate according to a second embodiment of the present invention, in which a thin film transistor and a pixel electrode connected thereto are formed. FIG.
FIG. 8 is a cross-sectional view of a pixel region of an array substrate according to a modification of the second embodiment of the present invention, in which a thin film transistor and a pixel electrode connected thereto are formed. FIG.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

First, a method of forming a wiring or an electrode made of copper on a substrate in a desired shape without a separate etchant will be described as an example of a metal material having a low resistance characteristic, which is the most characteristic constitution of the present invention. At this time, since the copper wiring or the copper electrode is different in shape only, it is hereinafter referred to as a copper wiring.

The metal material having the low resistance characteristic may be not only copper but also gold (Au) or silver (Ag) having similar or better resistivity characteristics. Hereinafter, copper .

FIGS. 3A through 3H are cross-sectional views illustrating steps of fabricating a copper pattern on a substrate according to an embodiment of the present invention.

First, a photosensitive material having a photosensitive property, for example, a photoresist, a photoacrylic, or a polymethly methacrylate (PMMA) is applied on the substrate 110 to form a photosensitive material layer, and then an exposure mask (not shown) And then developed to form a first photosensitive pattern 191. The first photosensitive pattern 191 is formed on the first photosensitive pattern 191,

At this time, the substrate 110 may be a pure substrate, or a specific material layer, for example, an inorganic insulating material or an oxide semiconductor material may be deposited on the substrate to form a specific material layer or a specific pattern.

That is, the insulating layer formed of silicon oxide (SiO ₂₎ or silicon nitride (SiNx) over pure substrate may be formed, or the oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide), ZTO (Zinc Tin Oxide), ZIO (Zinc And indium oxide (ITO), or a semiconductor pattern in which the oxide semiconductor material layer is patterned may be formed.

In the drawing, the substrate 110 in a pure substrate state is used as an example.

The first photosensitive pattern 191 exposes the substrate 110 to a portion where a copper pattern 125 (FIG. 3H) is to be formed later, and corresponds to a place where the copper pattern 125 of FIG. 3H should not be formed .

3B, an atomic layer chemical vapor deposition (ALCVD) or a metal organic chemical vapor deposition (MOCVD) using a first metal organic precursor is performed on the substrate 110 on which the first photosensitive pattern 191 is formed, Thereby forming a first barrier pattern 115 for suppressing diffusion of the copper pattern (125 of FIG. 3H) formed later by heat.

The first metal organic precursor used in the AICVD or MOCVD process used for forming the first barrier pattern 115 may include a material having a structural formula shown below, .

[First metal organic precursor]

When ALCVD or MOCVD is performed using the first metal organic precursor having the above-described chemical structure, the first metal organic precursor has stability against thermal self-decomposition and high volatility. Further, the portion where the first photosensitive pattern 191 is formed is not formed due to the absence of reactivity between the ligand or the ligand and the photosensitive pattern due to the self-limiting property, and only the portion exposed between the first photosensitive patterns 191 A first barrier pattern 115 is formed.

At this time, the first barrier pattern 115 has a single layer structure of TaN or Ta, or a dual layer structure of TaN and Ta or a single layer of TaN and Ta.

The formation of the first barrier pattern 115 in the form of a single layer or a bilayer structure may be achieved by using one or more of the first metal organic precursors or by using ALCVD or the like using two or more different conventional first metal organic precursors It is possible to have different structural characteristics depending on whether the vacuum chamber for introducing MOCVD is introduced at a time or at the same time.

In addition, the first barrier pattern 115 has a single-layer structure as an example, and the first barrier pattern 115 is very weakly formed on the first photosensitive pattern 191 due to the reaction characteristic. And only the surface of the substrate 110 exposed between the first photosensitive patterns 191 is mainly formed.

The first barrier pattern 115 may be formed of TaN or Ta. Alternatively, the first barrier pattern 115 may be formed of Mo or MoTi by using the first metal organic precursor as another material. have.

Next, as shown in FIG. 3C, the copper seed layer 120 may be further formed so that the copper pattern (125 of FIG. 3H) may be further formed over the first barrier pattern 115 selectively.

The copper seed layer 120 may be selectively etched using the same method of forming the first barrier pattern 115, that is, ALCVD or MOCVD using a second metal organic precursor having the following chemical structure, 115).

[Second Metal Organic Precursor]

This copper seed layer 120 is characterized by being made of copper.

Meanwhile, the step of forming the copper seed layer 120 on the first barrier pattern 115 as shown in FIG. 3C does not need to proceed and may be omitted.

Thus, omitting the step of forming the copper seed layer 120 on the first barrier pattern 115 is a modification of the embodiment of the present invention.

3D, the substrate 110 on which the first barrier pattern 115 is formed or the substrate 110 on which the first barrier pattern 115 and the copper seed layer 120 are formed is subjected to stripping the first barrier pattern 115 and the copper seed layer (not shown) formed finely above the first photosensitive pattern 191 (FIG. 3C) by removing the first photosensitive pattern 191 (FIG. 120 are removed together.

The removal of the first photoresist pattern 191 and the material layer (the first barrier pattern 115 or the first barrier pattern 115 and the copper seed layer 120) formed thereon together is lifted off, Process.

Accordingly, the first barrier pattern 115 finely formed on the first photosensitive pattern 191 (FIG. 3C) is removed together with the progress of the lift-off process, so that the copper pattern (125 The first barrier pattern 115 and the copper seed layer 120 (or the first barrier pattern 115 in the modified example) are formed only on the portion where the first barrier pattern 115 and the second barrier pattern 115 should be formed.

Next, as shown in FIG. 3E, the first photosensitive pattern 191 is removed so that the substrate 110 on which the first barrier pattern 115 and the copper seed layer 120 are formed is subjected to electrolytic plating or electroless plating Thereby selectively forming the copper pattern 125 only on the upper portion of the copper seed layer 120 (in the modified example, the upper portion of the first barrier pattern 115).

3F, a photosensitive material is coated on the entire surface of the substrate 110 on which the copper pattern 125 is formed, and a photosensitive material layer (not shown) is formed. Then, the copper pattern 125 is patterned, The second photosensitive pattern 192 is formed at a predetermined interval. At this time, it is preferable that the predetermined interval is about 2000 Å to 10000 Å, for example, of the thickness of the first barrier pattern 115.

At this time, the second photosensitive pattern 192 has the same shape as the first photosensitive pattern 191, and is smaller than the first photosensitive pattern 191 only.

The formation of the second photoresist pattern 192 on the substrate 110 at a predetermined distance from the copper pattern 125 may cause a second barrier pattern (see FIG. 3H) to be formed on the upper surface and the side surface of the copper pattern 125, 140 of the first embodiment).

3G, the same method as that of forming the first barrier pattern 115 in a state where the second photosensitive pattern 192 is formed, that is, an ALCVD process using the first metal organic precursor a second barrier pattern 140 is formed on the top and side surfaces of the copper pattern 125 spaced apart from the second photosensitive pattern 192 by performing chemical vapor deposition (MOCVD) or metal organic chemical vapor deposition (MOCVD).

The second barrier pattern 140 formed by progressing to atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD) using the first metal organic precursor is formed at the time of forming the first barrier pattern 115 The second barrier pattern 140 is mainly formed only on the upper surface and the side surface of the copper pattern 125 by the action of the same first metal organic precursor and the second barrier pattern 140 is formed of Ta or TaN .

The thickness of the second barrier pattern 140 formed on the upper surface and the side surface of the copper pattern 125 is the same or similar to the thickness of the first barrier pattern 115, that is, about 2000 Å to 10000 Å .

Next, as shown in FIG. 3H, a strip solution (not shown) for removing the second photosensitive pattern 192 is formed on the substrate 110 having the second barrier pattern 140 formed on the upper surface and the side surface of the copper pattern 125, The desired pattern of copper wiring 130 is formed on the substrate 110 by simultaneously removing the second photosensitive pattern 192 and the second barrier pattern 140 formed on the second photosensitive pattern 192.

The first barrier pattern 115 is formed on the lower surface of the copper pattern 125 and the second barrier pattern 115 is formed on the upper surface and the side surfaces of the copper pattern 125. In this case, (140) is formed.

The reason why the first and second barrier patterns 125 and 140 are formed on the slope of the copper pattern 125 is that diffusion of the copper pattern 125 into the adjacent material layer (not shown) .

Further, according to the method of forming the copper wiring 130 according to the embodiment of the present invention described above, an etchant for etching the copper material is not used at all.

In the case where a copper etchant for etching copper is not used, there is no possibility that the oxide semiconductor layer is exposed to the copper etchant during the fabrication of the array substrate 110, so that the characteristic deterioration of the thin film transistor including the oxide semiconductor layer is It can be prevented at the source.

On the other hand, according to the above-described manufacturing method of the copper wiring 130, both the upper surface and the side surface of the copper pattern 125 are covered with the first and second barrier patterns 125 and 140, The steps of forming the second photosensitive pattern 192 and the second barrier pattern 140 at predetermined intervals around the copper pattern 125, that is, steps shown in FIGS. 3F to 3H, The first barrier pattern 115 is formed only on the lower surface of the copper pattern 125 and the second barrier pattern 140 is formed on the upper surface and the side surface of the copper pattern 125 by omitting the step of stripping and removing the second photosensitive pattern 192. [ May not be formed.

At this time, a copper seed layer 120 may be further formed between the copper pattern 125 and the first barrier pattern 115.

In the case of the copper wiring 130 having the structure in which the first barrier pattern 115 is formed only on the copper pattern 125 and the bottom surface thereof, diffusion of the copper pattern 125 occurs through the side surface and the top surface, But it is prevented from spreading to the lower surface.

Such a structure can be applied to the source and drain electrodes that are usually located above the oxide semiconductor layer.

The first and second barrier patterns 125 and 140 are formed by atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD), respectively. It is characterized in that diffusion of the copper pattern 125 can be effectively prevented because the internal structure is very dense.

The first and second barrier patterns 125 and 140 are made of Ta or TaN. The resistivity of each of the first and second barrier patterns 125 and 140 is about 12.4 and 132 μΩcm, respectively, (Resistivity value: 1041 [mu] [Omega] cm), the electrical conductivity is much higher than MoTi.

Therefore, the barrier pattern of Ta or TaN material plays a role as a wiring having a low resistance characteristic suppressing signal delay in addition to the copper pattern 125, in addition to the copper pattern 125, great.

As a comparative example, in the case of forming a wiring using a copper material, it is possible to use a three-layered structure of MoTi / Cu / MoTi having a constitution in which a barrier layer of MoTi material is provided on the upper and lower surfaces of copper wiring, Wiring is proposed.

Compared with the wiring according to the comparative example having such a structure and the copper wiring 130 manufactured according to the embodiment of the present invention, the first and second barrier patterns 125 and 140 and the MoTi layer have the same thickness, the copper wiring 130 according to the embodiment of the present invention has a thickness of about 100 to 1000 탆 of the copper to the outside of the copper wiring 130 when exposed to a temperature atmosphere of 600 to 650 캜 for a predetermined time. On the other hand, in the case of the wiring according to the comparative example in which the barrier layer made of the MoTi material was formed, diffusion of copper occurred in a temperature atmosphere of 350 캜.

This is because the first and second barrier patterns 125 and 140 are formed by atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD) to form a MoTi material formed by sputtering, This is because the internal denseness compared to the barrier layer is excellent and it is not easy for the copper to penetrate the first and second barrier patterns 125 and 140.

 Furthermore, since the resistivity of MoTi is 1041 mu OMEGA cm, the conductivity is relatively low relative to Ta or TaN. Therefore, Ta or TaN relative to the wiring of MoTi / Cu / MoTi of the comparative example using MoTi as a barrier layer The copper wiring 130 according to the embodiment of the present invention formed through atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD) may be superior in terms of signal delay prevention.

FIG. 4 is a graph comparing signal delay constants of a copper pattern surrounded by a barrier pattern of a Ta or TaN material and a wiring of a triple-layered structure of MoTi / Cu / MoTi according to a comparative example, according to the present invention.

100㎛ based on the length of, in the case of copper interconnects according to the embodiment of the present invention, signal delay constant is 10 ⁰ to 10 ¹ to be a degree, but if the wiring of the three-layer structure according to the comparative example signal delay constant is 10 ^1.5 To about 10 < RTI ID = 0.0 > ^6.5 < / RTI >

Therefore, the copper wiring surrounded by the barrier pattern of the Ta or TaN material in the copper pattern according to the present invention and the slope of the copper wiring according to the present invention are excellent in the prevention of the signal delay compared to the wiring of the triple-layered structure of MoTi / Cu / MoTi according to the comparative example.

Meanwhile, in the embodiment of the present invention, a copper pattern is formed by progressing copper plating in the progress of plating in the embodiment of the present invention. However, a metal material similar to or having a lower resistance characteristic than copper, for example, It will be appreciated that the gold wiring or the silver wiring can also be formed by the same method by plating gold or silver.

Hereinafter, an array substrate and a structure manufactured by applying the above-described method of forming a copper wiring and a manufacturing method thereof will be described.

In this array substrate and its manufacturing method, a low resistance metal material is exemplarily made of copper, but it may be gold or silver instead of copper.

5 is a cross-sectional view of a pixel region formed on an array substrate according to the first embodiment of the present invention, in which a thin film transistor and a pixel electrode connected thereto are formed. Here, for convenience of description, a portion where the thin film transistor Tr as a switching element is formed in each pixel region P is defined as a switching region TrA.

As shown in the drawing, the array substrate 200 according to the first embodiment of the present invention includes a transparent insulating substrate 201, a plurality of gate wirings (not shown) extending in one direction and spaced apart from each other by a predetermined distance And a gate electrode 205 is formed in each pixel region P, which is connected to the gate wiring (not shown).

The gate wiring (not shown) and the gate electrode 205, which is one of the most characteristic structures in the array substrate 200 according to the first embodiment of the present invention, include a copper pattern 125 made of copper, The first barrier pattern 115 is provided for the lower surface of the pattern 125 and the second barrier pattern 140 is provided for the upper surface and the side surface of the copper pattern 125. [

The first and second barrier patterns 115 and 140 are made of the same metal material, and each of the first and second barrier patterns 115 and 140 may be formed of a single layer of Ta or TaN or a single layer of Ta and TaN mixed therein, .

Therefore, both the gate wiring (not shown) and the gate electrode 205 are provided with a copper pattern 125 made of copper at the center, and the first and second barrier patterns 115 and 140 ).

Since the first and second barrier patterns 115 and 140 themselves are made of a metal material, the gate wiring (not shown) and the gate electrode 205 having such a structure are not problematic in applying voltage or current.

Although it is shown that a copper seed layer 120 is further formed between the first barrier pattern 115 and the copper pattern 125 in the gate wiring (not shown) and the gate electrode 205, The copper seed layer 120 may be omitted. That is, the copper seed layer 120 functions to facilitate the formation of the copper pattern 125 by the plating method. As described above, the copper seed layer 120 can be formed by a plating method sufficiently on the first barrier pattern 115 125) can be well formed and thus can be omitted.

An example of the substrate 201 inorganic insulating material is formed on the gate wiring (not shown) (not shown) and the gate electrode 105 made of the copper pattern 125 and the first and second barrier patterns 115 and 140 A gate insulating film 115 made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 201.

The switching region TrA is formed on the gate insulating layer 215 by a material selected from the group consisting of Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), and Zinc Indium Oxide (ZIO) An oxide semiconductor layer 220 is formed in an island shape corresponding to a central portion of the oxide semiconductor layer 205.

An interlayer insulating layer 225 having a semiconductor layer contact hole 223 exposing the both end surfaces of the oxide semiconductor layer 220 is formed on the oxide semiconductor layer 220.

Data wirings 230 are formed on the interlayer insulating film 225 having the semiconductor layer contact holes 223 so as to cross the gate wirings (not shown) and define the pixel regions P at a predetermined interval A source electrode 233 is formed in the switching region TrA and is connected to the data line 230. A drain electrode 236 is formed to be spaced apart from the source electrode 233. [

At this time, the source electrode 233 and the drain electrode 236 are in contact with the oxide semiconductor layer 220 through the semiconductor layer contact hole 223, respectively.

In the array substrate 200 according to the first embodiment of the present invention, the data line 230 and the source and drain electrodes 233 and 236 are connected to the gate wiring (not shown) The first and second barrier patterns 115 and 140 are formed in the same shape as the gate electrode 205 and the copper pattern 125 and the surrounding pattern.

In other words. A first barrier pattern 115 is formed on the lower surface of the data pattern 230 and the source and drain electrodes 233 and 236 and a copper pattern 125. The copper pattern 125 And a copper seed layer 120 is formed between the copper pattern 125 and the first barrier pattern 115. The second barrier pattern 140 is formed on the upper surface and the side surface of the first barrier pattern 115,

The data line 230, the source and drain electrodes 233 and 236 having such a structure, and the copper seed layer 120 may be omitted.

The source electrode 233 and the drain electrode 236 spaced apart from the gate electrode 205, the gate insulating film 215, the oxide semiconductor layer 220, and the interlayer insulating film 225, which are sequentially stacked in each switching region TrA, ) Constitute a thin film transistor Tr which is a switching element.

Next, a protective layer 220 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) or an organic insulating material such as photo-acryl is formed on the thin film transistor Tr and the data line 230. (244) are formed.

The protective layer 244 is provided with a drain contact hole 248 for exposing the drain electrode 236 in each switching region TrA.

A transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed on the passivation layer 244 having the drain contact hole 248 through the drain contact hole 248, And the pixel electrode 270 is formed in contact with the pixel region 136 and separated for each pixel region P. [

(Not shown), the gate electrode 205, the data line 230, and the source and drain electrodes 233 and 236 in the case of the array substrate 200 according to the first embodiment of the present invention having the above- And a copper pattern 125 made of a copper material. This structure has a low resistance characteristic, so that even when the array substrate 201 is large-sized, signal delay and the like are suppressed.

Further, the copper pattern 125 made of a copper material in the gate wiring (not shown), the gate electrode 205, the data wiring 230, and the source and drain electrodes 233 and 236 serves to prevent diffusion thereof Since the lower surface, the upper surface and the side surface are covered by the first and second barrier patterns 115 and 140, even if heat is supplied to each of the components, the copper pattern 125 itself diffuses to other components .

Therefore, the copper pattern 125, which is a component constituting the gate wiring (not shown), the gate electrode 205, the data wiring 230, and the source and drain electrodes 233 and 236, Layer transistor 220. In this case, the characteristics of the thin-film transistor, which is caused by diffusion into the layer 220, are originally suppressed.

6 is a cross-sectional view of a pixel region formed on an array substrate according to a modification of the first embodiment of the present invention, in which a thin film transistor and a pixel electrode connected thereto are formed. The array substrate according to the first embodiment of the present invention is different from the array substrate according to the first embodiment only in the form of the data line and the source and drain electrodes and the other components are the same, Only the shapes of the source and drain electrodes will be described.

The data line 231 and the source and drain electrodes 234 and 237 provided on the array substrate 290 according to the modified example of the first embodiment of the present invention are formed in the same pattern as the copper pattern 125 and the first barrier pattern 115) are formed. At this time, the copper seed layer 120 may be formed between the first barrier pattern 115 and the copper pattern 125, or may be omitted.

That is, each of the data wiring 231 and the source and drain electrodes 234 and 237 provided in the array substrate 290 according to the modification of the first embodiment of the present invention is formed so that only the lower surface of the copper pattern 125 is covered with the first barrier A pattern 115 is formed, and a second barrier pattern is provided on the side surface and the top surface thereof.

When the first barrier pattern 115 is formed only on the lower portion of the copper pattern 125 as described above, even if the copper pattern 125 is formed on the lower portion of the data pattern 231 and the source and drain electrodes 234 and 237, The first barrier pattern 115 prevents the diffusion of the copper pattern 125 to the lower surface of the oxide semiconductor layer 220 ) Can be originally prevented.

Therefore, in the case of the array substrate 290 according to the modification of the first embodiment of the present invention having the above-described configuration, even if diffusion occurs in the copper pattern 125 by heat supply, it is limited to the protective layer 244, The diffusion into the semiconductor layer 220 is prevented, and the characteristics of the thin film transistor Tr are not reduced.

Hereinafter, a method of manufacturing the array substrate according to the first embodiment of the present invention and its modifications will be briefly described with reference to FIGS. 5 and 6. FIG.

3A to 3H, a copper pattern 125 made of copper is formed on a transparent insulating substrate 201 and a single layer or a double layer structure made of Ta or TaN (Not shown) having a first barrier pattern 115 and a second barrier pattern 240 having a single layer or a double layer structure of Ta or TaN on its upper and side surfaces, and a gate electrode 205 connected thereto, .

At this time, the gate wiring (not shown) extends in one direction and is spaced apart by a predetermined distance.

Next, a gate insulating film 215 is formed on the entire surface of the substrate 201 by depositing an inorganic insulating material on the gate wiring (not shown) and the gate electrode 205.

Thereafter, an oxide semiconductor material such as IGZO (Zinc Oxide Zinc Oxide), ZTO (Zinc Tin Oxide), or ZIO (Zinc Indium Oxide) is deposited or coated on the gate insulating layer 215, And an island-shaped oxide semiconductor layer 220 is formed in each switching region TrA corresponding to each of the gate electrodes.

An inorganic insulating material is deposited on the oxide semiconductor layer 220 to form an interlayer insulating layer 225 and then patterned to form a semiconductor layer contact hole 223 ).

Next, the method described above with reference to FIGS. 3A to 3H is performed (in the case of the first embodiment), or only the method described in FIGS. 3A to 3E (in the case of the modification of the first embodiment) A data line 230 or 231 having a first barrier pattern 115 or a second barrier pattern 115 enclosing the copper pattern 125 or a first barrier pattern 115 formed on the lower surface of the copper pattern 125, A source electrode 233 or 234 and a drain electrode 236 or 237 which are spaced apart from each other are formed. At this time, the source seed layer 120 may be further formed between the copper pattern 125 and the first barrier pattern 115, or may be omitted.

The source electrode 233 or 234 and the drain electrode 236 or 237 define a pixel region P which intersects the gate line (not shown) And contact with the oxide semiconductor layer 220 through the contact hole 223.

Each of the switching regions TrA includes an interlayer insulating film 225 having the gate electrode 205, the gate insulating film 215, the oxide semiconductor layer 220, and the semiconductor layer contact hole 223 sequentially stacked, The electrode 233 or 234 and the drain electrode 236 or 237 form a thin film transistor Tr.

An inorganic insulating material is deposited on the entire surface of the substrate 201 over the data line 230 or 231, the source electrode 233 or 234 and the drain electrode 236 or 237 or an organic insulating material is applied to the protective layer 244 are formed and patterned to form a drain contact hole 248 exposing the drain electrode 236 or 237 in each switching region TrA.

A transparent conductive material is then deposited on the passivation layer 244 and patterned to contact the drain electrode 236 or 237 through the drain contact hole 248 to form a pixel electrode The array substrate 200 or 290 according to the first embodiment of the present invention (or a modification thereof) is completed by forming the electrode 270.

FIG. 7 is a cross-sectional view of a pixel region of an array substrate according to a second embodiment of the present invention, in which a thin film transistor and a pixel electrode connected thereto are formed. FIG.

In the case of the array substrate 300 according to the second embodiment of the present invention, the difference from the array substrate 200 according to the first embodiment of the present invention (200 in FIG. 5) is that the thin film transistor Tr provided in each switching region, Only the shape of the thin film transistor Tr will be described briefly.

First, in the array substrate 300 according to the second embodiment of the present invention, the oxide semiconductor layer 308 is formed in an island shape in each switching region TrA.

At this time, a light shielding pattern 303 is further formed in each switching region TrA to shield light incident from the outside corresponding to the oxide semiconductor layer 308, and the light shielding pattern 303 is formed on the substrate 301 A buffer layer 305 may be further formed on the entire surface.

In the drawing, for example, it is shown that the light shielding pattern 303 and the buffer layer 305 are provided.

A gate insulating layer 315 and a gate electrode 317 made of an inorganic insulating material are formed on the oxide semiconductor layer 308 in correspondence with the central portion of the oxide semiconductor layer 308. Further, A gate insulating film 315 and a gate wiring (not shown) having the same shape as the gate insulating film 315 are formed extending in one direction.

The gate electrode 317 and the gate wiring (not shown) are formed of a copper pattern 125 and first and second barrier patterns 115 and 140 surrounding the copper pattern 125. The copper pattern 125 and the first The copper seed layer 120 is formed between the barrier patterns 115 or omitted.

 An interlayer insulating film 325 is formed on the entire surface of the substrate 301 over the gate electrode 317 and the gate wiring (not shown). The interlayer insulating film 325 is interposed between the gate electrode 317 And a semiconductor layer contact hole 323 for exposing the oxide reaction body layer 308 to both sides thereof.

A data line 330 is formed on the interlayer insulating layer 325 so as to intersect with the gate line (not shown). Each of the switching regions TrA is provided with the oxide semiconductor layer 323 through the semiconductor layer contact hole 323, The source and drain electrodes 333 and 326 are formed in contact with the source and drain electrodes 308, respectively.

At this time, the oxide semiconductor layer 308, the gate insulating film 315, the interlayer insulating film 325 having the gate electrode 317 and the semiconductor layer contact hole 323 sequentially stacked in each switching region TrA are spaced apart from each other The source and drain electrodes 333 and 336 form a thin film transistor Tr.

The data line 330 and the source and drain electrodes 333 and 336 are formed of a copper pattern 125 and first and second barrier patterns 115 and 140 surrounding the copper pattern 125. The copper pattern 125 And the first barrier pattern 115. The copper seed layer 120 may be formed on the first barrier pattern 115 or may be omitted.

Other configurations are the same as those of the array substrate according to the first embodiment, and therefore, the description is omitted.

8 is a cross-sectional view of a pixel region of an array substrate according to a modification of the second embodiment of the present invention, in which a thin film transistor and pixel electrodes connected thereto are formed.

In the case of the array substrate 390 according to the modified example of the second embodiment of the present invention, the data line 331 and the source electrode 334 and the drain electrode 339 (see FIG. 7) Only the shapes of the data line 331 and the source and drain electrodes 334 and 337 will be described.

The data line 331 and the source electrode 334 and the drain electrode 339 included in the array substrate 390 according to the modification of the second embodiment of the present invention are arranged on the array substrate according to the modification of the first embodiment The first barrier pattern 115 is formed only on the copper pattern 125 and the lower surface thereof. At this time, a copper seed layer 120 may be further formed between the first barrier pattern 115 and the copper pattern 125.

That is, the data line 331, the source electrode 334, and the drain electrode 339 included in the array substrate 390 according to the modification of the second embodiment of the present invention are formed only on the lower surface of the copper pattern 125 1 barrier pattern 115 is formed, and the second barrier pattern provided on the side surface and the upper surface thereof is omitted.

A method of manufacturing an array substrate according to a second embodiment of the present invention having such a configuration and a modification thereof will be briefly described with reference to Figs. 6 and 7. Fig.

First, a light shielding pattern 303 is formed corresponding to each switching region TrA by applying a material having a property of blocking or absorbing light, for example, black resin, on the transparent insulating substrate 301 and patterning the same do.

A buffer layer 305 is formed by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire surface of the substrate 301 over the light-shielding pattern 303.

At this time, the step of forming the light shielding pattern 303 and the buffer layer 305 may be omitted.

Next, an oxide semiconductor material is deposited or coated on the buffer layer 305 and patterned to form an island-shaped oxide semiconductor layer 308 in each switching region TrA.

Then, an inorganic insulating material is coated on the oxide semiconductor layer 308 to form an inorganic insulating material layer (not shown).

Next, the method described above with reference to FIGS. 3A to 3H is performed on the inorganic insulating material layer (not shown) to form a gate wiring (not shown) composed of the copper pattern 125 and the first and second barrier patterns 115 and 140 (Not shown) and a gate electrode 317 are formed. At this time, a copper seed layer 120 may be further formed between the copper pattern 125 and the first barrier pattern 115.

Thereafter, the inorganic interconnection layer (not shown) exposed to the outside of the gate interconnection (not shown) and the gate electrode 317 is removed by dry etching to form the gate interconnection (not shown) A gate insulating film 315 having the same planar shape as the gate wiring (not shown) and the gate electrode 317 is formed.

Next, an inorganic insulating material is deposited on the gate wiring (not shown) and the gate electrode 317 to form an interlayer insulating film 325 and patterned to form the oxide semiconductor 325 on both sides of the gate electrode 317, A semiconductor layer contact hole 323 exposing the layer 308 is formed.

Next, the method described above with reference to FIGS. 3A to 3H is performed (in the case of the second embodiment) on the interlayer insulating film 325 provided with the semiconductor layer contact hole 323, or only the method described in FIGS. 3A to 3E The copper pattern 125 and the first and second barrier patterns 115 and 140 may be provided on the copper pattern 125 and the first barrier pattern 115 may be provided on the bottom surface of the copper pattern 125. In this case, A source electrode 333 or 334 and a drain electrode 336 or 337 which are spaced apart from each other are formed. At this time, the source seed layer 120 may be further formed between the copper pattern 125 and the first barrier pattern 115, or may be omitted.

The data line 330 or 331 intersects the gate line (not shown) to define a pixel region P, and the source electrode 333 or 334 and the drain electrode 336 or 337 define a pixel region P, And contact with the oxide semiconductor layer 308 through the contact hole 323.

Each switching region TrA is formed by sequentially stacking the oxide semiconductor layer 308, the gate insulating film 315, the interlayer insulating film 325 having the gate electrode 317 and the semiconductor layer contact hole 323, The electrode 333 or 334 and the drain electrode 336 or 337 form a thin film transistor Tr.

An inorganic insulating material is deposited on the entire surface of the substrate 301 over the data line 330 or 331, the source electrode 333 or 334 and the drain electrode 336 or 337 or an organic insulating material is applied to the protective layer 344 are formed and then patterned to form drain contact holes 348 exposing the drain electrodes 336 or 337 in the respective switching regions TrA.

A transparent conductive material is then deposited on the passivation layer 344 and patterned to contact the drain electrode 336 or 337 through the drain contact hole 348 to form pixels The array substrate 300 or 390 according to the second embodiment of the present invention (or a modified example thereof) is completed by forming the electrode 370.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

100: substrate
115: first barrier pattern
125: Copper pattern
140: second barrier pattern
192: second photosensitive pattern

Claims (22)

Forming a first photosensitive pattern having a shape that is spaced apart from each other on a substrate;
(ALCVD) or metal organic chemical vapor deposition (MOCVD) using a first metal organic precursor on the substrate on which the first photosensitive pattern is formed, Forming a barrier pattern;
Forming a metal pattern on the first barrier pattern by performing plating on the substrate on which the first barrier pattern is formed;
Removing the first barrier pattern formed on top of the first photosensitive pattern by lifting off the first photosensitive pattern;
.
The method according to claim 1,
After the step of removing the first photosensitive pattern,
Forming a second photosensitive pattern spaced apart from the first metal pattern by a distance of a first width and spaced apart from each other by the metal pattern;
ALCVD (metal organic chemical vapor deposition) or MOCVD (metal organic chemical vapor deposition) using the first metal organic precursor is performed on the substrate on which the second photosensitive pattern is formed to correspond to a region exposed between the second photosensitive patterns Forming a second barrier pattern on both sides of the metal pattern and on the upper surface of the metal pattern;
Removing the second barrier pattern formed on the second photosensitive pattern with the second photosensitive pattern by lifting off the second photosensitive pattern;
.
3. The method according to claim 1 or 2,
Before proceeding with the plating,
Forming a metal seed layer on the first barrier pattern by performing atomic layer chemical vapor deposition (ALCVD) or metal organic chemical vapor deposition (MOCVD) using a second metal organic precursor.
The method of claim 3,
Wherein the second metal organic precursor is a material having the following chemical structural formula.

3. The method according to claim 1 or 2,
Wherein the metal pattern is made of any one of copper, silver, and gold.
3. The method according to claim 1 or 2,
Wherein the first metal organic precursor is a material having the following chemical structural formula.

3. The method according to claim 1 or 2,
The first barrier pattern and the second barrier pattern may have a single layer structure of Ta or TaN, a single layer structure of Ta and TaN, or a dual layer structure of Ta and TaN Wire forming method.
3. The method according to claim 1 or 2,
Wherein an insulating layer or an oxide semiconductor layer is further formed on the substrate before forming the first photosensitive pattern.
A gate electrode and a data line intersecting each other to define a pixel region; and a thin film transistor and a pixel electrode connected to the thin film transistor in the pixel region,
Wherein the gate wiring and the gate electrode of the thin film transistor have a metal pattern, a first barrier pattern below the metal pattern, and a second barrier pattern on the upper surface and the side surface of the metal pattern,
Wherein the data line and the source and drain electrodes of the thin film transistor each have a metal pattern and a first barrier pattern formed thereunder.
10. The method of claim 9,
And a second barrier pattern is provided on a surface and a side surface of the metal pattern of the data wiring and the source and drain electrodes.
10. The method of claim 9,
Wherein a metal seed layer is further provided between each of the metal patterns of the gate wiring, the gate electrode, the data wiring, the source and drain electrodes, and the first barrier pattern.
10. The method of claim 9,
Wherein the metal pattern is made of any one of copper, gold, and silver,
The first barrier pattern and the second barrier pattern may have a single layer structure of Ta or TaN, a single layer structure of Ta and TaN, or a dual layer structure of Ta and TaN Array substrate.
12. The method according to any one of claims 9 to 11,
The thin-
An interlayer insulating film having a gate electrode, a gate insulating film, a semiconductor layer, and a semiconductor layer contact hole exposing both end surfaces of the semiconductor layer, and an interlayer insulating film which contacts the semiconductor layer through the semiconductor layer contact hole, The source electrode and the drain electrode which are spaced apart form a bottom gate structure sequentially stacked,
A gate insulating layer and a gate electrode formed on the substrate so as to correspond to a central portion of the semiconductor layer and the semiconductor layer, and a semiconductor layer contact hole covering the gate electrode and exposing both end surfaces of the semiconductor layer, And the source electrode and the drain electrode which are in contact with the semiconductor layer through the semiconductor layer contact hole and are spaced apart from each other are sequentially laminated.
14. The method of claim 13,
Wherein the semiconductor layer is an oxide semiconductor layer made of any one selected from the group consisting of Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), and Zinc Indium Oxide (ZIO).
A method of manufacturing an array substrate including a gate and a data line crossing each other and defining a pixel region, and a thin film transistor and a pixel electrode connected to the pixel region,
Wherein the gate wiring and the gate electrode of the thin film transistor have a metal pattern, a first barrier pattern below the metal pattern, and a second barrier pattern on the upper surface and the side surface of the metal pattern,
Wherein the data line and the source and drain electrodes of the thin film transistor are formed to have a metal pattern and a first barrier pattern formed under the metal pattern, respectively.
16. The method of claim 15,
Wherein a second barrier pattern is formed on a surface and a side surface of the metal pattern of the data wiring and the source and drain electrodes.
16. The method of claim 15,
Wherein a metal seed layer is formed between each of the metal patterns of the gate wiring, the gate electrode, the data wiring, the source and drain electrodes, and the first barrier pattern.
16. The method of claim 15,
The gate electrode and the gate wiring are connected to each other,
(A) forming a first photosensitive pattern having a shape separated from each other on the substrate;
(ALCVD) or metal organic chemical vapor deposition (MOCVD) using a first metal organic precursor on the substrate on which the first photosensitive pattern is formed, (B) forming a barrier pattern;
(C) forming a metal pattern on the first barrier pattern by performing plating on the substrate on which the first barrier pattern is formed;
(D) removing a first barrier pattern formed on top of the first photosensitive pattern by lifting off the first photosensitive pattern;
(E) forming a second photosensitive pattern spaced apart from the first metal pattern by a distance of a first width and spaced apart from each other by the metal pattern;
ALCVD (metal organic chemical vapor deposition) or MOCVD (metal organic chemical vapor deposition) using the first metal organic precursor is performed on the substrate on which the second photosensitive pattern is formed to correspond to a region exposed between the second photosensitive patterns (F) forming a second barrier pattern on both sides of the metal pattern and on the upper surface of the metal pattern;
(G) of removing the second barrier pattern formed on the second photosensitive pattern by lifting off the second photosensitive pattern,
The data line and the source and drain electrodes are connected to each other through a contact hole,
Wherein the step (a) is performed after the step (d).
19. The method of claim 18,
In the step of forming the gate wiring, the gate electrode, the data wiring, and the source and drain electrodes,
Before proceeding with the plating,
(ALCVD) or metal organic chemical vapor deposition (MOCVD) using a second metal organic precursor to form a metal seed layer on the upper surface of the first barrier pattern. ≪ / RTI >
20. The method of claim 19,
Wherein the second metal organic precursor is a material having the following chemical structural formula.

20. The method according to claim 18 or 19,
The data line and the source and drain electrodes may be formed by further performing the steps (e) to (g) after the step (a) to (d) And a second barrier pattern is further formed on a side surface and an upper surface of the substrate.
20. The method according to claim 18 or 19,
Wherein the first metal organic precursor is a material having the following chemical structural formula.

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