JP5818210B2 - 誘電ライン・バイアのエレクトロマイグレーション耐性が向上した界面層を有する相互接続構造およびその製造方法 - Google Patents
誘電ライン・バイアのエレクトロマイグレーション耐性が向上した界面層を有する相互接続構造およびその製造方法 Download PDFInfo
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- JP5818210B2 JP5818210B2 JP2011542741A JP2011542741A JP5818210B2 JP 5818210 B2 JP5818210 B2 JP 5818210B2 JP 2011542741 A JP2011542741 A JP 2011542741A JP 2011542741 A JP2011542741 A JP 2011542741A JP 5818210 B2 JP5818210 B2 JP 5818210B2
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (12)
- 相互接続構造であって、
CuまたはCu合金を含む第1の導電材料が埋め込まれた第1の誘電材料と、
前記第1の誘電材料の上に位置した第2の誘電材料であって、前記第1の導電材料の上に位置する組み合わせバイアおよびラインを含む少なくとも1つの導電充填開口を含む、前記第2の誘電材料と、
前記バイアの底部および前記ラインの水平方向底部にのみ位置する界面層と、
前記界面層の上に形成された、下層の金属窒化物層と該金属窒化物層の上層の金属層とを含むバリア層と、
を含み、
前記バイアの前記底部に存在する前記界面層は、前記第1の導電材料内に形成され、前記第2の誘電材料内の前記少なくとも1つの導電充填開口から前記第1の導電材料を分離する少なくとも金属合金界面層を含み、
前記ラインの前記水平方向底部内に位置する前記界面層が、前記バリア層の下部に位置する金属界面層を含み、
前記金属界面層が、V、Nb、Ta、Fe、Ni、Ru、Rh、Pd、Os、IrおよびPtのいずれかから成る導電金属を含み、
前記金属合金界面層が前記金属界面層の導電金属と前記第1の導電材料との反応生成物を含む、相互接続構造。 - 前記金属合金界面層がTa−Cu、Ru−Cu、またはIr−Cuを含む、請求項1に記載の相互接続構造。
- 前記少なくとも1つの導電充填開口がCuまたはCu合金を含む、請求項1または2に記載の相互接続構造。
- 前記バリア層に含まれる前記金属窒化物層は、TaN、TiN、RuTaN、またはWNを含み、前記バリア層の前記金属層は、Ta、Ti、Ru、RuTaまたはWを含む、請求項1〜3のいずれか1項に記載の相互接続構造。
- 前記第1および第2の誘電材料が同一または異なる誘電材料から成り、前記誘電材料が4.0以下の誘電率を有する、請求項1〜4のいずれか1項に記載の相互接続構造。
- 前記第1および第2の誘電材料間に存在する誘電キャッピング層を更に含む、請求項1〜5のいずれか1項に記載の相互接続構造。
- 相互接続構造であって、
CuまたはCu合金を含む第1の導電材料が埋め込まれた第1の誘電材料と、
前記第1の誘電材料の上に位置した第2の誘電材料であって、前記第1の導電材料の上に位置する少なくとも1つの導電充填開口を含む、前記第2の誘電材料と、
前記少なくとも1つの導電充填開口の底部にのみ位置し、前記第1の導電材料内に形成される金属合金界面層と、
前記金属合金界面層の上に形成された、下層の金属窒化物層と該金属窒化物層の上層の金属層とを含むバリア層と、
を含み、前記少なくとも1つの導電充填開口および前記第1の導電材料が、前記金属合金界面層によって分離され、前記金属合金界面層が、V、Nb、Ta、Fe、Ni、Ru、Rh、Pd、Os、IrおよびPtのいずれかから成る導電金属と前記第1の導電材料との反応生成物を含む、相互接続構造。 - 前記金属合金界面層がTa−Cu、Ru−Cu、またはIr−Cuを含む、請求項7に記載の相互接続構造。
- 前記少なくとも1つの導電充填開口がCuまたはCu合金を含む、請求項7または8に記載の相互接続構造。
- 前記バリア層に含まれる前記金属窒化物層は、TaN、TiN、RuTaN、またはWNを含み、前記バリア層の前記金属層は、Ta、Ti、Ru、RuTaまたはWを含む、請求項7〜9のいずれか1項に記載の相互接続構造。
- 前記第1および第2の誘電材料が同一または異なる誘電材料から成り、前記誘電材料が4.0以下の誘電率を有する、請求項7〜10のいずれか1項に記載の相互接続構造。
- 前記第1および第2の誘電材料間に存在する誘電キャッピング層を更に含む、請求項7〜11のいずれか1項に記載の相互接続構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/346,040 US8288276B2 (en) | 2008-12-30 | 2008-12-30 | Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion |
US12/346,040 | 2008-12-30 | ||
PCT/EP2009/064974 WO2010076074A1 (en) | 2008-12-30 | 2009-11-11 | Interconnect structure with improved dielectric line to via electromigration resistant interfacial layer and method of fabricating same |
Publications (2)
Publication Number | Publication Date |
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JP2012514321A JP2012514321A (ja) | 2012-06-21 |
JP5818210B2 true JP5818210B2 (ja) | 2015-11-18 |
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JP2011542741A Expired - Fee Related JP5818210B2 (ja) | 2008-12-30 | 2009-11-11 | 誘電ライン・バイアのエレクトロマイグレーション耐性が向上した界面層を有する相互接続構造およびその製造方法 |
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US (2) | US8288276B2 (ja) |
EP (1) | EP2356677A1 (ja) |
JP (1) | JP5818210B2 (ja) |
CN (1) | CN102246293A (ja) |
WO (1) | WO2010076074A1 (ja) |
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-
2008
- 2008-12-30 US US12/346,040 patent/US8288276B2/en active Active
-
2009
- 2009-11-11 WO PCT/EP2009/064974 patent/WO2010076074A1/en active Application Filing
- 2009-11-11 CN CN2009801501315A patent/CN102246293A/zh active Pending
- 2009-11-11 JP JP2011542741A patent/JP5818210B2/ja not_active Expired - Fee Related
- 2009-11-11 EP EP09749125A patent/EP2356677A1/en not_active Withdrawn
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2012
- 2012-09-14 US US13/617,060 patent/US20130001789A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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US20130001789A1 (en) | 2013-01-03 |
WO2010076074A1 (en) | 2010-07-08 |
EP2356677A1 (en) | 2011-08-17 |
JP2012514321A (ja) | 2012-06-21 |
CN102246293A (zh) | 2011-11-16 |
US20100164111A1 (en) | 2010-07-01 |
US8288276B2 (en) | 2012-10-16 |
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