WO2011018938A1 - Carte de circuits imprimés à plusieurs couches - Google Patents

Carte de circuits imprimés à plusieurs couches Download PDF

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Publication number
WO2011018938A1
WO2011018938A1 PCT/JP2010/062424 JP2010062424W WO2011018938A1 WO 2011018938 A1 WO2011018938 A1 WO 2011018938A1 JP 2010062424 W JP2010062424 W JP 2010062424W WO 2011018938 A1 WO2011018938 A1 WO 2011018938A1
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WO
WIPO (PCT)
Prior art keywords
multilayer printed
layer
conductor
wiring board
printed wiring
Prior art date
Application number
PCT/JP2010/062424
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English (en)
Japanese (ja)
Inventor
薫 成田
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日本電気株式会社
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Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2011526711A priority Critical patent/JPWO2011018938A1/ja
Publication of WO2011018938A1 publication Critical patent/WO2011018938A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09618—Via fence, i.e. one-dimensional array of vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present invention relates to a signal transmission line of a multilayer printed wiring board, and more particularly to a multilayer printed wiring board having a vertical signal transmission line (through-hole via) structure.
  • FIG. 10 is a partial sectional view showing a signal path of the multilayer printed wiring board.
  • a multilayer printed wiring board is composed of a core layer 501 consisting of eight layers as a layer structure, one build-up layer 502 consisting of four layers provided on the upper surface side of the core layer 501 in FIG.
  • the other build-up layer 503 consisting of four layers provided on the lower surface side of the layer 501 in FIG. 10 is provided.
  • the core layer 501 and the buildup layers 502 and 503 constitute part or all of the signal paths L (1) and L (2), respectively, as will be described later.
  • the core layer 501 includes eight ground layers 501a, 501a,... Including a ground layer. Of the eight conductor layers, in the example of FIG. 10, the first layer (the layer facing the bottom layer of one buildup layer 502 in FIG. 10) and the eighth layer (the other buildup layer in FIG. 10).
  • the signal path conductor layers 501p and 501s are formed on a part of each of the uppermost layer 503), and the other layers function as the ground layer 501a.
  • a dielectric 511 is filled between the ground layers 501a.
  • a dielectric 513 is filled between each of the buildup layers 502 and 503 described above.
  • a cylindrical center conductor (through-hole via) 505 is disposed so as to penetrate the core layer 501 (over the vertical direction in FIG. 10).
  • the center conductor 505 is filled with a dielectric 512.
  • the four-layer structure of one of the buildup layers 502 described above is divided into four strip wirings as shown by reference numerals 502a, 502b, 502c, and 502d from the left side in FIG. Has been.
  • the second layer is divided into two strip wirings as indicated by reference numerals 502e and 502f.
  • the third layer is divided into two strip wirings as indicated by reference numerals 502g and 502h, and the fourth layer is divided into two strip wirings as indicated by reference numerals 502i and 502j.
  • the signal path L (1) uses the second strip wiring 502b from the left of the first layer of the buildup layer 502 as a signal input unit, and is a signal via. 504b communicates with the second-layer strip wiring 502f, and then communicates from the strip wiring 502f to the first-layer strip wiring 502d of the buildup layer 502 via the signal via 504c on the right end side of FIG. The wiring 502d is communicated with other circuits using the signal output unit.
  • the signal path L (2) uses the first strip wiring 502a from the left of the first layer of the buildup layer 502 as a signal input unit, and the strip wirings 502e, 502g, 502i is sequentially communicated through signal vias 504a, 504d, 504e, and 504f that are preliminarily connected and connected to the other buildup layer 503 via the central conductor (through-hole via) 505 of the core layer 501 described above. It is configured to be.
  • Reference numerals 501p and 501s denote communication layers that connect the build-up layers 502 and 503 and the end portions of the central conductor (through-hole via) 505 from the upper left in FIG. 10 toward the lower right in FIG.
  • Passing signals from the front side to the back side of the printed wiring board is highly demanded from the viewpoint of high-density mounting because it can increase the mounting density by mounting parts such as LSI on both sides of the printed wiring board. It is.
  • the upper layer (core layer 501 side) in FIG. 10 is the first layer, and this first layer is a strip wiring 503a having a long length and a strip wiring having a short length. 503b.
  • the other four-layer structure of the build-up layer 503 includes strip wires 503c, 503e, and 503g having a long length and strip wires 503d, 503f, and 503h having a short length, as in the case of the first layer. It is comprised by.
  • the short-length strip wirings 503b, 503d, 503f, and 503h disposed in the lower right portion of FIG. , 504j, and the strip wiring 503h is used as a signal output unit to communicate with other circuits.
  • the signal transmission characteristic in the multilayer printed wiring board of FIG. 10 is considerably worse in the signal path L (2) than in the signal path L (1). This is because the signal transmission characteristics of the center conductor (through-hole via) 505 are poor.
  • the upper end portion of the center conductor 505 and the strip wiring 502j immediately above it, and the lower end portion of the center conductor 505 and the strip wiring 503a directly below it face each other at a short distance. For this reason, the central conductor 505 and the strip wirings 502j and 503a are coupled to attenuate the signal. Therefore, it is strongly expected to improve the signal transmission characteristics of the central conductor 505.
  • Patent Document 1 In order to improve the signal transmission characteristics of the center conductor (through-hole via) 505, in Patent Document 1, openings are formed in strip wirings 502j and 503a existing above and below the center conductor (through-hole via) 505 as shown in FIG. The department is set up to deal with it. The contents of Patent Document 1 will be described with reference to FIG.
  • the multilayer printed wiring board shown in FIG. 11 is formed of the following seven layers. From the top, a conductor layer 606a, a power supply solid layer 601a, a signal wiring 602a, a power supply solid layer 601c, a signal wiring 602b, a power supply solid layer 601b, and a conductor layer 606b, respectively. Between these conductors, an insulator layer 607 is present to maintain insulation between the conductors.
  • a through hole 604 is provided in the center of FIG. 11, and a signal wiring 602a and a signal wiring 602b are connected to the through hole 604. The signal is transmitted from the left end of the signal wiring 602a through the through hole 604 to the right end of the signal wiring 602b. At both ends of the through hole 604, there are through hole pads 603a and 603b formed when the through hole 604 is formed.
  • FIG. 11 are power supply solid layers 601a and 601b (planes) having openings 605a and 605b, respectively, above and below the through hole 604 in FIG.
  • the through-hole pads 603a and 603b and the power supply solid layers 601a and 601b have less electromagnetic coupling, respectively. As a result, signal power loss is reduced, and signal transmission characteristics are improved.
  • FIG. 12 shows and explains the structure.
  • the layer structure of the multilayer printed wiring board of FIG. 12 is formed by four layers of wiring.
  • the uppermost layer is provided with a wiring pattern 703a
  • the next layer is provided with solid layers 701a and 701c
  • the third layer is provided with solid layers 701b and 701d
  • the lowermost layer is provided with a wiring pattern 703b.
  • a through hole 704 having a coaxial structure passes through the center of the multilayer printed wiring board in the center of FIG.
  • the coaxial through hole 704 insulates the first copper plating portion 705, the second copper plating portion 706 surrounding the copper plating arm 705, and the copper plating portions 705 and 706. And an insulator portion 707.
  • the second copper plating portion 706 is connected to the solid layers 701a to 701d and grounded.
  • the solid layers 701a to 701d and the wiring patterns 703a and 703b are insulated from each other by insulating layers 702a to 702c, respectively.
  • the signal passes through the first copper plating portion 705 from the right end of the wiring pattern 703a in the upper part of FIG. 12, and is transmitted to the left end of the wiring pattern 703b in the lower part of FIG. Because of the coaxial structure, there is little influence from the outside, so that the signal transmission characteristics are improved.
  • FIG. 13 shows and describes the structure.
  • the multilayer printed wiring board of FIG. 13 is formed of four layers of wiring.
  • Wiring patterns 803a and 803b are installed in the uppermost layer, a ground layer 801a is installed in the next layer, a ground layer 801b is installed in the third layer, and a wiring pattern 803c and a wiring pattern 803d are installed in the lowermost layer.
  • the first through-hole portion 804 and the second through-hole portions 805a and 805b penetrate the central portion of FIG.
  • the second through-hole portions 805a and 805b are surrounded by the insulator portion 807 and the first through-hole portion 804.
  • the first through-hole portion 804 and the second through-hole portions 805a and 805b are configured by plating portions 806a and 806b, respectively.
  • the first through-hole portion 804 is connected to the ground layers 801a and 801b and includes a plating portion 806c.
  • the wiring patterns 803a to 803d and the power supply or ground layers 801a and 801b are insulated from each other by insulator layers 802a to 802c.
  • the signal is transmitted from the wiring patterns 803a and 803b in the upper part of the drawing to the wiring patterns 803c and 803d in the lower part of the drawing through the second through holes 805a and 805b. Because of the coaxial structure, there is little influence from the outside, so that the signal transmission characteristics are improved.
  • Patent Document 4 as in Patent Documents 2 and 3, a coaxial signal line is realized to reduce external influences and improve signal transmission characteristics.
  • Patent Document 5 describes a structure in which a through-hole conductor is connected to a power supply pattern and a ground pattern.
  • Patent Documents 6 to 11 also propose a through hole structure and a forming method of a coaxial structure.
  • the signal transmission characteristics of 10 GHz or more as described above have a problem that the vertical signal transmission line (through-hole via) in the multilayer printed board is worse than the strip wiring or the microstrip wiring. This is because the power plane and ground plane above and below the through-hole via are coupled and the signal is attenuated.
  • openings are provided in the power plane and the ground plane above and below the through-hole via.
  • Patent Document 1 has a problem that a large number of openings are required in the plane when a large number of high-speed wirings pass through through-hole vias. If there are many openings in the power plane and ground plane, the resistance of the plane will increase. In addition, if there is an LSI that passes a large amount of current in the vicinity, the operation of the LSI becomes unstable due to a voltage drop, and in the worst case, it does not operate. Regarding other Patent Documents 2 to 11, the above-mentioned problem in Patent Document 1 is not solved at all.
  • the present invention relates to a multilayer printed wiring board capable of achieving both high-speed signal transmission and high density in the wiring without increasing the resistance of the plane on the high-density multilayer printed wiring board and its structure.
  • the purpose is to provide
  • a multilayer printed wiring board includes a build-up layer deposited on at least one surface of a core layer, and a cylindrical external body penetrating the core layer and connected to the core layer.
  • a signal via is provided at the central conductor end portion, and the diameter of the signal via is smaller than the diameter of the central conductor end portion. It is characterized by that.
  • the upper and lower planes are compared with the case where only the large-diameter central conductor is installed.
  • the amount of electrical coupling can be reduced, thereby reducing the impedance on the signal transmission path, so high-speed transmission signals can be sent from the front surface to the back surface of the printed wiring board without providing openings in the plane. Can pass through.
  • FIG. 1 It is a fragmentary sectional view showing a 1st embodiment of a multilayer printed wiring board of the present invention. It is a fragmentary sectional view along the II line in FIG. It is a fragmentary sectional view which shows the sample (related technique) used for the collection of the comparison data by the simulation about the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG. It is a fragmentary sectional view which shows the sample (patent document 1) used for the collection of the comparison data by the simulation about the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG.
  • FIG. 1st Embodiment multilayer printed wiring board
  • A data insertion loss
  • B return loss
  • the multilayer printed wiring board includes a buildup layer 21 a deposited on at least one surface of the core layer 20, and a cylinder that penetrates the central portion of the core layer 20 and is connected to the core layer 20.
  • the wiring provided in the build-up layer 21 a is disposed so as to face the end portion of the central conductor 11.
  • a signal via 12 a is provided at the end of the central conductor 11, and the diameter of the signal via 12 a is smaller than the diameter of the end of the central conductor 11. This will be described more specifically below.
  • FIG. 1 is a partial cross-sectional view showing a multilayer printed wiring board according to the first embodiment.
  • the multilayer printed wiring board includes a core layer 20 and buildup layers 21a and 21b deposited on the upper surface side and the lower surface side of the core layer 20, respectively.
  • the center conductor 11 penetrates through the center of the core layer 20 as shown in the figure.
  • the center conductor 11 is configured to have a coaxial structure with the outer conductor 15 inside the cylindrical outer conductor 15 connected to the core layer 20.
  • Signal vias 12a and 12b are provided at both ends of the central conductor 11, and the diameters of the signal vias 12a and 12b are set smaller than the diameter of the end of the central conductor 11, as described above.
  • the core conductor 20 in FIG. 1 is provided with the central conductor 11 on the central axis, and the outer conductor 15 surrounds the periphery thereof as described above.
  • the inside of the center conductor 11 is filled with a conductor material by plating.
  • the outer conductor 15 is connected to eight ground layers 501a.
  • a dielectric 511 is filled between the respective layers.
  • the buildup layer 21a on the upper surface side is composed of the strip line 13a and the plane 14a provided on the strip line 13a, and a dielectric 19a that insulates them.
  • the build-up layer 21b on the lower surface side is constituted by a strip line 13b and a plane 14b provided below the strip line 13b and a dielectric 19b that insulates them.
  • FIG. 2 is a partial cross-sectional view taken along the line II of FIG. In FIG. 2, the center conductor 11, the cylindrical outer conductor 15 formed so as to surround the center conductor 11, the signal via 12a connected to the center conductor 11, and the above-described strip connected to the signal via 12a. The interrelationship with the line 13a is shown.
  • the outer diameters of both end portions of the central conductor 11 are larger than the central portion, which appears due to the manufacturing process.
  • a cylindrical hole is opened in the dielectric 18.
  • plating is performed on the entire outer and inner surfaces such as the front and back surfaces of the core layer and the cylindrical holes.
  • plating of portions other than the wiring inside the cylindrical hole and the upper and lower surfaces of the core layer is removed by etching.
  • Other configurations are the same as those of the related technique shown in FIG.
  • a transmission signal passes from the left end of the upper layer strip wiring 13a in FIG. 1 to the right end of the lower layer strip wiring 13b through the signal via 12a, the central conductor 11, and the signal via 12b.
  • the signal transmission characteristic of the multilayer printed wiring board according to the first embodiment is excellent, a comparison of the signal transmission characteristics of the insertion loss and the return loss of two types of known structures. A simulation was performed.
  • the multilayer printed wiring board of FIG. 1 according to the first embodiment is used as the first structure.
  • the second structure is the structure in the related art shown in FIG. 3
  • the third structure is the one disclosed in Patent Document 1 shown in FIG.
  • the third structure shows a structure in which openings exist in the upper and lower planes of the through-hole via pads.
  • FIG. 3 the basic structure of FIG. 3 (the second structure) is the same as FIG. Differences from FIG. 1 are as follows. (1) The signal vias 12a and 12b in FIG. 1 do not exist. The strip wirings 501p and 501s are directly connected to the central conductor 505. (2) The outer conductor 15 does not exist, and the ground layer 501a directly surrounds the central conductor 505. (3) The center conductor 505 is hollow and a dielectric 512 is inserted. Since the amount of coupling with the upper and lower planes 502j and 503a is smaller than that of the central conductor 11 of the present invention in which the hollow is completely filled, it is assumed that the signal transmission characteristics are improved.
  • FIG. 4 is the same as that in FIG. 3 (the third structure). Differences from FIG. 3 are as follows. (1) Openings 22a and 22b having the same diameter as that of the ground layer 501a are present in the planes 502j and 503a.
  • the dimension values of FIG. 1 and the simulation results are shown below.
  • the conductor is a perfect conductor, and the dielectric constant of the dielectric is 3.35.
  • the high frequency characteristics from the left end of the upper layer strip wiring 13a to the right end of the lower layer strip wiring 13b were confirmed by simulation.
  • a curve 51 and a curve 61 in FIG. 5 are calculation results of insertion loss due to simulation and loss due to reflection (return loss) in the structure (first structure) in FIG. According to this result, when the vertical signal transmission line of the present invention is used, the insertion loss is ⁇ 0.5 dB and the return loss is ⁇ 17 dB at 20 GHz.
  • a curve 53 and a curve 63 in FIG. 5 are calculation results of insertion loss and loss due to reflection (return loss) in the structure (second structure) in FIG. 3, respectively. According to this result, in the case of a normal through-hole structure, there is an insertion loss of ⁇ 9 dB and a return loss of ⁇ 5 dB at 20 GHz.
  • the dimension values in FIG. 4 and the simulation results will be described.
  • the dimension values were exactly the same as those in the structure of FIG. 3 except that the openings 22a and 22b were provided in the planes 502j and 503a.
  • a curve 52 and a curve 62 in FIG. 5 indicate an insertion loss and a return loss, respectively, in the structure (third structure) in FIG.
  • the insertion loss is ⁇ 3.5 dB at 20 GHz and the return loss is ⁇ 12 dB, which is an improvement over the characteristics of the through hole when there is no opening in the planes 502j and 503a.
  • the simulation result (curve 51 and curve 61) of FIG. 1 which is the multilayer printed wiring board (first structure) of the first embodiment has an insertion loss of ⁇ 0.5 dB and a return loss of ⁇ 17 dB at 20 GHz. Further improvement is achieved compared to the simulation results (curve 52 and curve 62) in the structure of FIG. 4 (method of Patent Document 1, third structure).
  • the central conductor 505 of FIGS. 3 and 4 is hollow, and the amount of coupling between the upper and lower planes 502j and 503a is smaller than that of the central conductor 11 of the present invention in which the hollow is completely filled. Therefore, although the signal transmission characteristics are improved, the signal characteristics of the present invention are improved.
  • the first embodiment has the following effects.
  • a vertical signal transmission line with good high-frequency characteristics can be formed even when the planes 14a and 14b in FIG. 1 have no openings. It is not necessary to provide openings in the upper and lower planes 14a and 14b of the central conductor 11 in FIG. 1, and the resistance of the ground planes 14a and 14b is not increased. Therefore, a high-speed transmission signal can be passed from the upper surface to the lower surface of the multilayer printed wiring board. According to the first embodiment, there is an effect that both high-speed signal transmission and high-density mounting can be realized.
  • the diameter of the signal vias 12a and 12b in FIG. 1 is smaller than the central conductor 11, the wiring density in the build-up layers 21a and 21b can be further increased. Further, by connecting the external conductor and the power supply layer or the ground layer, there is an effect of further reducing the resistance between the power supply layer and the ground layer, so that power supply to the LSI can be facilitated.
  • FIG. 6 shows the structure of the second embodiment of the multilayer printed wiring board of the present invention.
  • the signal vias 12a and 12b arranged in the respective build-up layers 21a and 21b in FIG. 1 have a four-layer stacked via structure in FIG.
  • Another system of strip wirings 31a and 31b is arranged around the signal via 12a, and another system of strip wirings 31c and 31d is arranged around the signal via 12b.
  • the signal vias 12a and 12b have a stacked stack via structure, the vias installed in each layer can be connected to the strip wiring installed in that layer. Therefore, the signal vias 12a and 12b can be accessed from any layer. Therefore, there is an effect that a signal can be extracted from an arbitrary layer of the buildup layer without deteriorating the signal transmission characteristics.
  • Other configurations and operational effects are the same as those of the first embodiment.
  • FIG. 7 shows the structure of the third embodiment of the multilayer printed wiring board of the present invention.
  • FIG. 7 shows a partial sectional view of a third embodiment of the present invention.
  • the differences from the second embodiment (FIG. 6) are as follows.
  • the shield vias 33a to 33d connected to the shield vias 32a to 32d having a stack via structure around the signal vias 12a and 12b arranged in the respective buildup layers 21a and 21b of FIG. 33d is that it is installed.
  • Shield vias 32a and 32b and shield wirings 33a and 33b are installed around the signal via 12a in FIG.
  • FIG. 8 shows a plan view seen from II-II in FIG. Eight rows of shield vias 32 are arranged so as to surround the signal vias 12a.
  • the shield wiring 33 is closer to the signal via 12a than the shield via 32, and surrounds the signal via 12a.
  • the shield wiring 33 surrounds the signal vias 12a and 12b due to the presence of the shield wiring 33, the shield wiring 33 can block electromagnetic waves from the outside and the inside. Therefore, there is an effect that leakage loss from the signal vias 12a and 12b is reduced and that it is hardly affected by external noise.
  • Other configurations and operational effects are the same as those of the first and second embodiments described above.
  • FIG. 9 shows the structure of the fourth embodiment of the multilayer printed wiring board of the present invention.
  • FIG. 9 shows a partial cross-sectional view of the fourth embodiment of the present invention.
  • the difference from FIG. 1 is that second power / ground layers 42a to 42d exist.
  • the external conductor 15 is connected to the first power / ground layers 41a to 41c and is not connected to the second power / ground layers 42a to 42d.
  • the first power supply / ground layers 41a to 41c can be set to the ground potential
  • the second power supply / ground layers 42a to 42d can be set to the power supply potential (this type of structure is referred to as type 1 herein).
  • the first power supply / ground layers 41a to 41c can be set to the power supply potential
  • the second power supply / ground layers 42a to 42d can be set to the ground potential (this type of structure is referred to as type 2 herein). ).
  • the outer conductor 15 Even if the potential of the outer conductor 15 is not a ground potential, if the potential is constant without fluctuation, the outer conductor 15 has an electromagnetic wave blocking effect on the vertical signal transmission line in the present embodiment. Therefore, the outer conductor 15 having a constant potential without changing the potential does not affect the high frequency characteristics of the vertical signal transmission line. Therefore, it is possible to reduce the resistance by connecting the power supply layer or the ground layer having the same potential via the external conductor while keeping the signal transmission characteristics good. Further, in a multilayer printed wiring board having N vertical signal transmission lines, about N / 2 pieces can have a type 1 structure, and about N / 2 pieces can have a type 2 structure.
  • the resistance of the power supply layer and the ground layer can be lowered by the large number of external conductors 15, and the potential can be stabilized such that the fluctuations of the power supply potential and the ground potential in each wiring are reduced.
  • This enables stable power supply without causing a voltage drop even if an LSI that carries a large current is mounted.
  • Other configurations and operational effects are the same as those of the first embodiment.
  • the present invention can contribute to both high-speed signal transmission and high density in the wiring without increasing the resistance of the plane on the high-density multilayer printed wiring board.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé pour améliorer les caractéristiques haute fréquence d'un trou d'interconnexion débouchant dans une carte de circuits imprimés à plusieurs couches, dans lequel les parties supérieure et inférieure du trou d'interconnexion débouchant s'ouvrent sur des plans de puissance/masse. Cependant, le problème est que les ouvertures augmentent la résistance des plans de puissance/masse, compliquant l'alimentation électrique de la puce LSI. L'invention concerne donc une carte de circuits imprimés à plusieurs couches, ladite carte de circuits imprimés comprenant : des couches d'accumulation (21a) stratifiées sur les deux côtés d'une couche de noyau (20) ; un conducteur extérieur (15) cylindrique traversant la couche de noyau (20) ; un conducteur central (11) formé à l'intérieur de la couche de noyau (20) de façon à constituer une structure coaxiale avec le conducteur extérieur (15) ; et un isolateur (18) entre le conducteur central (11) et le conducteur extérieur (15). Le câblage sur les couches d'accumulation (21a) est disposé opposé aux deux extrémités du conducteur central (11). La carte de circuits imprimés à plusieurs couches selon l'invention est caractérisée par la fourniture de trous d'interconnexion de signal (12a) aux deux extrémités du conducteur central (11), les diamètres desdits trous d'interconnexion de signal (12a) étant inférieurs aux diamètres des extrémités du conducteur central (11).
PCT/JP2010/062424 2009-08-12 2010-07-23 Carte de circuits imprimés à plusieurs couches WO2011018938A1 (fr)

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JP2011526711A JPWO2011018938A1 (ja) 2009-08-12 2010-07-23 多層プリント配線板

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JP2009187227 2009-08-12
JP2009-187227 2009-08-12

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WO2011018938A1 true WO2011018938A1 (fr) 2011-02-17

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PCT/JP2010/062424 WO2011018938A1 (fr) 2009-08-12 2010-07-23 Carte de circuits imprimés à plusieurs couches

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JP2013214741A (ja) * 2012-04-02 2013-10-17 Kofukin Seimitsu Kogyo (Shenzhen) Yugenkoshi フレキシブル回路基板
JP2014175356A (ja) * 2013-03-06 2014-09-22 Renesas Electronics Corp 半導体装置
CN104604345A (zh) * 2012-08-31 2015-05-06 索尼公司 布线板及布线板的制造方法
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JP2017085132A (ja) * 2016-12-15 2017-05-18 ルネサスエレクトロニクス株式会社 半導体装置
JP2017199763A (ja) * 2016-04-26 2017-11-02 京セラ株式会社 印刷配線板およびその製造方法
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WO2021153016A1 (fr) * 2020-01-30 2021-08-05 京セラ株式会社 Carte de câblage

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JP2012256675A (ja) * 2011-06-08 2012-12-27 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びその製造方法
JP2013214741A (ja) * 2012-04-02 2013-10-17 Kofukin Seimitsu Kogyo (Shenzhen) Yugenkoshi フレキシブル回路基板
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JP2014175356A (ja) * 2013-03-06 2014-09-22 Renesas Electronics Corp 半導体装置
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JP7431865B2 (ja) 2020-01-30 2024-02-15 京セラ株式会社 配線基板

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