WO2011018938A1 - Multilayer printed circuit board - Google Patents

Multilayer printed circuit board Download PDF

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Publication number
WO2011018938A1
WO2011018938A1 PCT/JP2010/062424 JP2010062424W WO2011018938A1 WO 2011018938 A1 WO2011018938 A1 WO 2011018938A1 JP 2010062424 W JP2010062424 W JP 2010062424W WO 2011018938 A1 WO2011018938 A1 WO 2011018938A1
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WO
WIPO (PCT)
Prior art keywords
multilayer printed
layer
conductor
wiring board
printed wiring
Prior art date
Application number
PCT/JP2010/062424
Other languages
French (fr)
Japanese (ja)
Inventor
薫 成田
Original Assignee
日本電気株式会社
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Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2011526711A priority Critical patent/JPWO2011018938A1/en
Publication of WO2011018938A1 publication Critical patent/WO2011018938A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09618—Via fence, i.e. one-dimensional array of vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present invention relates to a signal transmission line of a multilayer printed wiring board, and more particularly to a multilayer printed wiring board having a vertical signal transmission line (through-hole via) structure.
  • FIG. 10 is a partial sectional view showing a signal path of the multilayer printed wiring board.
  • a multilayer printed wiring board is composed of a core layer 501 consisting of eight layers as a layer structure, one build-up layer 502 consisting of four layers provided on the upper surface side of the core layer 501 in FIG.
  • the other build-up layer 503 consisting of four layers provided on the lower surface side of the layer 501 in FIG. 10 is provided.
  • the core layer 501 and the buildup layers 502 and 503 constitute part or all of the signal paths L (1) and L (2), respectively, as will be described later.
  • the core layer 501 includes eight ground layers 501a, 501a,... Including a ground layer. Of the eight conductor layers, in the example of FIG. 10, the first layer (the layer facing the bottom layer of one buildup layer 502 in FIG. 10) and the eighth layer (the other buildup layer in FIG. 10).
  • the signal path conductor layers 501p and 501s are formed on a part of each of the uppermost layer 503), and the other layers function as the ground layer 501a.
  • a dielectric 511 is filled between the ground layers 501a.
  • a dielectric 513 is filled between each of the buildup layers 502 and 503 described above.
  • a cylindrical center conductor (through-hole via) 505 is disposed so as to penetrate the core layer 501 (over the vertical direction in FIG. 10).
  • the center conductor 505 is filled with a dielectric 512.
  • the four-layer structure of one of the buildup layers 502 described above is divided into four strip wirings as shown by reference numerals 502a, 502b, 502c, and 502d from the left side in FIG. Has been.
  • the second layer is divided into two strip wirings as indicated by reference numerals 502e and 502f.
  • the third layer is divided into two strip wirings as indicated by reference numerals 502g and 502h, and the fourth layer is divided into two strip wirings as indicated by reference numerals 502i and 502j.
  • the signal path L (1) uses the second strip wiring 502b from the left of the first layer of the buildup layer 502 as a signal input unit, and is a signal via. 504b communicates with the second-layer strip wiring 502f, and then communicates from the strip wiring 502f to the first-layer strip wiring 502d of the buildup layer 502 via the signal via 504c on the right end side of FIG. The wiring 502d is communicated with other circuits using the signal output unit.
  • the signal path L (2) uses the first strip wiring 502a from the left of the first layer of the buildup layer 502 as a signal input unit, and the strip wirings 502e, 502g, 502i is sequentially communicated through signal vias 504a, 504d, 504e, and 504f that are preliminarily connected and connected to the other buildup layer 503 via the central conductor (through-hole via) 505 of the core layer 501 described above. It is configured to be.
  • Reference numerals 501p and 501s denote communication layers that connect the build-up layers 502 and 503 and the end portions of the central conductor (through-hole via) 505 from the upper left in FIG. 10 toward the lower right in FIG.
  • Passing signals from the front side to the back side of the printed wiring board is highly demanded from the viewpoint of high-density mounting because it can increase the mounting density by mounting parts such as LSI on both sides of the printed wiring board. It is.
  • the upper layer (core layer 501 side) in FIG. 10 is the first layer, and this first layer is a strip wiring 503a having a long length and a strip wiring having a short length. 503b.
  • the other four-layer structure of the build-up layer 503 includes strip wires 503c, 503e, and 503g having a long length and strip wires 503d, 503f, and 503h having a short length, as in the case of the first layer. It is comprised by.
  • the short-length strip wirings 503b, 503d, 503f, and 503h disposed in the lower right portion of FIG. , 504j, and the strip wiring 503h is used as a signal output unit to communicate with other circuits.
  • the signal transmission characteristic in the multilayer printed wiring board of FIG. 10 is considerably worse in the signal path L (2) than in the signal path L (1). This is because the signal transmission characteristics of the center conductor (through-hole via) 505 are poor.
  • the upper end portion of the center conductor 505 and the strip wiring 502j immediately above it, and the lower end portion of the center conductor 505 and the strip wiring 503a directly below it face each other at a short distance. For this reason, the central conductor 505 and the strip wirings 502j and 503a are coupled to attenuate the signal. Therefore, it is strongly expected to improve the signal transmission characteristics of the central conductor 505.
  • Patent Document 1 In order to improve the signal transmission characteristics of the center conductor (through-hole via) 505, in Patent Document 1, openings are formed in strip wirings 502j and 503a existing above and below the center conductor (through-hole via) 505 as shown in FIG. The department is set up to deal with it. The contents of Patent Document 1 will be described with reference to FIG.
  • the multilayer printed wiring board shown in FIG. 11 is formed of the following seven layers. From the top, a conductor layer 606a, a power supply solid layer 601a, a signal wiring 602a, a power supply solid layer 601c, a signal wiring 602b, a power supply solid layer 601b, and a conductor layer 606b, respectively. Between these conductors, an insulator layer 607 is present to maintain insulation between the conductors.
  • a through hole 604 is provided in the center of FIG. 11, and a signal wiring 602a and a signal wiring 602b are connected to the through hole 604. The signal is transmitted from the left end of the signal wiring 602a through the through hole 604 to the right end of the signal wiring 602b. At both ends of the through hole 604, there are through hole pads 603a and 603b formed when the through hole 604 is formed.
  • FIG. 11 are power supply solid layers 601a and 601b (planes) having openings 605a and 605b, respectively, above and below the through hole 604 in FIG.
  • the through-hole pads 603a and 603b and the power supply solid layers 601a and 601b have less electromagnetic coupling, respectively. As a result, signal power loss is reduced, and signal transmission characteristics are improved.
  • FIG. 12 shows and explains the structure.
  • the layer structure of the multilayer printed wiring board of FIG. 12 is formed by four layers of wiring.
  • the uppermost layer is provided with a wiring pattern 703a
  • the next layer is provided with solid layers 701a and 701c
  • the third layer is provided with solid layers 701b and 701d
  • the lowermost layer is provided with a wiring pattern 703b.
  • a through hole 704 having a coaxial structure passes through the center of the multilayer printed wiring board in the center of FIG.
  • the coaxial through hole 704 insulates the first copper plating portion 705, the second copper plating portion 706 surrounding the copper plating arm 705, and the copper plating portions 705 and 706. And an insulator portion 707.
  • the second copper plating portion 706 is connected to the solid layers 701a to 701d and grounded.
  • the solid layers 701a to 701d and the wiring patterns 703a and 703b are insulated from each other by insulating layers 702a to 702c, respectively.
  • the signal passes through the first copper plating portion 705 from the right end of the wiring pattern 703a in the upper part of FIG. 12, and is transmitted to the left end of the wiring pattern 703b in the lower part of FIG. Because of the coaxial structure, there is little influence from the outside, so that the signal transmission characteristics are improved.
  • FIG. 13 shows and describes the structure.
  • the multilayer printed wiring board of FIG. 13 is formed of four layers of wiring.
  • Wiring patterns 803a and 803b are installed in the uppermost layer, a ground layer 801a is installed in the next layer, a ground layer 801b is installed in the third layer, and a wiring pattern 803c and a wiring pattern 803d are installed in the lowermost layer.
  • the first through-hole portion 804 and the second through-hole portions 805a and 805b penetrate the central portion of FIG.
  • the second through-hole portions 805a and 805b are surrounded by the insulator portion 807 and the first through-hole portion 804.
  • the first through-hole portion 804 and the second through-hole portions 805a and 805b are configured by plating portions 806a and 806b, respectively.
  • the first through-hole portion 804 is connected to the ground layers 801a and 801b and includes a plating portion 806c.
  • the wiring patterns 803a to 803d and the power supply or ground layers 801a and 801b are insulated from each other by insulator layers 802a to 802c.
  • the signal is transmitted from the wiring patterns 803a and 803b in the upper part of the drawing to the wiring patterns 803c and 803d in the lower part of the drawing through the second through holes 805a and 805b. Because of the coaxial structure, there is little influence from the outside, so that the signal transmission characteristics are improved.
  • Patent Document 4 as in Patent Documents 2 and 3, a coaxial signal line is realized to reduce external influences and improve signal transmission characteristics.
  • Patent Document 5 describes a structure in which a through-hole conductor is connected to a power supply pattern and a ground pattern.
  • Patent Documents 6 to 11 also propose a through hole structure and a forming method of a coaxial structure.
  • the signal transmission characteristics of 10 GHz or more as described above have a problem that the vertical signal transmission line (through-hole via) in the multilayer printed board is worse than the strip wiring or the microstrip wiring. This is because the power plane and ground plane above and below the through-hole via are coupled and the signal is attenuated.
  • openings are provided in the power plane and the ground plane above and below the through-hole via.
  • Patent Document 1 has a problem that a large number of openings are required in the plane when a large number of high-speed wirings pass through through-hole vias. If there are many openings in the power plane and ground plane, the resistance of the plane will increase. In addition, if there is an LSI that passes a large amount of current in the vicinity, the operation of the LSI becomes unstable due to a voltage drop, and in the worst case, it does not operate. Regarding other Patent Documents 2 to 11, the above-mentioned problem in Patent Document 1 is not solved at all.
  • the present invention relates to a multilayer printed wiring board capable of achieving both high-speed signal transmission and high density in the wiring without increasing the resistance of the plane on the high-density multilayer printed wiring board and its structure.
  • the purpose is to provide
  • a multilayer printed wiring board includes a build-up layer deposited on at least one surface of a core layer, and a cylindrical external body penetrating the core layer and connected to the core layer.
  • a signal via is provided at the central conductor end portion, and the diameter of the signal via is smaller than the diameter of the central conductor end portion. It is characterized by that.
  • the upper and lower planes are compared with the case where only the large-diameter central conductor is installed.
  • the amount of electrical coupling can be reduced, thereby reducing the impedance on the signal transmission path, so high-speed transmission signals can be sent from the front surface to the back surface of the printed wiring board without providing openings in the plane. Can pass through.
  • FIG. 1 It is a fragmentary sectional view showing a 1st embodiment of a multilayer printed wiring board of the present invention. It is a fragmentary sectional view along the II line in FIG. It is a fragmentary sectional view which shows the sample (related technique) used for the collection of the comparison data by the simulation about the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG. It is a fragmentary sectional view which shows the sample (patent document 1) used for the collection of the comparison data by the simulation about the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG.
  • FIG. 1st Embodiment multilayer printed wiring board
  • A data insertion loss
  • B return loss
  • the multilayer printed wiring board includes a buildup layer 21 a deposited on at least one surface of the core layer 20, and a cylinder that penetrates the central portion of the core layer 20 and is connected to the core layer 20.
  • the wiring provided in the build-up layer 21 a is disposed so as to face the end portion of the central conductor 11.
  • a signal via 12 a is provided at the end of the central conductor 11, and the diameter of the signal via 12 a is smaller than the diameter of the end of the central conductor 11. This will be described more specifically below.
  • FIG. 1 is a partial cross-sectional view showing a multilayer printed wiring board according to the first embodiment.
  • the multilayer printed wiring board includes a core layer 20 and buildup layers 21a and 21b deposited on the upper surface side and the lower surface side of the core layer 20, respectively.
  • the center conductor 11 penetrates through the center of the core layer 20 as shown in the figure.
  • the center conductor 11 is configured to have a coaxial structure with the outer conductor 15 inside the cylindrical outer conductor 15 connected to the core layer 20.
  • Signal vias 12a and 12b are provided at both ends of the central conductor 11, and the diameters of the signal vias 12a and 12b are set smaller than the diameter of the end of the central conductor 11, as described above.
  • the core conductor 20 in FIG. 1 is provided with the central conductor 11 on the central axis, and the outer conductor 15 surrounds the periphery thereof as described above.
  • the inside of the center conductor 11 is filled with a conductor material by plating.
  • the outer conductor 15 is connected to eight ground layers 501a.
  • a dielectric 511 is filled between the respective layers.
  • the buildup layer 21a on the upper surface side is composed of the strip line 13a and the plane 14a provided on the strip line 13a, and a dielectric 19a that insulates them.
  • the build-up layer 21b on the lower surface side is constituted by a strip line 13b and a plane 14b provided below the strip line 13b and a dielectric 19b that insulates them.
  • FIG. 2 is a partial cross-sectional view taken along the line II of FIG. In FIG. 2, the center conductor 11, the cylindrical outer conductor 15 formed so as to surround the center conductor 11, the signal via 12a connected to the center conductor 11, and the above-described strip connected to the signal via 12a. The interrelationship with the line 13a is shown.
  • the outer diameters of both end portions of the central conductor 11 are larger than the central portion, which appears due to the manufacturing process.
  • a cylindrical hole is opened in the dielectric 18.
  • plating is performed on the entire outer and inner surfaces such as the front and back surfaces of the core layer and the cylindrical holes.
  • plating of portions other than the wiring inside the cylindrical hole and the upper and lower surfaces of the core layer is removed by etching.
  • Other configurations are the same as those of the related technique shown in FIG.
  • a transmission signal passes from the left end of the upper layer strip wiring 13a in FIG. 1 to the right end of the lower layer strip wiring 13b through the signal via 12a, the central conductor 11, and the signal via 12b.
  • the signal transmission characteristic of the multilayer printed wiring board according to the first embodiment is excellent, a comparison of the signal transmission characteristics of the insertion loss and the return loss of two types of known structures. A simulation was performed.
  • the multilayer printed wiring board of FIG. 1 according to the first embodiment is used as the first structure.
  • the second structure is the structure in the related art shown in FIG. 3
  • the third structure is the one disclosed in Patent Document 1 shown in FIG.
  • the third structure shows a structure in which openings exist in the upper and lower planes of the through-hole via pads.
  • FIG. 3 the basic structure of FIG. 3 (the second structure) is the same as FIG. Differences from FIG. 1 are as follows. (1) The signal vias 12a and 12b in FIG. 1 do not exist. The strip wirings 501p and 501s are directly connected to the central conductor 505. (2) The outer conductor 15 does not exist, and the ground layer 501a directly surrounds the central conductor 505. (3) The center conductor 505 is hollow and a dielectric 512 is inserted. Since the amount of coupling with the upper and lower planes 502j and 503a is smaller than that of the central conductor 11 of the present invention in which the hollow is completely filled, it is assumed that the signal transmission characteristics are improved.
  • FIG. 4 is the same as that in FIG. 3 (the third structure). Differences from FIG. 3 are as follows. (1) Openings 22a and 22b having the same diameter as that of the ground layer 501a are present in the planes 502j and 503a.
  • the dimension values of FIG. 1 and the simulation results are shown below.
  • the conductor is a perfect conductor, and the dielectric constant of the dielectric is 3.35.
  • the high frequency characteristics from the left end of the upper layer strip wiring 13a to the right end of the lower layer strip wiring 13b were confirmed by simulation.
  • a curve 51 and a curve 61 in FIG. 5 are calculation results of insertion loss due to simulation and loss due to reflection (return loss) in the structure (first structure) in FIG. According to this result, when the vertical signal transmission line of the present invention is used, the insertion loss is ⁇ 0.5 dB and the return loss is ⁇ 17 dB at 20 GHz.
  • a curve 53 and a curve 63 in FIG. 5 are calculation results of insertion loss and loss due to reflection (return loss) in the structure (second structure) in FIG. 3, respectively. According to this result, in the case of a normal through-hole structure, there is an insertion loss of ⁇ 9 dB and a return loss of ⁇ 5 dB at 20 GHz.
  • the dimension values in FIG. 4 and the simulation results will be described.
  • the dimension values were exactly the same as those in the structure of FIG. 3 except that the openings 22a and 22b were provided in the planes 502j and 503a.
  • a curve 52 and a curve 62 in FIG. 5 indicate an insertion loss and a return loss, respectively, in the structure (third structure) in FIG.
  • the insertion loss is ⁇ 3.5 dB at 20 GHz and the return loss is ⁇ 12 dB, which is an improvement over the characteristics of the through hole when there is no opening in the planes 502j and 503a.
  • the simulation result (curve 51 and curve 61) of FIG. 1 which is the multilayer printed wiring board (first structure) of the first embodiment has an insertion loss of ⁇ 0.5 dB and a return loss of ⁇ 17 dB at 20 GHz. Further improvement is achieved compared to the simulation results (curve 52 and curve 62) in the structure of FIG. 4 (method of Patent Document 1, third structure).
  • the central conductor 505 of FIGS. 3 and 4 is hollow, and the amount of coupling between the upper and lower planes 502j and 503a is smaller than that of the central conductor 11 of the present invention in which the hollow is completely filled. Therefore, although the signal transmission characteristics are improved, the signal characteristics of the present invention are improved.
  • the first embodiment has the following effects.
  • a vertical signal transmission line with good high-frequency characteristics can be formed even when the planes 14a and 14b in FIG. 1 have no openings. It is not necessary to provide openings in the upper and lower planes 14a and 14b of the central conductor 11 in FIG. 1, and the resistance of the ground planes 14a and 14b is not increased. Therefore, a high-speed transmission signal can be passed from the upper surface to the lower surface of the multilayer printed wiring board. According to the first embodiment, there is an effect that both high-speed signal transmission and high-density mounting can be realized.
  • the diameter of the signal vias 12a and 12b in FIG. 1 is smaller than the central conductor 11, the wiring density in the build-up layers 21a and 21b can be further increased. Further, by connecting the external conductor and the power supply layer or the ground layer, there is an effect of further reducing the resistance between the power supply layer and the ground layer, so that power supply to the LSI can be facilitated.
  • FIG. 6 shows the structure of the second embodiment of the multilayer printed wiring board of the present invention.
  • the signal vias 12a and 12b arranged in the respective build-up layers 21a and 21b in FIG. 1 have a four-layer stacked via structure in FIG.
  • Another system of strip wirings 31a and 31b is arranged around the signal via 12a, and another system of strip wirings 31c and 31d is arranged around the signal via 12b.
  • the signal vias 12a and 12b have a stacked stack via structure, the vias installed in each layer can be connected to the strip wiring installed in that layer. Therefore, the signal vias 12a and 12b can be accessed from any layer. Therefore, there is an effect that a signal can be extracted from an arbitrary layer of the buildup layer without deteriorating the signal transmission characteristics.
  • Other configurations and operational effects are the same as those of the first embodiment.
  • FIG. 7 shows the structure of the third embodiment of the multilayer printed wiring board of the present invention.
  • FIG. 7 shows a partial sectional view of a third embodiment of the present invention.
  • the differences from the second embodiment (FIG. 6) are as follows.
  • the shield vias 33a to 33d connected to the shield vias 32a to 32d having a stack via structure around the signal vias 12a and 12b arranged in the respective buildup layers 21a and 21b of FIG. 33d is that it is installed.
  • Shield vias 32a and 32b and shield wirings 33a and 33b are installed around the signal via 12a in FIG.
  • FIG. 8 shows a plan view seen from II-II in FIG. Eight rows of shield vias 32 are arranged so as to surround the signal vias 12a.
  • the shield wiring 33 is closer to the signal via 12a than the shield via 32, and surrounds the signal via 12a.
  • the shield wiring 33 surrounds the signal vias 12a and 12b due to the presence of the shield wiring 33, the shield wiring 33 can block electromagnetic waves from the outside and the inside. Therefore, there is an effect that leakage loss from the signal vias 12a and 12b is reduced and that it is hardly affected by external noise.
  • Other configurations and operational effects are the same as those of the first and second embodiments described above.
  • FIG. 9 shows the structure of the fourth embodiment of the multilayer printed wiring board of the present invention.
  • FIG. 9 shows a partial cross-sectional view of the fourth embodiment of the present invention.
  • the difference from FIG. 1 is that second power / ground layers 42a to 42d exist.
  • the external conductor 15 is connected to the first power / ground layers 41a to 41c and is not connected to the second power / ground layers 42a to 42d.
  • the first power supply / ground layers 41a to 41c can be set to the ground potential
  • the second power supply / ground layers 42a to 42d can be set to the power supply potential (this type of structure is referred to as type 1 herein).
  • the first power supply / ground layers 41a to 41c can be set to the power supply potential
  • the second power supply / ground layers 42a to 42d can be set to the ground potential (this type of structure is referred to as type 2 herein). ).
  • the outer conductor 15 Even if the potential of the outer conductor 15 is not a ground potential, if the potential is constant without fluctuation, the outer conductor 15 has an electromagnetic wave blocking effect on the vertical signal transmission line in the present embodiment. Therefore, the outer conductor 15 having a constant potential without changing the potential does not affect the high frequency characteristics of the vertical signal transmission line. Therefore, it is possible to reduce the resistance by connecting the power supply layer or the ground layer having the same potential via the external conductor while keeping the signal transmission characteristics good. Further, in a multilayer printed wiring board having N vertical signal transmission lines, about N / 2 pieces can have a type 1 structure, and about N / 2 pieces can have a type 2 structure.
  • the resistance of the power supply layer and the ground layer can be lowered by the large number of external conductors 15, and the potential can be stabilized such that the fluctuations of the power supply potential and the ground potential in each wiring are reduced.
  • This enables stable power supply without causing a voltage drop even if an LSI that carries a large current is mounted.
  • Other configurations and operational effects are the same as those of the first embodiment.
  • the present invention can contribute to both high-speed signal transmission and high density in the wiring without increasing the resistance of the plane on the high-density multilayer printed wiring board.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A method for improving the high-frequency characteristics of a through-hole via in a multilayer printed circuit board, in which the top and bottom of the through-hole via open to power/ground planes, has been proposed. However, there is the problem that having openings increases the resistance of the power/ground planes, making power supply to the LSI chip difficult. Thus, a multilayer printed circuit board is disclosed, said circuit board comprising: build-up layers (21a) layered on both sides of a core layer (20); a cylindrical external conductor (15) going through the core layer (20); a central conductor (11) formed inside the core layer (20) so as to constitute a coaxial structure together with the external conductor (15); and an insulator (18) between the central conductor (11) and the external conductor (15). Wiring on the build-up layers (21a) is disposed opposite both ends of the central conductor (11). The disclosed multilayer printed circuit board is characterized by the provision of signal vias (12a) at both ends of the central conductor (11), the diameters of said signal vias (12a) being smaller than the diameters of the ends of the central conductor (11).

Description

多層プリント配線板Multilayer printed wiring board
　本発明は、多層プリント配線板の信号伝送線路に関し、特に、垂直方向信号伝送線路（スルーホールビア）の構造を備えた多層プリント配線板に関する。 The present invention relates to a signal transmission line of a multilayer printed wiring board, and more particularly to a multilayer printed wiring board having a vertical signal transmission line (through-hole via) structure.
　電子機器、特にデジタル電子回路の高密度化及び高速化には進展が著しいものがある。プリント配線板の高密度多層化が進み、数十層のプリント配線板が存在する。ＬＳＩの処理速度が上昇し、そこで生じた膨大なデータを他のＬＳＩに送信する必要が生じている。最高機種の電子機器、通信機器における多層プリント配線板上の信号伝送レートは、１秒間に１０Ｇビット（10Gb/s）以上にも達しており、信号に含まれる周波数成分は10GHz以上となる。さらに今後は高い実装密度、高いデータレートを求める傾向にある。そのような高い信号伝送レートの信号を多層プリント配線板の表面から裏面へ信号ロスを少ない状態で通すことは困難であった。これは、多層プリント配線板を縦に横切るスルーホールビアの信号伝送特性が悪いためであった。 There is a remarkable progress in increasing the density and speed of electronic devices, especially digital electronic circuits. As the printed wiring board is increased in density and density, several tens of layers of printed wiring boards exist. The processing speed of an LSI has increased, and it has become necessary to transmit the enormous amount of data generated there to another LSI. The signal transmission rate on the multilayer printed wiring board in the highest-class electronic devices and communication devices reaches 10 Gbit (10 Gb / s) or more per second, and the frequency component included in the signal is 10 GHz or more. Furthermore, in the future, there is a tendency to demand a high mounting density and a high data rate. It has been difficult to pass such a signal with a high signal transmission rate from the front surface to the back surface of the multilayer printed wiring board with little signal loss. This is because the signal transmission characteristic of the through-hole via that vertically traverses the multilayer printed wiring board is poor.
　多層プリント配線板に直接関係する関連技術の一例を図１０に示す。この図１０は、多層プリント配線板の信号経路を示す部分断面図である。 An example of the related technology directly related to the multilayer printed wiring board is shown in FIG. FIG. 10 is a partial sectional view showing a signal path of the multilayer printed wiring board.
　この図１０において、多層プリント配線板は、層構成として８層から成るコア層５０１と、このコア層５０１の図１０における上面側に設けられた４層から成る一方のビルドアップ層５０２と、コア層５０１の図１０における下面側に設けられた４層から成る他方のビルドアップ層５０３とを備えている。
これらのコア層５０１及び各ビルドアップ層５０２，５０３は、後述するように、それぞれ信号経路Ｌ（１），Ｌ（２）の一部又は全部を構成する。 In FIG. 10, a multilayer printed wiring board is composed of a core layer 501 consisting of eight layers as a layer structure, one build-up layer 502 consisting of four layers provided on the upper surface side of the core layer 501 in FIG. The other build-up layer 503 consisting of four layers provided on the lower surface side of the layer 501 in FIG. 10 is provided.
The core layer 501 and the buildup layers 502 and 503 constitute part or all of the signal paths L (1) and L (2), respectively, as will be described later.
　コア層５０１はグランド層を含む８層のグランド層５０１ａ，５０１ａ，・・・・により構成されている。この８層の導体層の内、この図１０の例では、１層目（図１０の一方のビルドアップ層５０２の最下層に対向する層）と８層目（図１０の他方のビルドアップ層５０３の最上層に対向する層）の各一部に、信号経路用の導体層５０１ｐ，５０１ｓが形成され、その他の層はグランド層５０１ａとして機能する構成となっている。
　そして、各グランド層５０１ａの相互間には、誘電体５１１が充填されている。また、前述した各ビルドアップ層５０２，５０３との相互間には、それぞれ誘電体５１３が充填されている。 The core layer 501 includes eight ground layers 501a, 501a,... Including a ground layer. Of the eight conductor layers, in the example of FIG. 10, the first layer (the layer facing the bottom layer of one buildup layer 502 in FIG. 10) and the eighth layer (the other buildup layer in FIG. 10). The signal path conductor layers 501p and 501s are formed on a part of each of the uppermost layer 503), and the other layers function as the ground layer 501a.
A dielectric 511 is filled between the ground layers 501a. A dielectric 513 is filled between each of the buildup layers 502 and 503 described above.
　このコア層５０１の中央部には、当該コア層５０１を貫通して（図１０の上下方向にわたって）円筒状の中心導体（スルーホールビア）５０５が配置されている。そして、この中心導体５０５内には、誘電体５１２が充填されている。 In the central portion of the core layer 501, a cylindrical center conductor (through-hole via) 505 is disposed so as to penetrate the core layer 501 (over the vertical direction in FIG. 10). The center conductor 505 is filled with a dielectric 512.
　前述した一方のビルドアップ層５０２の４層構造は、この図１０の部分断面図内において、一層目が、同図左側から符号５０２ａ，５０２ｂ，５０２ｃ，５０２ｄに示すように４つのストリップ配線に分断されている。又、二層目が符号５０２ｅ，５０２ｆに示すように２つのストリップ配線に分断されている。又、三層目が符号５０２ｇ，５０２ｈに示すように２つのストリップ配線に分断され、そして四層目が符号５０２ｉ，５０２ｊに示すように２つのストリップ配線に分断されている。 The four-layer structure of one of the buildup layers 502 described above is divided into four strip wirings as shown by reference numerals 502a, 502b, 502c, and 502d from the left side in FIG. Has been. The second layer is divided into two strip wirings as indicated by reference numerals 502e and 502f. The third layer is divided into two strip wirings as indicated by reference numerals 502g and 502h, and the fourth layer is divided into two strip wirings as indicated by reference numerals 502i and 502j.
　そして、前述した信号経路Ｌ（１），Ｌ（２）の内、信号経路Ｌ（１）は、ビルドアップ層５０２の一層目の左から２番目のストリップ配線５０２ｂを信号入力部とし、信号ビア５０４ｂを介して二層目のストリップ配線５０２ｆに連通され、続いてストリップ配線５０２ｆから図１０の右端側の信号ビア５０４ｃを介してビルドアップ層５０２の一層目のストリップ配線５０２ｄに連通され、このストリップ配線５０２ｄを信号出力部として他の回路へ連通されるようになっている。 Of the signal paths L (1) and L (2) described above, the signal path L (1) uses the second strip wiring 502b from the left of the first layer of the buildup layer 502 as a signal input unit, and is a signal via. 504b communicates with the second-layer strip wiring 502f, and then communicates from the strip wiring 502f to the first-layer strip wiring 502d of the buildup layer 502 via the signal via 504c on the right end side of FIG. The wiring 502d is communicated with other circuits using the signal output unit.
　これに対して、信号経路Ｌ（２）は、ビルドアップ層５０２の一層目の左から１番目のストリップ配線５０２ａを信号入力部とし、二層目乃至四層目の各ストリップ配線５０２ｅ，５０２ｇ，５０２ｉを予め連結装備された信号ビア５０４ａ，５０４ｄ，５０４ｅ，５０４ｆを介して順次連通され、続いて前述したコア層５０１の中心導体（スルーホールビア）５０５を介して他方のビルドアップ層５０３へ連通されるよう構成されている。符号５０１ｐと５０１ｓは、各ビルドアップ層５０２，５０３と中心導体(スルーホールビア)５０５の各端部とを、図１０の左上から同図の右下に向けて連通する連通層を示す。 On the other hand, the signal path L (2) uses the first strip wiring 502a from the left of the first layer of the buildup layer 502 as a signal input unit, and the strip wirings 502e, 502g, 502i is sequentially communicated through signal vias 504a, 504d, 504e, and 504f that are preliminarily connected and connected to the other buildup layer 503 via the central conductor (through-hole via) 505 of the core layer 501 described above. It is configured to be. Reference numerals 501p and 501s denote communication layers that connect the build- up layers 502 and 503 and the end portions of the central conductor (through-hole via) 505 from the upper left in FIG. 10 toward the lower right in FIG.
　信号をプリント配線板の表面から裏面へ通すことは、これによってプリント配線板の両面にLSI等の部品を搭載し実装密度を上げることができるため、高密度実装の観点から強く要求されていることである。 Passing signals from the front side to the back side of the printed wiring board is highly demanded from the viewpoint of high-density mounting because it can increase the mounting density by mounting parts such as LSI on both sides of the printed wiring board. It is.
　ここで、前述他方のビルドアップ層５０３の四層構造は、図１０の上層（コア層５０１側）を一層目とし、この一層目が、長さの長いストリップ配線５０３ａと長さの短いストリップ配線５０３ｂとにより構成されている。
又、ビルドアップ層５０３の他の四層構造は、この一層目の場合と同様に、それぞれ、長さの長いストリップ配線５０３ｃ，５０３ｅ，５０３ｇと、長さの短いストリップ配線５０３ｄ，５０３ｆ，５０３ｈとにより構成されている。 Here, in the four-layer structure of the other buildup layer 503, the upper layer (core layer 501 side) in FIG. 10 is the first layer, and this first layer is a strip wiring 503a having a long length and a strip wiring having a short length. 503b.
Further, the other four-layer structure of the build-up layer 503 includes strip wires 503c, 503e, and 503g having a long length and strip wires 503d, 503f, and 503h having a short length, as in the case of the first layer. It is comprised by.
　これにより、他方のビルドアップ層５０３の図１０における右下部分に配置された長さの短いストリップ配線５０３ｂ，５０３ｄ，５０３ｆ，５０３ｈは、予め相互間に介装された信号ビア５０４ｇ，５０４ｈ，５０４ｉ，５０４ｊを介して順次連通され、このストリップ配線５０３ｈを信号出力部として他の回路へ連通されるようになっている。 As a result, the short- length strip wirings 503b, 503d, 503f, and 503h disposed in the lower right portion of FIG. , 504j, and the strip wiring 503h is used as a signal output unit to communicate with other circuits.
　この図１０の多層プリント配線板における信号伝達特性は、信号経路Ｌ（１）の特性に比較して、信号経路Ｌ（２）の方の特性がかなり悪いことが知られている。これは、中心導体（スルーホールビア）５０５の信号伝送特性が悪いためである。中心導体５０５の上端部とその直上のストリップ配線５０２ｊと、中心導体５０５の下端部とその直下のストリップ配線５０３ａとは、近距離で対面している。その為、中心導体５０５と上記ストリップ配線５０２ｊ，５０３ａとがカップリングし、信号が減衰するためである。そのため、この中心導体５０５の信号伝送特性を改善することが強く期待されている。 It is known that the signal transmission characteristic in the multilayer printed wiring board of FIG. 10 is considerably worse in the signal path L (2) than in the signal path L (1). This is because the signal transmission characteristics of the center conductor (through-hole via) 505 are poor. The upper end portion of the center conductor 505 and the strip wiring 502j immediately above it, and the lower end portion of the center conductor 505 and the strip wiring 503a directly below it face each other at a short distance. For this reason, the central conductor 505 and the strip wirings 502j and 503a are coupled to attenuate the signal. Therefore, it is strongly expected to improve the signal transmission characteristics of the central conductor 505.
　中心導体（スルーホールビア）５０５の信号伝送特性を改善するために、特許文献１では、図１０におけるような中心導体（スルーホールビア）５０５の上部と下部に存在するストリップ配線５０２ｊと５０３ａに開口部を設置して対処している。特許文献１の内容を図１１に示して説明する。 In order to improve the signal transmission characteristics of the center conductor (through-hole via) 505, in Patent Document 1, openings are formed in strip wirings 502j and 503a existing above and below the center conductor (through-hole via) 505 as shown in FIG. The department is set up to deal with it. The contents of Patent Document 1 will be described with reference to FIG.
　図１１に示す多層プリント配線板は、以下の７層により形成されている。上からそれぞれ、導体層６０６ａ、電源ベタ層６０１ａ、信号配線６０２ａ、電源ベタ層６０１ｃ、信号配線６０２ｂ、電源ベタ層６０１ｂ、導体層６０６ｂである。、これら導体の間には、絶縁体層６０７が存在し、各導体間の絶縁を保っている。図１１の中心部には、スルーホール６０４が設けられており、そのスルーホール６０４には信号配線６０２ａと信号配線６０２ｂが結線されている。信号は、信号配線６０２ａの左端からスルーホール６０４を通り、信号配線６０２ｂ右端へと伝達される。スルーホール６０４の両端には、スルーホール６０４を形成するときに形成されるスルーホールパッド６０３ａ，６０３ｂが存在する。 The multilayer printed wiring board shown in FIG. 11 is formed of the following seven layers. From the top, a conductor layer 606a, a power supply solid layer 601a, a signal wiring 602a, a power supply solid layer 601c, a signal wiring 602b, a power supply solid layer 601b, and a conductor layer 606b, respectively. Between these conductors, an insulator layer 607 is present to maintain insulation between the conductors. A through hole 604 is provided in the center of FIG. 11, and a signal wiring 602a and a signal wiring 602b are connected to the through hole 604. The signal is transmitted from the left end of the signal wiring 602a through the through hole 604 to the right end of the signal wiring 602b. At both ends of the through hole 604, there are through hole pads 603a and 603b formed when the through hole 604 is formed.
　図１１のスルーホール６０４の上方部と下方部には、それぞれ，開口部６０５ａ，６０５ｂを持つ電源ベタ層６０１ａ，６０１ｂ（プレーン）が存在する。電源ベタ層６０１ａ，６０１ｂ（プレーン）に開口部６０５ａ，６０５ｂが存在すると、スルーホールパッド６０３ａ，６０３ｂと電源ベタ層６０１ａ，６０１ｂとは、それぞれ電磁気的なカップリングが少なくなる。そのため信号の電力損失が低減され、信号伝達特性の向上が図られる。 11 are power supply solid layers 601a and 601b (planes) having openings 605a and 605b, respectively, above and below the through hole 604 in FIG. When the openings 605a and 605b exist in the power supply solid layers 601a and 601b (planes), the through- hole pads 603a and 603b and the power supply solid layers 601a and 601b have less electromagnetic coupling, respectively. As a result, signal power loss is reduced, and signal transmission characteristics are improved.
　特許文献２では、同軸構造の信号線を実現し、外部からの影響を少なくし、信号伝達特性の向上を図っている。図１２には、その構造を示して説明する。
図１２の多層プリント配線板の層構造は、４層の配線により形成されている。最上層には配線パターン７０３ａが、次の層にはベタ層７０１ａ及び７０１ｃが、３番目の層にはベタ層７０１ｂ及び７０１ｄが、最下層には配線パターン７０３ｂがそれぞれ設置されている。図１２の中央には同軸構造のスルーホール７０４がこの多層プリント配線板の中央を貫通している。 In Patent Document 2, a coaxial signal line is realized, the influence from the outside is reduced, and signal transmission characteristics are improved. FIG. 12 shows and explains the structure.
The layer structure of the multilayer printed wiring board of FIG. 12 is formed by four layers of wiring. The uppermost layer is provided with a wiring pattern 703a, the next layer is provided with solid layers 701a and 701c, the third layer is provided with solid layers 701b and 701d, and the lowermost layer is provided with a wiring pattern 703b. A through hole 704 having a coaxial structure passes through the center of the multilayer printed wiring board in the center of FIG.
　この同軸構造のスルーホール７０４は、第１の銅めっき部７０５と、前記銅めっき武７０５の周囲を囲んでいる第２の銅めっき部７０６と、前記銅めっき部７０５と７０６との間を絶縁する絶縁体部７０７とにより構成されている。第２の銅めっき部７０６は、ベタ層７０１ａ～７０１ｄに接続され、接地されている。それぞれのベタ層７０１ａ～７０１ｄとそれぞれの配線パターン７０３ａ，７０３ｂとの相互間は、それぞれ絶縁層７０２ａ～７０２ｃにより絶縁されている。信号は、図１２上部の配線パターン７０３ａの右端から第１の銅メッキ部７０５を通過し、同図下部の配線パターン７０３ｂの左端へと伝達される。同軸構造のため、外部からの影響が少ないので、信号伝達特性が向上する。 The coaxial through hole 704 insulates the first copper plating portion 705, the second copper plating portion 706 surrounding the copper plating arm 705, and the copper plating portions 705 and 706. And an insulator portion 707. The second copper plating portion 706 is connected to the solid layers 701a to 701d and grounded. The solid layers 701a to 701d and the wiring patterns 703a and 703b are insulated from each other by insulating layers 702a to 702c, respectively. The signal passes through the first copper plating portion 705 from the right end of the wiring pattern 703a in the upper part of FIG. 12, and is transmitted to the left end of the wiring pattern 703b in the lower part of FIG. Because of the coaxial structure, there is little influence from the outside, so that the signal transmission characteristics are improved.
　特許文献３では、特許文献２の場合と同様に、同軸構造の信号線を実現し、外部からの影響を少なくし、信号伝達特性の向上を図っている。図１３には、その構造を示して説明する。
　図１３の多層プリント配線板は、４層の配線により形成されている。最上層には配線パターン８０３ａと８０３ｂが、次の層にはグランド層８０１ａが、３番目の層にはグランド層８０１ｂが、最下層には配線パターン８０３ｃと配線パターン８０３ｄが、それぞれ設置されている。第１のスルーホール部８０４と第２のスルーホール部８０５ａ，８０５ｂは、図１３の中央部を貫いている。第２のスルーホール部８０５ａ，８０５ｂは、絶縁体部８０７および第１のスルーホール部８０４により周囲を囲まれている。 In Patent Document 3, as in Patent Document 2, a coaxial signal line is realized, the influence from the outside is reduced, and signal transmission characteristics are improved. FIG. 13 shows and describes the structure.
The multilayer printed wiring board of FIG. 13 is formed of four layers of wiring. Wiring patterns 803a and 803b are installed in the uppermost layer, a ground layer 801a is installed in the next layer, a ground layer 801b is installed in the third layer, and a wiring pattern 803c and a wiring pattern 803d are installed in the lowermost layer. . The first through-hole portion 804 and the second through-hole portions 805a and 805b penetrate the central portion of FIG. The second through-hole portions 805a and 805b are surrounded by the insulator portion 807 and the first through-hole portion 804.
　第１のスルーホール部８０４及び第２のスルーホール部８０５ａ，８０５ｂは、それぞれめっき部８０６a，８０６ｂにより構成されている。第１のスルーホール部８０４は、グランド層８０１ａ，８０１ｂに接続され、めっき部８０６ｃにより構成されている。配線パターン８０３ａ～８０３ｄと電源あるいはグランド層８０１ａ，８０１ｂとはそれぞれ絶縁体層８０２ａ～８０２ｃにより絶縁されている。信号は、図上部の配線パターン８０３ａ，８０３ｂから，第２のスルーホール８０５ａ，８０５ｂを通り、図下部の配線パターン８０３ｃ，８０３ｄへと伝達される。同軸構造のため、外部からの影響が少ないので、信号伝達特性が向上する。 The first through-hole portion 804 and the second through-hole portions 805a and 805b are configured by plating portions 806a and 806b, respectively. The first through-hole portion 804 is connected to the ground layers 801a and 801b and includes a plating portion 806c. The wiring patterns 803a to 803d and the power supply or ground layers 801a and 801b are insulated from each other by insulator layers 802a to 802c. The signal is transmitted from the wiring patterns 803a and 803b in the upper part of the drawing to the wiring patterns 803c and 803d in the lower part of the drawing through the second through holes 805a and 805b. Because of the coaxial structure, there is little influence from the outside, so that the signal transmission characteristics are improved.
　特許文献４では、特許文献２、３と同様に、同軸構造の信号線を実現し、外部からの影響を少なくし、信号伝達特性の向上を図っている。特許文献５では、スルーホール導体と電源パターン及びグランドパターンと接続されている構造が記載されている。特許文献６から１１においても、同軸構造のスルーホールの構造及び形成方法を提案している。 In Patent Document 4, as in Patent Documents 2 and 3, a coaxial signal line is realized to reduce external influences and improve signal transmission characteristics. Patent Document 5 describes a structure in which a through-hole conductor is connected to a power supply pattern and a ground pattern. Patent Documents 6 to 11 also propose a through hole structure and a forming method of a coaxial structure.
特開２００５－１９４８３号公報JP 2005-19483 A 特開平６－３７４１６号公報JP-A-6-37416 特開２００２－３５３５８８号公報JP 2002-353588 A 特開２００３－１３３８０１号公報JP 2003-133801 A 特開２００７－３１８０８９号公報JP 2007-318089 A 特開２００３－６０３５１号公報Japanese Patent Laid-Open No. 2003-60351 特開２００４－３５６１６０号公報JP 2004-356160 A 特開２００１－１３５８９９号公報JP 2001-135899 A 特開２００１－１６８５３０号公報JP 2001-168530 A 特開２００２－２３２１４３号公報JP 2002-232143 A 特開２００５－１２１４５号公報Japanese Patent Laying-Open No. 2005-12145
　前述のような10GHz以上の信号伝送特性は、多層プリント基板内の垂直方向の信号伝送線路（スルーホールビア）においては、ストリップ配線やマイクロストリップ配線に比べて悪いという課題がある。それは、スルーホールビアの上部及び下部の電源プレーンやグランドプレーンがカップリングし、信号が減衰するためである。このような問題を改善するために、特許文献１では、上述した様に、スルーホールビアの上部及び下部の電源プレーンやグランドプレーンに開口部を設けている。 The signal transmission characteristics of 10 GHz or more as described above have a problem that the vertical signal transmission line (through-hole via) in the multilayer printed board is worse than the strip wiring or the microstrip wiring. This is because the power plane and ground plane above and below the through-hole via are coupled and the signal is attenuated. In order to improve such a problem, in Patent Document 1, as described above, openings are provided in the power plane and the ground plane above and below the through-hole via.
　しかしながら、特許文献１に開示された技術的手法は、高密度で多数の高速配線がスルーホールビアを経由する場合、プレーンに多くの開口部が必要となるという課題があった。電源プレーンやグランドプレーンに多くの開口部がある場合には、そのプレーンの抵抗の上昇を招くことになる。又、近傍に多くの電流を流すLSIが存在すると、電圧降下によって、LSIの動作が不安定になったり、最悪の場合には、動作しなくなるという不都合が生じる。他の特許文献２から１１についても、特許文献１における上記課題については何ら解決していない。 However, the technical method disclosed in Patent Document 1 has a problem that a large number of openings are required in the plane when a large number of high-speed wirings pass through through-hole vias. If there are many openings in the power plane and ground plane, the resistance of the plane will increase. In addition, if there is an LSI that passes a large amount of current in the vicinity, the operation of the LSI becomes unstable due to a voltage drop, and in the worst case, it does not operate. Regarding other Patent Documents 2 to 11, the above-mentioned problem in Patent Document 1 is not solved at all.
　本発明は、高密度の多層プリント配線板上でプレーンの抵抗を上昇させることなく配線内での信号の高速伝送化と高密度化とを両立させることを可能とした多層プリント配線板及びその構造を提供することを、その目的とする。 The present invention relates to a multilayer printed wiring board capable of achieving both high-speed signal transmission and high density in the wiring without increasing the resistance of the plane on the high-density multilayer printed wiring board and its structure. The purpose is to provide
　上記目的を達成するため、本発明にかかる多層プリント配線板は、コア層の少なくとも一つの面に堆積されたビルドアップ層と、前記コア層を貫くと共に当該コア層と連結された円筒状の外部導体と、コア層内に前記外部導体と同軸構造をなすように形成された中心導体と、この中心導体と前記外部導体との間に充填された絶縁体とを有し、前記ビルドアップ層に設けられた配線が前記中心導体の端部に対抗して配置された多層プリント配線板において、前記中心導体端部に信号ビアを設け、その信号ビアの直径が前記中心導体端部の直径より小さくしたことを特徴とする。 In order to achieve the above object, a multilayer printed wiring board according to the present invention includes a build-up layer deposited on at least one surface of a core layer, and a cylindrical external body penetrating the core layer and connected to the core layer. A conductor, a central conductor formed in the core layer so as to form a coaxial structure with the outer conductor, and an insulator filled between the central conductor and the outer conductor; In the multilayer printed wiring board in which the provided wiring is arranged to oppose the end portion of the central conductor, a signal via is provided at the central conductor end portion, and the diameter of the signal via is smaller than the diameter of the central conductor end portion. It is characterized by that.
　本発明は、上述したように、小さい直径の信号ビアを中心導体の上方部および下方部に設置したので、直径の大きい中心導体のみを設置した場合に比べて上方部及び下方部のプレーンとの電気的なカップリング量を小さくすることができ、これにより信号伝達経路上のインピーダンスを低下させることができるので、プレーンに開口部を設けることなくプリント配線板の表面から裏面に高速の伝送信号を通すことができる。 In the present invention, as described above, since the small-diameter signal vias are installed in the upper part and the lower part of the central conductor, the upper and lower planes are compared with the case where only the large-diameter central conductor is installed. The amount of electrical coupling can be reduced, thereby reducing the impedance on the signal transmission path, so high-speed transmission signals can be sent from the front surface to the back surface of the printed wiring board without providing openings in the plane. Can pass through.
本発明の多層プリント配線板の第１の実施形態を示す部分断面図である。It is a fragmentary sectional view showing a 1st embodiment of a multilayer printed wiring board of the present invention. 図１におけるＩ-Ｉ線に沿った部分断面図である。It is a fragmentary sectional view along the II line in FIG. 図１に開示した第１の実施形態（多層プリント配線板）の信号伝達特性について、そのシミュレーションによる比較データの収集に使用した試料（関連技術）を示す部分断面図である。It is a fragmentary sectional view which shows the sample (related technique) used for the collection of the comparison data by the simulation about the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG. 図１に開示した第１の実施形態（多層プリント配線板）の信号伝達特性について、そのシミュレーションによる比較データの収集に使用した試料（特許文献１）を示す部分断面図である。It is a fragmentary sectional view which shows the sample (patent document 1) used for the collection of the comparison data by the simulation about the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG. 図１に開示した第１の実施形態（多層プリント配線板）の信号伝達特性のシミュレーション結果であるデータ挿入損失（Ａ）とリターンロス（Ｂ）とを示す線図である。It is a diagram which shows the data insertion loss (A) and return loss (B) which are the simulation results of the signal transmission characteristic of 1st Embodiment (multilayer printed wiring board) disclosed in FIG. 本発明にかかる多層プリント配線板の第２の実施形態を示す部分断面図である。It is a fragmentary sectional view which shows 2nd Embodiment of the multilayer printed wiring board concerning this invention. 本発明にかかる多層プリント配線板の第３の実施形態を示す部分断面図である。It is a fragmentary sectional view which shows 3rd Embodiment of the multilayer printed wiring board concerning this invention. 図７におけるＩ-Ｉ線に沿った部分断面図である。It is a fragmentary sectional view along the II line in FIG. 本発明にかかる多層プリント配線板の第４の実施形態を示す部分断面図である。It is a fragmentary sectional view which shows 4th Embodiment of the multilayer printed wiring board concerning this invention. 関連技術における多層プリント配線板の信号伝達経路を示す部分断面図である。It is a fragmentary sectional view which shows the signal transmission path | route of the multilayer printed wiring board in related technology. 関連技術（特許文献１）のスルーホール構造を示す部分断面である。It is a partial cross section which shows the through-hole structure of related technology (patent document 1). 関連技術（特許文献２）の同軸ビア構造を示す部分断面図である。It is a fragmentary sectional view which shows the coaxial via structure of related technology (patent document 2). 関連技術（特許文献３）の同軸ビア構造を示す部分斜視図である。It is a fragmentary perspective view which shows the coaxial via structure of related technology (patent document 3).
[第１の実施形態]
　以下、本発明にかかる多層プリント配線基板の第１実施形態を図１乃至図５に基づいて説明する。
　この第１実施形態において、多層プリント配線基板は、コア層２０の少なくとも一つの面に堆積されたビルドアップ層２１ａと、前記コア層２０の中央部を貫くと共に当該コア層２０と連結された円筒状の外部導体１５と、コア層２０内に前記外部導体１５と同軸構造をなすように形成された中心導体１１と、この中心導体１１と前記外部導体１５との間に充填された絶縁体１８とを有している。前記ビルドアップ層２１ａに設けられた配線は、前記中心導体１１の端部に対向して配置されている。そして、前記中心導体１１の端部には、信号ビア１２ａを設け、その信号ビア１２ａの直径が前記中心導体１１の端部の直径より小さくしたことを特徴としている。以下、これを更に具体的に説明する。 [First embodiment]
Hereinafter, a first embodiment of a multilayer printed wiring board according to the present invention will be described with reference to FIGS.
In the first embodiment, the multilayer printed wiring board includes a buildup layer 21 a deposited on at least one surface of the core layer 20, and a cylinder that penetrates the central portion of the core layer 20 and is connected to the core layer 20. Outer conductor 15, a central conductor 11 formed in the core layer 20 so as to form a coaxial structure with the outer conductor 15, and an insulator 18 filled between the central conductor 11 and the outer conductor 15. And have. The wiring provided in the build-up layer 21 a is disposed so as to face the end portion of the central conductor 11. A signal via 12 a is provided at the end of the central conductor 11, and the diameter of the signal via 12 a is smaller than the diameter of the end of the central conductor 11. This will be described more specifically below.
（全体の構成）
　図１は第１実施形態における多層プリント配線板を示す部分断面図である。この図１において、多層プリント配線板は、コア層２０とこのコア層２０の上面側と下面側にそれぞれ堆積されたビルドアップ層２１ａ，２１ｂとにより構成されている。中心導体１１は、前記コア層２０の中心部を図示の如く貫いている。この中心導体１１は、周囲がコア層２０に連結された円筒状の外部導体１５の内部にあって当該外部導体１５と同軸構造をなすように構成されている。前記中心導体１１の両端部には、信号ビア１２ａ，１２ｂが設けられ、その信号ビア１２ａ，１２ｂの各直径は前述したように中心導体１１の端部の直径より小さく設定されている。 (Overall configuration)
FIG. 1 is a partial cross-sectional view showing a multilayer printed wiring board according to the first embodiment. In FIG. 1, the multilayer printed wiring board includes a core layer 20 and buildup layers 21a and 21b deposited on the upper surface side and the lower surface side of the core layer 20, respectively. The center conductor 11 penetrates through the center of the core layer 20 as shown in the figure. The center conductor 11 is configured to have a coaxial structure with the outer conductor 15 inside the cylindrical outer conductor 15 connected to the core layer 20. Signal vias 12a and 12b are provided at both ends of the central conductor 11, and the diameters of the signal vias 12a and 12b are set smaller than the diameter of the end of the central conductor 11, as described above.
　上述したように、図１のコア層２０には、中心軸上に中心導体１１が設置され、その周囲を前述したように外部導体１５が囲んでいる。中心導体１１の内部は、めっきによりすべて導体材で充填されている。又、外部導体１５には、８層のグランド層５０１ａが接続されている。それぞれの層間には誘電体５１１が充填されている。 As described above, the core conductor 20 in FIG. 1 is provided with the central conductor 11 on the central axis, and the outer conductor 15 surrounds the periphery thereof as described above. The inside of the center conductor 11 is filled with a conductor material by plating. The outer conductor 15 is connected to eight ground layers 501a. A dielectric 511 is filled between the respective layers.
　このコア層２０の図１における上面側および下面側には、それぞれ一方と他方のビルドアップ層２１ａと２１ｂが設けられている。この内、上面側のビルドアップ層２１ａは、ストリップライン１３ａおよびその上部に設けられたプレーン１４ａと、それらを絶縁する誘電体１９ａとにより構成されている。又、下面側のビルドアップ層２１ｂには、上面側のビルドアップ層２１ａと同様にストリップライン１３ｂおよびその下部に設けられたプレーン１４ｂと、それらを絶縁する誘電体１９ｂとにより構成されている。 1 and the other buildup layers 21a and 21b are provided on the upper surface side and the lower surface side in FIG. 1 of the core layer 20, respectively. Among these, the buildup layer 21a on the upper surface side is composed of the strip line 13a and the plane 14a provided on the strip line 13a, and a dielectric 19a that insulates them. Similarly to the build-up layer 21a on the lower surface side, the build-up layer 21b on the lower surface side is constituted by a strip line 13b and a plane 14b provided below the strip line 13b and a dielectric 19b that insulates them.
　中心導体１１の図１における上端部と下端部には、中心導体１１の直径より小さな直径の信号ビア１２ａ，１２ｂが接続している。この信号ビア１２ａ，１２ｂは、それぞれ前述したストリップライン１３ａ，１３ｂによって引き出されている。図２は、図１のＩ-Ｉ線に沿った部分断面図である。この図２では、中心導体１１と、それを取り囲むように形成された円柱状の外部導体１５と、中心導体１１に接続された信号ビア１２ａと、その信号ビア１２ａに接続されている前述したストリップライン１３ａとの相互関係を示してある。 Signal vias 12a and 12b having a diameter smaller than the diameter of the central conductor 11 are connected to the upper end and the lower end of the central conductor 11 in FIG. The signal vias 12a and 12b are drawn out by the above-described strip lines 13a and 13b, respectively. FIG. 2 is a partial cross-sectional view taken along the line II of FIG. In FIG. 2, the center conductor 11, the cylindrical outer conductor 15 formed so as to surround the center conductor 11, the signal via 12a connected to the center conductor 11, and the above-described strip connected to the signal via 12a. The interrelationship with the line 13a is shown.
　図１において、中央導体１１の両端部が中央部分より外径が大きくなっているのは、作製工程により出現するものである。この中心導体１１を作製に際しては、先ず誘電体１８に円柱状の孔を開口する。その後、コア層の表面と裏面および円柱状の孔など外部と内部全てにめっきを行う。そして、円柱状の孔の内部とコア層の上面と下面の配線以外の部分のめっきをエッチングで取り去る。その時、コア層の円柱内部のめっきをエッチングしないように中心導体１１の両端部の外径を大きくする必要がある。そのため、中央導体１１の両端部が中央部分より外径が大きくなり、これにより、中心導体１１は安定した状態が維持されている。その他の構成は、前述した図１０の関連技術と同一となっている。 In FIG. 1, the outer diameters of both end portions of the central conductor 11 are larger than the central portion, which appears due to the manufacturing process. In producing the central conductor 11, first, a cylindrical hole is opened in the dielectric 18. Thereafter, plating is performed on the entire outer and inner surfaces such as the front and back surfaces of the core layer and the cylindrical holes. Then, plating of portions other than the wiring inside the cylindrical hole and the upper and lower surfaces of the core layer is removed by etching. At that time, it is necessary to increase the outer diameter of both ends of the center conductor 11 so as not to etch the plating inside the column of the core layer. Therefore, both ends of the central conductor 11 have an outer diameter larger than that of the central portion, whereby the central conductor 11 is maintained in a stable state. Other configurations are the same as those of the related technique shown in FIG.
（動作）
　次に、上記第１実施形態の動作について説明する。
　まず、伝送信号は、図１の上層のストリップ配線１３ａの左端から、信号ビア１２ａ、中心導体１１、信号ビア１２ｂを通り、下層のストリップ配線１３ｂの右端までを通過する。
　ここで、本第１実施形態にかかる多層プリント配線板の信号伝達特性が優れていることを示すために、公知の２種類の構造のものについて、その挿入損失とリターンロスの信号伝達特性の比較シミュレーションを行った。 (Operation)
Next, the operation of the first embodiment will be described.
First, a transmission signal passes from the left end of the upper layer strip wiring 13a in FIG. 1 to the right end of the lower layer strip wiring 13b through the signal via 12a, the central conductor 11, and the signal via 12b.
Here, in order to show that the signal transmission characteristic of the multilayer printed wiring board according to the first embodiment is excellent, a comparison of the signal transmission characteristics of the insertion loss and the return loss of two types of known structures. A simulation was performed.
　このシミュレーションでは、本第１実施形態に係る図１の多層プリント配線板のものを第１の構造とした。又、第２の構造は図３に示す関連技術における構造のものとし、第３の構造は図４に示す特許文献１に開示されているのものとした。この内、第３の構造では、スルーホールビアのパッドの上部及び下部のプレーンに開口部が存在する構造を示す。以下、プレーンに開口部が存在しない本発明と、基本構造のものと、プレーンに開口部が存在する場合との効果がどの様に異なるかを比較する。 In this simulation, the multilayer printed wiring board of FIG. 1 according to the first embodiment is used as the first structure. Further, the second structure is the structure in the related art shown in FIG. 3, and the third structure is the one disclosed in Patent Document 1 shown in FIG. Among these, the third structure shows a structure in which openings exist in the upper and lower planes of the through-hole via pads. Hereinafter, it will be compared how the effect of the present invention in which the opening does not exist in the plane is different from that of the basic structure and the case in which the opening exists in the plane.
　ここで、図３の基本的な構造（第２の構造のもの）は図１と同じである。図１と異なる点は以下である。
　（１）図１における信号ビア１２ａ，１２ｂが存在しない。ストリップ配線５０１ｐと５０１ｓとは、直接中央導体５０５に繋がっている。
　（２）外部導体１５は存在せず、グランド層５０１ａが直接中央導体５０５を取り囲んでいる。
　（３）中心導体５０５内は中空であり、誘電体５１２が挿入されている。
　中空の方が完全充填した本発明の中央導体１１より、上部下部のプレーン５０２ｊ，５０３ａとのカップリング量が少なくなるため、信号透過特性は良くなることが想定される。 Here, the basic structure of FIG. 3 (the second structure) is the same as FIG. Differences from FIG. 1 are as follows.
(1) The signal vias 12a and 12b in FIG. 1 do not exist. The strip wirings 501p and 501s are directly connected to the central conductor 505.
(2) The outer conductor 15 does not exist, and the ground layer 501a directly surrounds the central conductor 505.
(3) The center conductor 505 is hollow and a dielectric 512 is inserted.
Since the amount of coupling with the upper and lower planes 502j and 503a is smaller than that of the central conductor 11 of the present invention in which the hollow is completely filled, it is assumed that the signal transmission characteristics are improved.
　又、図４の基本的な構造（第３の構造のもの）は図３と同じである。図３と異なる点は以下である。
　（１）グランド層５０１ａの開口部直径と同じ直径を有する開口部２２ａ，２２ｂがプレーン５０２ｊ，５０３ａに存在する。 4 is the same as that in FIG. 3 (the third structure). Differences from FIG. 3 are as follows.
(1) Openings 22a and 22b having the same diameter as that of the ground layer 501a are present in the planes 502j and 503a.
　図１の寸法値とそのシミュレーション結果を以下に示す。各部の寸法は、dpad1=0.3mm、dcoax=0.7mm、drod=0.15mm、dpad2=0.078mm、drod2=0.05mm
とした。また、多層プリント配線板の導体と誘電体の厚さは、ビルドアップ層２１ａ，２１ｂ部分が、tcond-b=18mm、tde-b=35mm であり、コア層２０部分が、tcond-c=35mm、tde-c=100mmとした。 The dimension values of FIG. 1 and the simulation results are shown below. The dimensions of each part are d pad1 = 0.3mm, d coax = 0.7mm, d rod = 0.15mm , d pad2 = 0.078mm, d rod2 = 0.05mm
It was. The thicknesses of the conductors and dielectrics of the multilayer printed wiring board are t cond-b = 18 mm and t de-b = 35 mm in the build-up layers 21a and 21b, and the core layer 20 portion is t cond- c = 35 mm and t de-c = 100 mm.
　図１の構造でのシミュレーションでは、導電体は完全導体とし、誘電体の誘電率は3.35とした。上層のストリップ配線１３ａの左端から、下層のストリップ配線１３ｂの右端までの高周波特性をシミュレーションにより確認した。図５のカーブ５１とカーブ６１は、それぞれシ図１の構造（第１の構造）でのミュレーションによる挿入損失と反射によるロス（リターンロス）の計算結果である。この結果によると、本発明の垂直信号伝送線路を用いた場合、20GHzにおいて、挿入損失が －0.5dB、リターンロスが －17dBである。 In the simulation with the structure of FIG. 1, the conductor is a perfect conductor, and the dielectric constant of the dielectric is 3.35. The high frequency characteristics from the left end of the upper layer strip wiring 13a to the right end of the lower layer strip wiring 13b were confirmed by simulation. A curve 51 and a curve 61 in FIG. 5 are calculation results of insertion loss due to simulation and loss due to reflection (return loss) in the structure (first structure) in FIG. According to this result, when the vertical signal transmission line of the present invention is used, the insertion loss is −0.5 dB and the return loss is −17 dB at 20 GHz.
　図３の寸法値とそのシミュレーション結果について説明する。図３のシミュレーションも上層のストリップ配線５０１ｐの左端から、下層のストリップ配線５０１ｓの右端までの高周波特性を調べた。中心導体５０５の各部の寸法は、dpad=0.5mm、dcle=0.7mm、drod=0.25mmとした。また、プリント配線板の導体と誘電体の厚さはそれぞれ、tcond-b=18mm、tde-b=35mm と、tcond-c=35mm、tde-c=100mmとした。 The dimension values in FIG. 3 and the simulation results will be described. In the simulation of FIG. 3 as well, the high frequency characteristics from the left end of the upper layer strip wiring 501p to the right end of the lower layer strip wiring 501s were examined. The dimensions of each part of the center conductor 505 were d pad = 0.5 mm, d cle = 0.7 mm, and d rod = 0.25 mm. The thicknesses of the conductor and dielectric of the printed wiring board were t cond-b = 18 mm, t de-b = 35 mm, t cond-c = 35 mm, and t de-c = 100 mm, respectively.
　このシミュレーションでも、導電体は完全導体とし、誘電体の誘電率は3.35とした。図５のカーブ５３とカーブ６３は、それぞれ図３の構造（第２の構造）でのシミュレーションによる挿入損失と反射によるロス（リターンロス）の計算結果である。この結果によると、通常のスルーホール構造の場合、20GHzにおいて、－９ｄBの挿入損失が、－５ｄBのリターンロスがある。 In this simulation as well, the conductor was a perfect conductor, and the dielectric constant of the dielectric was 3.35. A curve 53 and a curve 63 in FIG. 5 are calculation results of insertion loss and loss due to reflection (return loss) in the structure (second structure) in FIG. 3, respectively. According to this result, in the case of a normal through-hole structure, there is an insertion loss of −9 dB and a return loss of −5 dB at 20 GHz.
　図４の寸法値とそのシミュレーション結果について説明する。寸法値は、プレーン５０２ｊ，５０３ａに開口部２２ａ，２２ｂを設けてある以外は、図３の構造と全く同じ寸法とした。図５のカーブ５２とカーブ６２は、図４の構造（第３の構造）でのそれぞれ挿入損失とリターンロスを示している。挿入損失は20GHzで－３．５dB、リターンロスは－１２dBであり、プレーン５０２ｊ，５０３ａに開口部が無い場合のスルーホールの特性に比べて改善がなされている。 The dimension values in FIG. 4 and the simulation results will be described. The dimension values were exactly the same as those in the structure of FIG. 3 except that the openings 22a and 22b were provided in the planes 502j and 503a. A curve 52 and a curve 62 in FIG. 5 indicate an insertion loss and a return loss, respectively, in the structure (third structure) in FIG. The insertion loss is −3.5 dB at 20 GHz and the return loss is −12 dB, which is an improvement over the characteristics of the through hole when there is no opening in the planes 502j and 503a.
　本第１実施形態の多層プリント配線板（第１の構造）である図１のシミュレーション結果（カーブ５１とカーブ６１）は、20GHzにおいて、挿入損失が －0.5dB、リターンロスが －17dBであり、上記の図４（特許文献１の方法、第３の構造体）の構造でのシミュレーション結果（カーブ５２とカーブ６２）よりもさらに改善が図られている。この場合、図３と図４の中心導体５０５は中空であり、中空の方が完全充填した本発明の中央導体１１より、上部と下部のプレーン５０２ｊ，５０３aとのカップリング量が少なくなる。その為信号透過特性は良くなるにも係らず、本発明の方が信号特性が良くなっている。 The simulation result (curve 51 and curve 61) of FIG. 1 which is the multilayer printed wiring board (first structure) of the first embodiment has an insertion loss of −0.5 dB and a return loss of −17 dB at 20 GHz. Further improvement is achieved compared to the simulation results (curve 52 and curve 62) in the structure of FIG. 4 (method of Patent Document 1, third structure). In this case, the central conductor 505 of FIGS. 3 and 4 is hollow, and the amount of coupling between the upper and lower planes 502j and 503a is smaller than that of the central conductor 11 of the present invention in which the hollow is completely filled. Therefore, although the signal transmission characteristics are improved, the signal characteristics of the present invention are improved.
（第１実施形態の効果）
　本第１実施形態は、以下の効果を備えている。図１のプレーン１４ａ，１４ｂに開口部が無い状態でも高周波特性の良好な垂直方向の信号伝送線路が形成できる。図１の中央導体１１の上部及び下部のプレーン１４ａ，１４ｂに開口部を設置する必要がなく、グランドのプレーン１４ａ，１４ｂの抵抗を上昇させない。その為、多層プリント配線板の上面から下面に高速の伝送信号を通すことが可能となる。本第１実施形態により、高速信号伝送と高密度実装の両立が実現できるという効果がある。 (Effect of 1st Embodiment)
The first embodiment has the following effects. A vertical signal transmission line with good high-frequency characteristics can be formed even when the planes 14a and 14b in FIG. 1 have no openings. It is not necessary to provide openings in the upper and lower planes 14a and 14b of the central conductor 11 in FIG. 1, and the resistance of the ground planes 14a and 14b is not increased. Therefore, a high-speed transmission signal can be passed from the upper surface to the lower surface of the multilayer printed wiring board. According to the first embodiment, there is an effect that both high-speed signal transmission and high-density mounting can be realized.
　さらに、図１の前記信号ビア１２ａ，１２ｂの直径が、前記中心導体１１より小さいため、ビルドアップ層２１ａ，２１ｂでの配線密度をさらに上げることができる。
また、外部導体と電源層、またはグランド層を接続することによって、さらに、電源層とグランド層の抵抗を下げる効果があるため、ＬＳＩへの電源供給を容易にすることが可能となる。 Furthermore, since the diameter of the signal vias 12a and 12b in FIG. 1 is smaller than the central conductor 11, the wiring density in the build-up layers 21a and 21b can be further increased.
Further, by connecting the external conductor and the power supply layer or the ground layer, there is an effect of further reducing the resistance between the power supply layer and the ground layer, so that power supply to the LSI can be facilitated.
　以上のように、本第１実施形態では、図１の中央導体１１の上部及び下部のプレーン１４ａ，１４ｂに開口部が無い状態でも、高周波特性の良好な垂直方向の信号伝送線路が形成できるという優れた効果を有する。 As described above, in the first embodiment, it is possible to form a vertical signal transmission line with good high-frequency characteristics even when the upper and lower planes 14a and 14b of the central conductor 11 in FIG. 1 have no openings. Has an excellent effect.
[第２の実施形態] 
　次に、本発明にかかる第２の実施の形態について、図６に基づいて説明する。図６は、本発明の多層プリント配線板の第２実施形態の構造を示している。 [Second Embodiment]
Next, a second embodiment according to the present invention will be described with reference to FIG. FIG. 6 shows the structure of the second embodiment of the multilayer printed wiring board of the present invention.
　第１実施形態（図１）との相違点は、下記である。図１でのビルドアップ層２１ａ，２１ｂのそれぞれの層に配置されている信号ビア１２ａと１２ｂが、図６では４層の積層型のスタックビア構造となっている。信号ビア１２ａの周囲には、別系統のストリップ配線３１ａ，３１ｂが配置され、信号ビア１２ｂの周囲には、別系統のストリップ配線３１ｃ，３１ｄが配置されている。 Differences from the first embodiment (FIG. 1) are as follows. The signal vias 12a and 12b arranged in the respective build-up layers 21a and 21b in FIG. 1 have a four-layer stacked via structure in FIG. Another system of strip wirings 31a and 31b is arranged around the signal via 12a, and another system of strip wirings 31c and 31d is arranged around the signal via 12b.
　信号ビア１２ａ，１２ｂが積層型のスタックビア構造となっているため、各層に設置されたビアとその層に設置されたストリップ配線とを接続することができる。そのため、任意の層から信号ビア１２ａ，１２ｂにアクセスが可能となる。その為、信号伝達特性を悪化させずにビルドアップ層の任意の層から信号を引き出しすることが出来るという効果を有する。
　その他の構成及び作用効果は前述の第１実施形態と同等となっている。 Since the signal vias 12a and 12b have a stacked stack via structure, the vias installed in each layer can be connected to the strip wiring installed in that layer. Therefore, the signal vias 12a and 12b can be accessed from any layer. Therefore, there is an effect that a signal can be extracted from an arbitrary layer of the buildup layer without deteriorating the signal transmission characteristics.
Other configurations and operational effects are the same as those of the first embodiment.
[第３の実施形態] 
　次に、本発明にかかる第３の実施の形態について、図７に基づいて説明する。図７は、本発明の多層プリント配線板の第３実施形態の構造を示している。
　図７は本発明の第３の実施形態の部分断面図を示している。第２の実施形態（図６）と異なっている点は、以下である。図７のビルドアップ層２１ａ，２１ｂのそれぞれの層に配置されている信号ビア１２ａ，１２ｂの周囲に、スタックビア構造となっているシールドビア３２ａ～３２ｄとそれぞれに接続しているシールド配線３３ａ～３３ｄが、設置されているという点である。図７の信号ビア１２ａの周囲には、シールドビア３２ａ，３２ｂとシールド配線３３ａ，３３ｂが、信号ビア１２ｂの周囲にはシールドビア３２ｃ，３２ｄとシールド配線３３ｃ，３３ｄが、設置されている。
　図８は、図７のII-II間から見た平面図を示している。８列のシールドビア３２が、信号ビア１２ａを取り囲むように配置されている。シールド配線３３は、シールドビア３２よりさらに信号ビア１２ａに近づいており、信号ビア１２ａの周囲を取り囲んでいる。 [Third embodiment]
Next, a third embodiment according to the present invention will be described with reference to FIG. FIG. 7 shows the structure of the third embodiment of the multilayer printed wiring board of the present invention.
FIG. 7 shows a partial sectional view of a third embodiment of the present invention. The differences from the second embodiment (FIG. 6) are as follows. The shield vias 33a to 33d connected to the shield vias 32a to 32d having a stack via structure around the signal vias 12a and 12b arranged in the respective buildup layers 21a and 21b of FIG. 33d is that it is installed. Shield vias 32a and 32b and shield wirings 33a and 33b are installed around the signal via 12a in FIG. 7, and shield vias 32c and 32d and shield wirings 33c and 33d are installed around the signal via 12b.
FIG. 8 shows a plan view seen from II-II in FIG. Eight rows of shield vias 32 are arranged so as to surround the signal vias 12a. The shield wiring 33 is closer to the signal via 12a than the shield via 32, and surrounds the signal via 12a.
　シールド配線３３の存在により、信号ビア１２ａ，１２ｂをシールド配線３３が周囲を取り囲むので、シールド配線３３が、外部及び内部からの電磁波を遮断することができる。そのため、信号ビア１２ａ，１２ｂからの漏れ損失を低減したり、外部からのノイズに影響され難いという効果を有する。
　その他の構成及び作用効果は前述の第１及び第２の実施形態と同等となっている。 Since the shield wiring 33 surrounds the signal vias 12a and 12b due to the presence of the shield wiring 33, the shield wiring 33 can block electromagnetic waves from the outside and the inside. Therefore, there is an effect that leakage loss from the signal vias 12a and 12b is reduced and that it is hardly affected by external noise.
Other configurations and operational effects are the same as those of the first and second embodiments described above.
[第４の実施形態] 
　次に、本発明にかかる第４の実施の形態について、図９に基づいて説明する。図９は、本発明の多層プリント配線板の第４実施形態の構造を示している。 [Fourth Embodiment]
Next, a fourth embodiment according to the present invention will be described with reference to FIG. FIG. 9 shows the structure of the fourth embodiment of the multilayer printed wiring board of the present invention.
　図９は、本発明の第４の実施形態の部分断面図を示している。図１と異なっている点は、第２の電源・グランド層４２ａ～４２ｄが存在している点である。外部導体１５は、第１の電源・グランド層４１ａ～４１ｃに接続され、第２の電源・グランド層４２ａ～４２ｄには接続されていない構造である。例えば、第１の電源・グランド層４１ａ～４１ｃをグランド電位に、第２の電源・グランド層４２ａ～４２ｄを電源電位に設定することができる（このタイプの構造をここではタイプ１と呼ぶ）。また逆に、第１の電源・グランド層４１ａ～４１ｃを電源電位に、第２の電源・グランド層４２ａ～４２ｄをグランド電位に設定することもできる（このタイプの構造をここではタイプ２と呼ぶ）。 FIG. 9 shows a partial cross-sectional view of the fourth embodiment of the present invention. The difference from FIG. 1 is that second power / ground layers 42a to 42d exist. The external conductor 15 is connected to the first power / ground layers 41a to 41c and is not connected to the second power / ground layers 42a to 42d. For example, the first power supply / ground layers 41a to 41c can be set to the ground potential, and the second power supply / ground layers 42a to 42d can be set to the power supply potential (this type of structure is referred to as type 1 herein). Conversely, the first power supply / ground layers 41a to 41c can be set to the power supply potential, and the second power supply / ground layers 42a to 42d can be set to the ground potential (this type of structure is referred to as type 2 herein). ).
　外部導体１５の電位がグランド電位でなくとも、変動せずに一定であれば、外部導体１５は本実施形態における垂直方向信号伝送線路に対して、電磁波の遮断効果を持つ。そのため、電位が変動せずに一定の電位を持つ外部導体１５は、この垂直方向信号伝送線路の高周波特性に影響を与えない。そのため、信号伝送特性を良好に保ったまま、同じ電位の電源層またはグランド層を外部導体を経由して接続し、抵抗を下げることができる。また、垂直方向信号伝送線路をN個有する多層プリント配線板において、約N/2個がタイプ１の構造であり、約N/2個がタイプ２の構造にすることもできる。 Even if the potential of the outer conductor 15 is not a ground potential, if the potential is constant without fluctuation, the outer conductor 15 has an electromagnetic wave blocking effect on the vertical signal transmission line in the present embodiment. Therefore, the outer conductor 15 having a constant potential without changing the potential does not affect the high frequency characteristics of the vertical signal transmission line. Therefore, it is possible to reduce the resistance by connecting the power supply layer or the ground layer having the same potential via the external conductor while keeping the signal transmission characteristics good. Further, in a multilayer printed wiring board having N vertical signal transmission lines, about N / 2 pieces can have a type 1 structure, and about N / 2 pieces can have a type 2 structure.
　このようにすることで、多数の外部導体１５によって電源層、グランド層の抵抗を下げることができ、各配線での電源電位とグランド電位の変動が少なくなるという、電位の安定化が図られる。このことで、大電流を流すLSIが搭載されても電圧降下が起こることなく、安定した電源供給が可能となる。
　その他の構成及び作用効果は前述の第１の実施形態と同等となっている。 In this way, the resistance of the power supply layer and the ground layer can be lowered by the large number of external conductors 15, and the potential can be stabilized such that the fluctuations of the power supply potential and the ground potential in each wiring are reduced. This enables stable power supply without causing a voltage drop even if an LSI that carries a large current is mounted.
Other configurations and operational effects are the same as those of the first embodiment.
　以上、実施形態（及び実施例）を参照して本願発明を説明したが、本願発明は上記実施形態（及び実施例）に限定されるものではない。本願発明の構成や詳細には、本願発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 As mentioned above, although this invention was demonstrated with reference to embodiment (and an Example), this invention is not limited to the said embodiment (and Example). Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
　この出願は２００９年８月１２日に出願された日本出願特願２００９－１８７２２７を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2009-187227 filed on August 12, 2009, the entire disclosure of which is incorporated herein.
　本発明は、高密度の多層プリント配線板上でプレーンの抵抗を上昇させることなく配線内での信号の高速伝送化と高密度化とを両立させることに貢献できるものである。 The present invention can contribute to both high-speed signal transmission and high density in the wiring without increasing the resistance of the plane on the high-density multilayer printed wiring board.
　１１　中心導体
　１２ａ，１２ｂ　信号ビア
　１３ａ，１３ｂ　ストリップ配線
　１４ａ，１４ｂ　プレーン
　１５　外部導体
　１８，１９ａ，１９ｂ　誘電体
　２０　コア層
　２１ａ，２１ｂ　ビルドアップ層
　２２ａ，２２ｂ　開口部
　３２，３２ａ，３２ｂ，３２ｃ，３２ｄ　シールドビア
　３３，３３ａ，３３ｂ，３３ｃ，３３ｄ　シールド配線
　４１ａ，４１ｂ，４１ｃ　第１の電源・グランド層
　４２ａ，４２ｂ，４２ｃ，４２ｄ　第２の電源・グランド層
　５０１ａ　グランド層
　５０１ｐ，５０１ｓ　ストリップ配線
　５０２ｊ，５０３ａ　プレーン
　５０５　中心導体
　５１１，５１２，５１３　誘電体 11 Central conductor 12a, 12b Signal via 13a, 13b Strip wiring 14a, 14b Plane 15 Outer conductor 18, 19a, 19b Dielectric 20 Core layer 21a, 21b Build- up layer 22a, 22b Opening 32, 32a, 32b, 32c, 32d Shield via 33, 33a, 33b, 33c, 33d Shield wiring 41a, 41b, 41c First power / ground layer 42a, 42b, 42c, 42d Second power / ground layer 501a Ground layer 501p, 501s Strip wiring 502j, 503a Plane 505 Center conductor 511, 512, 513 Dielectric

Claims (7)

  1. 　コア層の両面にそれぞれ堆積された一方と他方のビルドアップ層と、前記コア層を貫通し且つ当該コア層と連結された円筒状の外部導体と、前記コア層内に前記外部導体と同軸構造をなすように装備された中心導体と、この中心導体と前記外部導体との間に充填された絶縁体とを有し、前記ビルドアップ層に設けられた配線が前記中心導体の両端部に対向して配置された多層プリント配線板において、
    　前記中心導体の各端部に信号ビアを設け、その各信号ビアの直径を前記中心導体の各端部の直径より小さくしたことを特徴とする多層プリント配線板。     One and the other build-up layers deposited on both surfaces of the core layer, a cylindrical outer conductor penetrating the core layer and connected to the core layer, and a coaxial structure with the outer conductor in the core layer A central conductor equipped so as to form an insulator, and an insulator filled between the central conductor and the outer conductor, and the wiring provided in the build-up layer faces both ends of the central conductor In the multilayer printed wiring board arranged as
    A multilayer printed wiring board, wherein a signal via is provided at each end of the center conductor, and the diameter of each signal via is smaller than the diameter of each end of the center conductor.
  2. 　請求項１に記載の多層プリント配線板において、
    　前記信号ビアを、複数直列に重ねて接続して成るスタックビア構造としたことを特徴とする多層プリント配線板。     In the multilayer printed wiring board according to claim 1,
    A multilayer printed wiring board having a stacked via structure in which a plurality of the signal vias are connected in series.
  3. 　請求項１又は２に記載の多層プリント配線板において、
    　前記ビルドアップ層にシールドビアとシールド配線を設置し、このシールドビアとシールド配線を、前記外部導体に接続し且つ前記信号ビアの周囲に配置したことを特徴とする多層プリント配線板。     In the multilayer printed wiring board according to claim 1 or 2,
    A multilayer printed wiring board, wherein a shield via and a shield wiring are installed in the build-up layer, and the shield via and the shield wiring are connected to the external conductor and arranged around the signal via.
  4. 　請求項３に記載の多層プリント配線板において、
    　前記シールドビアを、複数直列に重ねて接続してスタックビア構造とし、それぞれの前記シールドビアに接続した前記シールド配線を前記ビルドアップ層に配置したことを特徴とする多層プリント配線板。     In the multilayer printed wiring board according to claim 3,
    A multilayer printed wiring board, wherein a plurality of the shield vias are connected in series to form a stack via structure, and the shield wiring connected to each of the shield vias is arranged in the build-up layer.
  5. 　請求項１乃至４の何れか一項に記載の多層プリント配線板において、
    　前記外部導体を、前記コア層の前記グランド層に接続したことを特徴とする多層プリント配線板。     In the multilayer printed wiring board according to any one of claims 1 to 4,
    A multilayer printed wiring board, wherein the outer conductor is connected to the ground layer of the core layer.
  6. 　請求項１乃至４の何れか一項に記載の多層プリント配線板において、
    　前記外部導体を、前記コア層に予め設けられた電源層に接続したことを特徴とする多層プリント配線板。     In the multilayer printed wiring board according to any one of claims 1 to 4,
    A multilayer printed wiring board, wherein the outer conductor is connected to a power supply layer provided in advance in the core layer.
  7. 　コア層の両面にそれぞれ堆積された一方と他方のビルドアップ層と、前記コア層を貫通し且つ当該コア層と連結された円筒状の外部導体と、前記コア層内に前記外部導体と同軸構造をなすように装備された信号伝達用の中心導体と、この中心導体と前記外部導体との間に充填された絶縁体と、前記中心導体の端部に対向してあらかじめ設けられた配線と、前記中心導体の少なくとも一方の端部に信号ビアとを設け、その信号ビアの直径が前記中心導体端部の直径より小さくしたことを特徴とする多層プリント配線板。 One and the other build-up layers deposited on both surfaces of the core layer, a cylindrical outer conductor penetrating the core layer and connected to the core layer, and a coaxial structure with the outer conductor in the core layer A center conductor for signal transmission equipped to form an insulator, an insulator filled between the center conductor and the outer conductor, and a wiring provided in advance facing an end of the center conductor, A multilayer printed wiring board, wherein a signal via is provided at at least one end of the central conductor, and the diameter of the signal via is smaller than the diameter of the central conductor end.
PCT/JP2010/062424 2009-08-12 2010-07-23 Multilayer printed circuit board WO2011018938A1 (en)

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