WO2011016219A1 - 電子デバイス用エピタキシャル基板およびその製造方法 - Google Patents
電子デバイス用エピタキシャル基板およびその製造方法 Download PDFInfo
- Publication number
- WO2011016219A1 WO2011016219A1 PCT/JP2010/004871 JP2010004871W WO2011016219A1 WO 2011016219 A1 WO2011016219 A1 WO 2011016219A1 JP 2010004871 W JP2010004871 W JP 2010004871W WO 2011016219 A1 WO2011016219 A1 WO 2011016219A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- single crystal
- resistance
- crystal substrate
- epitaxial
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 208
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims description 97
- 239000000203 mixture Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 5
- 239000000463 material Substances 0.000 description 17
- 239000012535 impurity Substances 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
Definitions
- the present invention relates to an epitaxial substrate for electronic devices and a method for manufacturing the same, and more particularly to an HEMT epitaxial substrate having a lateral direction as a current conduction direction and a method for manufacturing the same.
- HEMT high electron mobility transistor
- FET field effect transistor
- a field effect transistor for example, as schematically shown in FIG. 1, a channel layer 22 and an electron supply layer 23 are stacked on an insulating substrate 21, and a source electrode is formed on the surface of the electron supply layer 23. 24, the drain electrode 25 and the gate electrode 26 are generally provided.
- electrons move in the order of the source electrode 24, the electron supply layer 23, the channel layer 22, the electron supply layer 23, and the drain electrode 25, and the lateral direction becomes the main current conduction direction.
- the voltage applied to the gate electrode 26 is controlled.
- HEMT electrons generated at the junction interface between the electron supply layer 23 and the channel layer 22 having different band gaps can move at a higher speed than in a normal semiconductor.
- Patent Document 1 discloses. For the purpose of reducing substrate loss that degrades device performance, it is described that a Si substrate having a resistance value exceeding 1 ⁇ 10 2 ⁇ ⁇ cm is used.
- An object of the present invention is to provide an epitaxial substrate for an electronic device in which the lateral direction is a current conduction direction and the method for manufacturing the same, which solves the above problems and appropriately controls the warp shape.
- the gist of the present invention is as follows. (1) A step of bonding a low resistance Si single crystal substrate and a high resistance Si single crystal substrate to form a bonded substrate, and an insulating layer on the surface of the bonded substrate on the high resistance Si single crystal substrate side And forming a main laminate by epitaxially growing a plurality of group III nitride layers on the buffer, and producing an epitaxial substrate.
- a low resistance Si single crystal substrate a substrate having a high resistance Si single crystal substrate disposed above the low resistance Si single crystal substrate, and an insulating layer disposed on the high resistance Si single crystal substrate And a main laminate obtained by epitaxially growing a plurality of Group III nitride layers on the buffer, and the specific resistance of the low resistance Si single crystal substrate is 100 ⁇ ⁇ cm or less, and the high resistance
- the thickness of the low resistance Si single crystal substrate is not less than 10 times the thickness of the high resistance Si single crystal substrate, and the epitaxial for electronic devices according to (4), (5) or (6) above substrate.
- the present invention uses a low-resistance Si single crystal substrate and a substrate having a high-resistance Si single crystal substrate disposed above the low-resistance Si single crystal substrate, so that the warping shape is properly controlled.
- An epitaxial substrate for an electronic device having a current conduction direction and a manufacturing method thereof can be provided.
- FIG. 1 is a schematic cross-sectional view showing a general field effect transistor.
- FIG. 2 is a schematic cross-sectional view of an epitaxial substrate for an electronic device according to the present invention.
- 3 (a) and 3 (b) schematically show the shape of the warp when viewed in the cross section of the substrate.
- FIG. 3 (a) shows a state where the warp is uniformly warped in one direction.
- FIG. 3B shows a state in which the warping is uneven in both directions.
- 4 (a) to 4 (d) are schematic diagrams for explaining SORI and LTV of the present invention.
- FIGS. 5A and 5B are schematic cross-sectional views showing a warped shape as seen from a cross section of the epitaxial substrate according to the present invention.
- FIGS. 6A and 6B are schematic cross-sectional views showing a warped shape viewed from the cross section of the epitaxial substrate of the comparative example.
- FIG. 2 schematically shows a cross-sectional structure of an epitaxial substrate for an electronic device according to the present invention. Note that FIG. 2 shows the thickness direction exaggerated for convenience of explanation.
- an epitaxial substrate 1 for an electronic device has a low resistance Si single crystal substrate 2a and a high resistance Si single crystal substrate 2b disposed above the low resistance Si single crystal substrate 2a.
- a substrate 2, a buffer 3 as an insulating layer disposed on the high-resistance Si single crystal substrate 2 b, and a main laminate 4 in which a plurality of group III nitride layers are epitaxially grown on the buffer 3 are provided.
- the horizontal direction is the main current conduction direction
- a current flows from the source electrode 24 to the drain electrode 25 mainly in the width direction of the stacked body as shown in FIG.
- the shape of the warp when viewed in a cross section of the substrate, it means that the warp is uniformly warped in one direction as shown in FIG.
- the case where the shape is not uniform means a state where it is warped unevenly in both directions as shown in FIG.
- the substrate 2 is formed by bonding a low resistance Si single crystal substrate 2a and a high resistance Si single crystal substrate 2b, or a high resistance Si single crystal layer 2b on the low resistance Si single crystal substrate 2a. Is formed by epitaxial growth. Although not shown in FIG. 2, when the low-resistance Si single crystal substrate 2a and the high-resistance Si single crystal substrate 2b are bonded together, after forming an Si oxide film on the entire surfaces of these substrates 2a and 2b, these May be pasted together.
- the specific resistance of the low resistance Si single crystal substrate 2a is 100 ⁇ ⁇ cm or less.
- the lower limit is not particularly specified, but is preferably 0.001 ⁇ ⁇ cm or more which is industrially available by actual doping.
- the specific resistance of the low resistance Si single crystal substrate 2a is adjusted by adding a p-type impurity element and an n-type impurity element. Examples of the p-type and n-type impurity elements include boron and phosphorus, respectively.
- a substrate to which the impurity element is added is harder than a high-purity substrate to which no impurity is added.
- boron which is the lightest element among these impurities, is particularly preferable as an impurity element to be used because of its high binding energy and high effect of increasing the hardness of the substrate.
- impurities that contribute to conductivity C, H, O, Ge, N, and the like may be mixed at the same time. Depending on the impurities, it can be expected to further improve the hardness. Further, such a substrate is preferably manufactured by a CZ method.
- the specific resistance of the high resistance Si single crystal substrate 2b shall be 1000 ⁇ ⁇ cm or more.
- the upper limit is not particularly specified, but is preferably 20000 ⁇ ⁇ cm or less, which is industrially available due to actual high purity.
- an epitaxial substrate for electronic devices having excellent high frequency characteristics can be produced.
- the crystal faces of the main surfaces of the low resistance Si and the high resistance Si are not necessarily the same.
- a (110) plane can be used for a low resistance Si substrate, and a (111) plane suitable for epitaxial growth can be used for a high resistance Si substrate.
- the high resistance Si single crystal substrate 2b is an FZ that facilitates high purity of Si crystals. It is preferable to prepare by the method.
- the substrate 2 is formed by epitaxially growing the high-resistance Si single crystal layer (substrate) 2b on the low-resistance Si single crystal substrate 2a, the high-resistance Si single crystal layer 2b has a condition in which impurity contamination is suppressed as much as possible. And grow in equipment configuration. Since it is necessary to grow a thick single crystal, it is preferable to fabricate it using a thermal CVD method.
- the present invention uses the substrate 2 having the low-resistance Si single crystal substrate 2a and the high-resistance Si single crystal substrate 2b described above to achieve both high-frequency characteristics of the substrate and hardness for obtaining uniform warpage. It is something that can be done. Since the low-resistance Si single crystal substrate 2a and the high-resistance Si single crystal layer (substrate) 2b are made of the same material, warpage due to thermal stress can be expected to be suppressed.
- the thickness of the high-resistance Si single crystal substrate or the layer 2b is preferably 10 ⁇ m or more.
- the thickness is less than 10 ⁇ m, carriers existing in the low-resistance Si single crystal substrate 2a have inductive or capacitive interaction with carriers in the conductive layer of the electronic device layer, and operate at a high frequency of 1 GHz or more. This is because loss may occur.
- the thickness of the low-resistance Si single crystal substrate 2a is not particularly limited as long as it can maintain the shape of the substrate, but is preferably in the range of 100 to 2000 ⁇ m. If the thickness is less than 100 ⁇ m, it may be damaged during handling, and if it exceeds 2000 ⁇ m, handling due to the weight of the substrate may be difficult. Further, since the low resistance Si single crystal substrate needs to supplement the rigidity of the high resistance Si single crystal substrate, it is preferable to have a thickness of 10 times or more the thickness of the high resistance Si single crystal substrate. Note that the low-resistance Si single crystal substrate may be removed to improve heat dissipation during device manufacturing.
- the buffer 3 preferably has a superlattice structure or a graded composition structure.
- the superlattice structure means that the first layer 5a and the second layer 5b are stacked so as to include them periodically. It is possible to include a layer (for example, a composition transition layer) other than the first layer 5a and the second layer 5b.
- the gradient composition structure means that a specific group III element content is inclined in the film thickness direction.
- the buffer 3 preferably has an initial growth layer 6 in contact with the Si single crystal substrate 2 and a superlattice laminate 5 having a superlattice laminate structure on the initial growth layer 6.
- the initial growth layer 6 can be made of, for example, an AlN material.
- AlN an AlN material.
- the reaction with the high-resistance Si single crystal substrate 2b is suppressed, and the vertical breakdown voltage can be improved. This is because when the initial growth layer 6 is formed of a group III nitride material containing Ga and In, Ga and In react with Si of the substrate to generate a defect and induce a through defect in the epitaxial film. The purpose is to suppress the decrease in the longitudinal breakdown voltage.
- the AlN material mentioned here may contain trace impurities of 1% or less.
- impurities such as Ga, In, Si, H, O, C, B, Mg, As, P, etc. Can be included.
- the buffer 3 preferably has a C concentration of 1 ⁇ 10 18 atoms / cm 3 or more. This is to improve the vertical breakdown voltage.
- a plurality of group III nitride layers are epitaxially grown on the buffer 3 to form the main laminate 4 to produce an epitaxial substrate.
- the epitaxial substrate 1 for electronic devices is preferably used for HEMT.
- both layers can be composed of a single composition or a plurality of compositions.
- the portion 4a 2 in contact with at least the electron supply layer 4b of the channel layer 4a is preferably a GaN material.
- 1, 2 and 3 show examples of typical embodiments, and the present invention is not limited to these embodiments.
- an intermediate layer that does not adversely affect the effects of the present invention can be inserted between the layers, another superlattice layer can be inserted, or the composition can be graded.
- SORI means the difference between the maximum value and minimum value of the surface height during non-vacuum adsorption of the substrate shown in FIG. 4 (a), and LTV (Local thickness variation) is shown in FIG. As shown in b), it means the difference between the maximum value and the minimum value of each of the plurality of sites (10 mm ⁇ 10 mm) defined as shown in FIG.
- LTV Layer thickness variation
- FIG. 4C when the vacuum suction is insufficient, a gap is formed between the suction stage and the LTV is increased by this gap. Since exposure is performed with focus at each site, if the LTV is large, the focus is not achieved, resulting in poor exposure. Therefore, a small maximum value of LTV means that exposure failure is unlikely to occur.
- Both SORI and LTV measurements were performed under conditions of edge exclusion (outside of the outer circumference measurement station) of 3 mm.
- an initial growth layer AlN material, thickness: 100 nm
- a superlattice laminate AlN, thickness: 4 nm and Al 0.15 Ga 0.85 N are formed on the surface of the bonded substrate on the high resistance Si single crystal substrate side. , Thickness: 25 nm, 75 layers in total
- a channel layer GaN material, thickness: 0.75 ⁇ m
- an electron supply layer Al 0.27 Ga 0.73 N material
- a main laminate having a HEMT structure was formed by epitaxial growth (thickness: 18 nm) to obtain a sample.
- the C concentration of the superlattice laminate was 2.0 ⁇ 10 18 atoms / cm 3 .
- the portion of the channel layer on the electron supply layer side had a C concentration of 0.8 to 1.5 ⁇ 10 16 atoms / cm 3 .
- Table 1 shows the growth temperature and pressure of each layer.
- the growth method was MOCVD, TMA (trimethylaluminum) / TMG (trimethylgallium) was used as the group III material, ammonia was used as the group V material, and hydrogen and nitrogen gas were used as the carrier gas.
- the film-forming temperature here means the temperature of the substrate itself measured using a radiation thermometer during growth.
- FIG. 5 (a) shows the warped shape seen from the cross section of the epitaxial substrate thus formed.
- FIG. 5A shows the surface shape of the cross section of the substrate passing through the center portion of the orientation flat and the central portion of the substrate.
- Example 2 On the surface of the high resistance Si single crystal substrate side of the bonded substrate (SORI: 4.2 ⁇ m, LTV maximum value: 1.4 ⁇ m) formed in the same manner as in Example 1, an initial growth layer (AlN material, (Thickness: 100 nm) and an Al 0.6 Ga 0.4 N layer (thickness: 0.5 ⁇ m) and an Al 0.3 Ga 0.7 N layer (thickness: 0.3 ⁇ m) were sequentially grown to form a buffer, and on this gradient composition buffer layer A channel layer (GaN material: thickness 0.75 ⁇ m) and an electron supply layer (Al 0.27 Ga 0.73 N material, thickness: 18 nm) were epitaxially grown to form a main stack of HEMT structure, and a sample was obtained.
- AlN material Thinm
- Al 0.6 Ga 0.4 N layer thickness: 0.5 ⁇ m
- Al 0.3 Ga 0.7 N layer thickness: 0.3 ⁇ m
- the C concentration in the AlGaN layer was 2.0 ⁇ 10 18 atoms / cm 3 .
- the portion of the channel layer on the electron supply layer side had a C concentration of 0.8 to 1.5 ⁇ 10 16 atoms / cm 3 .
- Table 2 shows the growth temperature and pressure of each layer.
- the growth method was MOCVD, TMA (trimethylaluminum) / TMG (trimethylgallium) was used as the group III material, ammonia was used as the group V material, and hydrogen and nitrogen gas were used as the carrier gas.
- the film-forming temperature here means the temperature of the substrate itself measured using a radiation thermometer during growth.
- FIG. 5 (b) shows the warped shape seen from the cross section of the epitaxial substrate thus formed.
- FIG. 5B shows the surface shape of the cross section of the substrate passing through the center portion of the orientation flat and the central portion of the substrate.
- Example 1 (Comparative Example 1) Implemented on (111) 4 inch Si single crystal substrate (thickness: 600 ⁇ m, CZ method, B-doped, specific resistance: 6 ⁇ 10 3 ⁇ ⁇ cm, SORI: 3.1 ⁇ m, maximum LTV value: 0.9 ⁇ m)
- FIG. 6A shows a warped shape as viewed from the cross section of the epitaxial substrate thus formed.
- FIG. 6A shows the surface shape of the cross section of the substrate passing through the center portion of the orientation flat and the central portion of the substrate.
- SORI and LTV of this epitaxial substrate were measured, SORI was 21.8 ⁇ m, and the maximum value of LTV was 3.0 ⁇ m.
- Comparative Example 2 On the same Si single crystal substrate (SORI: 3.0 ⁇ m, maximum value of LTV: 0.9 ⁇ m) as in Comparative Example 1, the same structure as in Example 2 was formed under the same conditions to obtain a sample.
- FIG. 6B shows the warped shape seen from the cross section of the epitaxial substrate thus formed.
- FIG. 6B shows the surface shape of the cross section of the substrate passing through the orientation flat center and the substrate center.
- the epitaxial substrates of Comparative Examples 1 and 2 have a downwardly convex shape at the center, but a region close to the periphery of the substrate has an upwardly convex shape.
- the outer peripheries hanged down by about 5 ⁇ m and about 10 ⁇ m, respectively, and were M-shaped as a whole.
- there were many sites in the periphery of the substrate where the thickness unevenness of each site exceeded 2 ⁇ m. The reason is that the back surface was not evenly adsorbed.
- FIGS. 6 (a) and 6 (b) the epitaxial substrates of Comparative Examples 1 and 2 have a downwardly convex shape at the center, but a region close to the periphery of the substrate has an upwardly convex shape.
- the outer peripheries hanged down by about 5 ⁇ m and about 10 ⁇ m, respectively, and were M-shaped as a whole.
- there were many sites in the periphery of the substrate where the thickness unevenness of each site exceeded 2
- the epitaxial substrates of Examples 1 and 2 according to the present invention had a downward convex shape and a uniform shape as a whole. As shown in Table 3, the maximum value of LTV after epitaxial growth did not increase compared to the maximum value of LTV before epitaxial growth.
- the warpage shape is appropriately controlled. It is possible to provide an epitaxial substrate for an electronic device whose direction is a current conduction direction and a method for manufacturing the same.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
(1)低抵抗Si単結晶基板と高抵抗Si単結晶基板とを貼り合わせて貼り合わせ基板を形成する工程と、該貼り合わせ基板の高抵抗Si単結晶基板側の表面上に、絶縁層としてのバッファを形成する工程と、該バッファ上に、複数層のIII族窒化物層をエピタキシャル成長させて主積層体を形成してエピタキシャル基板を作製する工程とを具え、前記低抵抗Si単結晶基板の比抵抗が100Ω・cm以下であり、かつ前記高抵抗Si単結晶基板の比抵抗が1000Ω・cm以上であることを特徴とする横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法。
(111)面4インチ高抵抗Si単結晶基板(厚さ:40μm,FZ法,意図的なドープ無し,比抵抗:6×103Ω・cm)と(111)面4インチ低抵抗Si単結晶基板(厚さ:560μm,CZ法,Bドープ,比抵抗:15Ω・cm)とを張り合わせて、貼り合わせ基板を用意した。この高抵抗Si単結晶基板は、予め熱酸化することにより基板の両面にSi酸化膜を形成後、片面のSi酸化膜を除去することにより形成した、一方の面にSi酸化膜(厚さ:1μm)を有し、上記貼り合わせは、このSi酸化膜を介して行った。
(111)面4インチSi単結晶基板(厚さ:600μm,CZ法,Bドープ,比抵抗:6×103Ω・cm,SORI:3.1μm、LTVの最大値:0.9μm)上に、実施例1と同様の構造を同条件にて形成し、試料を得た。このようにして形成されたエピタキシャル基板の断面から見た反り形状を図6(a)に示す。図6(a)は、オリエンテーションフラット中心部と基板中心部とを通る基板断面の表面形状を表している。このエピタキシャル基板のSORIおよびLTVを測定したところ、SORIは21.8μm、LTVの最大値は3.0μmであった。
比較例1と同様のSi単結晶基板(SORI:3.0μm、LTVの最大値:0.9μm)上に、実施例2と同様の構造を同条件にて形成し、試料を得た。このようにして形成されたエピタキシャル基板の断面から見た反り形状を図6(b)に示す。図6(b)は、オリエンテーションフラット中心部と基板中心部とを通る基板断面の表面形状を表している。このエピタキシャル基板のSORIおよびLTVを測定したところ、SORIは36.9μm、LTVの最大値は3.5μmであった。
2 基板
2a 低抵抗Si単結晶基板
2b 高抵抗Si単結晶基板
3 バッファ
4 主積層体
4a チャネル層
4b 電子供給層
5 超格子積層体
5a 第1層
5b 第2層
6 初期成長層
21 絶縁性基板
22 チャネル層
23 電子供給層
24 ソース電極
25 ドレイン電極
26 ゲート電極
Claims (9)
- 低抵抗Si単結晶基板と高抵抗Si単結晶基板とを貼り合わせて貼り合わせ基板を形成する工程と、該貼り合わせ基板の高抵抗Si単結晶基板側の表面上に、絶縁層としてのバッファを形成する工程と、該バッファ上に、複数層のIII族窒化物層をエピタキシャル成長させて主積層体を形成してエピタキシャル基板を作製する工程とを具え、前記低抵抗Si単結晶基板の比抵抗が100Ω・cm以下であり、かつ前記高抵抗Si単結晶基板の比抵抗が1000Ω・cm以上であることを特徴とする横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法。
- 前記貼り合わせ基板を形成する工程は、前記低抵抗Si単結晶基板と前記高抵抗Si単結晶基板との貼り合わせを、Si酸化膜を介して行う請求項1に記載の電子デバイス用エピタキシャル基板の製造方法。
- 低抵抗Si単結晶基板上に、高抵抗Si単結晶層をエピタキシャル成長させる工程と、前記高抵抗Si単結晶層上に、絶縁層としてのバッファを形成する工程と、該バッファ上に、複数層のIII族窒化物層をエピタキシャル成長させて主積層体を形成してエピタキシャル基板を作製する工程とを具え、前記低抵抗Si単結晶基板の比抵抗が100Ω・cm以下であり、かつ前記高抵抗Si単結晶層の比抵抗が1000Ω・cm以上であることを特徴とする横方向を電流導通方向とする電子デバイス用エピタキシャル基板の製造方法。
- 低抵抗Si単結晶基板および該低抵抗Si単結晶基板の上方に配設された高抵抗Si単結晶基板を有する基板と、前記高抵抗Si単結晶基板上に配設された絶縁層としてのバッファと、該バッファ上に、複数層のIII族窒化物層をエピタキシャル成長させた主積層体とを具え、前記低抵抗Si単結晶基板の比抵抗が100Ω・cm以下であり、かつ前記高抵抗Si単結晶基板の比抵抗が1000Ω・cm以上であることを特徴とする横方向を電流導通方向とする電子デバイス用エピタキシャル基板。
- 前記低抵抗Si単結晶基板および前記高抵抗Si単結晶基板の間にSi酸化膜を設ける請求項4に記載の電子デバイス用エピタキシャル基板。
- 前記高抵抗Si単結晶基板の厚さは、10μm以上である請求項4または5に記載の電子デバイス用エピタキシャル基板。
- 前記低抵抗Si単結晶基板の厚さは、前記高抵抗Si単結晶基板の厚さの10倍以上である請求項4、5または6に記載の電子デバイス用エピタキシャル基板。
- 前記バッファは、超格子構造または傾斜組成構造を有する請求項4~7のいずれか一項に記載の電子デバイス用エピタキシャル基板。
- 前記バッファは、C濃度が1×1018atoms/cm3以上である請求項4~8のいずれか一項に記載の電子デバイス用エピタキシャル基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011525781A JP5665745B2 (ja) | 2009-08-04 | 2010-08-02 | 電子デバイス用エピタキシャル基板およびその製造方法 |
US13/388,804 US8946863B2 (en) | 2009-08-04 | 2010-08-02 | Epitaxial substrate for electronic device comprising a high resistance single crystal substrate on a low resistance single crystal substrate, and method of manufacturing |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-181669 | 2009-08-04 | ||
JP2009181669 | 2009-08-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011016219A1 true WO2011016219A1 (ja) | 2011-02-10 |
Family
ID=43544129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/004871 WO2011016219A1 (ja) | 2009-08-04 | 2010-08-02 | 電子デバイス用エピタキシャル基板およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8946863B2 (ja) |
JP (1) | JP5665745B2 (ja) |
WO (1) | WO2011016219A1 (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011103380A (ja) * | 2009-11-11 | 2011-05-26 | Covalent Materials Corp | 化合物半導体基板 |
JP2015002329A (ja) * | 2013-06-18 | 2015-01-05 | シャープ株式会社 | エピタキシャルウェハおよびその製造方法並びに窒化物半導体装置 |
JP2016222539A (ja) * | 2016-07-22 | 2016-12-28 | 住友化学株式会社 | 窒化物半導体エピタキシャル基板の製造方法、及び窒化物半導体デバイスの製造方法 |
EP2546880A3 (en) * | 2011-07-15 | 2017-07-05 | International Rectifier Corporation | Composite semiconductor device with integrated diode |
WO2021005872A1 (ja) | 2019-07-11 | 2021-01-14 | 信越半導体株式会社 | 電子デバイス用基板およびその製造方法 |
WO2021024654A1 (ja) | 2019-08-06 | 2021-02-11 | 信越半導体株式会社 | 電子デバイス用基板およびその製造方法 |
JP7541073B2 (ja) | 2022-01-03 | 2024-08-27 | 環球晶圓股▲ふん▼有限公司 | 半導体構造 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014041736A1 (ja) * | 2012-09-13 | 2014-03-20 | パナソニック株式会社 | 窒化物半導体構造物 |
US10692839B2 (en) * | 2015-06-26 | 2020-06-23 | Intel Corporation | GaN devices on engineered silicon substrates |
CN108886000A (zh) * | 2016-02-26 | 2018-11-23 | 三垦电气株式会社 | 半导体基体以及半导体装置 |
DE102016223622A1 (de) * | 2016-11-29 | 2018-05-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Halbleiterbauelement und Verfahren zu dessen Herstellung |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196308A (ja) * | 2000-01-11 | 2001-07-19 | Tokin Corp | シリコンウエハーおよびその製造方法およびそれを用いた半導体素子 |
JP2002299254A (ja) * | 2001-03-30 | 2002-10-11 | Toyota Central Res & Dev Lab Inc | 半導体基板の製造方法及び半導体素子 |
JP2008262973A (ja) * | 2007-04-10 | 2008-10-30 | Toyota Motor Corp | 半導体ウエハとその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6008110A (en) * | 1994-07-21 | 1999-12-28 | Kabushiki Kaisha Toshiba | Semiconductor substrate and method of manufacturing same |
US5897362A (en) * | 1998-04-17 | 1999-04-27 | Lucent Technologies Inc. | Bonding silicon wafers |
US7011707B2 (en) | 2001-03-30 | 2006-03-14 | Toyoda Gosei Co., Ltd. | Production method for semiconductor substrate and semiconductor element |
US7112830B2 (en) * | 2002-11-25 | 2006-09-26 | Apa Enterprises, Inc. | Super lattice modification of overlying transistor |
US7339205B2 (en) * | 2004-06-28 | 2008-03-04 | Nitronex Corporation | Gallium nitride materials and methods associated with the same |
US7247889B2 (en) | 2004-12-03 | 2007-07-24 | Nitronex Corporation | III-nitride material structures including silicon substrates |
CN101331249B (zh) * | 2005-12-02 | 2012-12-19 | 晶体公司 | 掺杂的氮化铝晶体及其制造方法 |
-
2010
- 2010-08-02 JP JP2011525781A patent/JP5665745B2/ja active Active
- 2010-08-02 WO PCT/JP2010/004871 patent/WO2011016219A1/ja active Application Filing
- 2010-08-02 US US13/388,804 patent/US8946863B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196308A (ja) * | 2000-01-11 | 2001-07-19 | Tokin Corp | シリコンウエハーおよびその製造方法およびそれを用いた半導体素子 |
JP2002299254A (ja) * | 2001-03-30 | 2002-10-11 | Toyota Central Res & Dev Lab Inc | 半導体基板の製造方法及び半導体素子 |
JP2008262973A (ja) * | 2007-04-10 | 2008-10-30 | Toyota Motor Corp | 半導体ウエハとその製造方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011103380A (ja) * | 2009-11-11 | 2011-05-26 | Covalent Materials Corp | 化合物半導体基板 |
EP2546880A3 (en) * | 2011-07-15 | 2017-07-05 | International Rectifier Corporation | Composite semiconductor device with integrated diode |
JP2015002329A (ja) * | 2013-06-18 | 2015-01-05 | シャープ株式会社 | エピタキシャルウェハおよびその製造方法並びに窒化物半導体装置 |
JP2016222539A (ja) * | 2016-07-22 | 2016-12-28 | 住友化学株式会社 | 窒化物半導体エピタキシャル基板の製造方法、及び窒化物半導体デバイスの製造方法 |
WO2021005872A1 (ja) | 2019-07-11 | 2021-01-14 | 信越半導体株式会社 | 電子デバイス用基板およびその製造方法 |
US11705330B2 (en) | 2019-07-11 | 2023-07-18 | Shin-Etsu Handotai Co., Ltd. | Substrate for electronic device and method for producing the same |
WO2021024654A1 (ja) | 2019-08-06 | 2021-02-11 | 信越半導体株式会社 | 電子デバイス用基板およびその製造方法 |
JP2021027186A (ja) * | 2019-08-06 | 2021-02-22 | 信越半導体株式会社 | 電子デバイス用基板およびその製造方法 |
JP7541073B2 (ja) | 2022-01-03 | 2024-08-27 | 環球晶圓股▲ふん▼有限公司 | 半導体構造 |
Also Published As
Publication number | Publication date |
---|---|
US8946863B2 (en) | 2015-02-03 |
JPWO2011016219A1 (ja) | 2013-01-10 |
JP5665745B2 (ja) | 2015-02-04 |
US20120153440A1 (en) | 2012-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5665745B2 (ja) | 電子デバイス用エピタキシャル基板およびその製造方法 | |
US10388517B2 (en) | Epitaxial substrate for electronic device and method of producing the same | |
US8426893B2 (en) | Epitaxial substrate for electronic device and method of producing the same | |
JP4685953B2 (ja) | 横方向を電流導通方向とする電子デバイス用エピタキシャル基板およびその製造方法 | |
KR101273040B1 (ko) | 전자 디바이스용 에피택셜 기판 및 그 제조 방법 | |
JP4908886B2 (ja) | 半導体装置 | |
CN104137226A (zh) | 适用于具有异质衬底的iii族氮化物器件的缓冲层结构 | |
US8785942B2 (en) | Nitride semiconductor substrate and method of manufacturing the same | |
WO2013168371A1 (ja) | エピタキシャル基板、半導体装置及び半導体装置の製造方法 | |
JP5543866B2 (ja) | Iii族窒化物エピタキシャル基板 | |
JP2009260296A (ja) | 窒化物半導体エピタキシャルウエハ及び窒化物半導体素子 | |
JP5546301B2 (ja) | 電子デバイス用エピタキシャル基板およびその製造方法 | |
JP2016219690A (ja) | 13族窒化物半導体基板 | |
JP2014022698A (ja) | 窒化物半導体成長用Si基板およびそれを用いた電子デバイス用エピタキシャル基板およびそれらの製造方法 | |
CN113539786B (zh) | 硅基氮化镓外延结构及其制备方法 | |
TWI441331B (zh) | A epitaxial substrate for electronic components and a method for manufacturing the same | |
JP6404738B2 (ja) | 電子デバイス用エピタキシャル基板および高電子移動度トランジスタならびにそれらの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10806219 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2011525781 Country of ref document: JP Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13388804 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 10806219 Country of ref document: EP Kind code of ref document: A1 |