WO2010147059A1 - Circuit électronique, son procédé de formation et stratifié cuivré pour la formation de circuit électronique - Google Patents

Circuit électronique, son procédé de formation et stratifié cuivré pour la formation de circuit électronique Download PDF

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Publication number
WO2010147059A1
WO2010147059A1 PCT/JP2010/059947 JP2010059947W WO2010147059A1 WO 2010147059 A1 WO2010147059 A1 WO 2010147059A1 JP 2010059947 W JP2010059947 W JP 2010059947W WO 2010147059 A1 WO2010147059 A1 WO 2010147059A1
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Prior art keywords
copper
layer
etching
electronic circuit
forming
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PCT/JP2010/059947
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English (en)
Japanese (ja)
Inventor
敬亮 山西
賢吾 神永
亮 福地
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Jx日鉱日石金属株式会社
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Priority to JP2011519752A priority Critical patent/JP5676443B2/ja
Publication of WO2010147059A1 publication Critical patent/WO2010147059A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors

Definitions

  • the present invention relates to an electronic circuit for forming a circuit by etching, a method for forming the same, and a copper-clad laminate for forming an electronic circuit.
  • Copper foil for printed circuits is widely used in electronic and electrical equipment, but this copper foil for printed circuits is generally used with a base material such as a synthetic resin board or film with or without an adhesive. Bonding under high temperature and high pressure to produce a copper clad laminate, then printing the circuit by resist coating and exposure process to form the desired circuit, and further through an etching process to remove unnecessary portions of the copper foil Further, various elements are soldered to form a printed circuit for an electro device.
  • Copper foils used in such printed circuits are broadly divided into electrolytic copper foils and rolled copper foils depending on the type of manufacturing method, both of which are used according to the types of printed circuit boards and quality requirements. Yes. These copper foils have a surface to be bonded to the resin base material and a non-bonded surface, and are each subjected to a special surface treatment (treating treatment). In some cases, the copper foil used for the inner layer of the multilayer printed wiring board has a function of adhering to the resin on both sides (double treatment).
  • electrolytic copper foil is produced by electrodepositing copper onto a rotating drum and continuously peeling it to produce a copper foil.
  • the surface that contacts the rotating drum is a glossy surface and the opposite surface. Has many irregularities (rough surface).
  • a thin plating layer may be formed in order to prevent such copper particles from falling off while enhancing such unevenness.
  • a series of these steps is called roughening treatment.
  • Such a roughening treatment is required not only for the electrolytic copper foil but also for the rolled copper foil, and the same roughening treatment is also carried out for the rolled copper foil.
  • Copper-clad laminates are manufactured by hot pressing and continuous processes using the above copper foil.
  • this laminated plate is produced by synthesize epoxy resin, impregnate paper substrate with phenol resin, and dry it to produce a prepreg, and further combine this prepreg and copper foil with a combination press. It is manufactured through processes such as hot pressing.
  • the copper-clad laminate produced in this way is printed by a resist coating and exposure process to form the target circuit, and further undergoes an etching process to remove unnecessary portions of the copper layer.
  • an etching process to remove unnecessary portions of the copper layer.
  • Such “sag” needs to be made as small as possible.
  • the “sag” is reduced by extending the etching time and increasing the etching time.
  • the circuit width will be reduced accordingly, and the uniform line width (circuit width) that is intended for circuit design will be reduced.
  • the uniform line width (circuit width) that is intended for circuit design will be reduced.
  • the present inventors have proposed a copper foil in which a metal or alloy layer (hereinafter referred to as an EF layer) having a slower etching rate than copper is formed on a copper foil on the etching surface side (Patent Literature). 1).
  • the metal or alloy is nickel, cobalt, or an alloy thereof.
  • circuit shape improvement effect does not reach the copper plating layer formed on the EF layer when the copper plating step is further included on the EF layer as a pre-process of circuit formation.
  • the EF layer is removed, so that there is a problem that the circuit shape cannot be improved.
  • the effect of improving the circuit shape cannot be obtained in the first place in a laminated board using a copper foil in which an EF layer is not formed or a laminated board in which a copper layer is formed on a resin film.
  • the present invention when performing circuit formation by etching the copper layer of the copper-clad laminate, prevents sagging due to etching, can form a uniform circuit of the desired circuit width, and further improve the etchability by pattern etching, It is an object of the present invention to obtain an electronic circuit, a method for forming the same, and a copper-clad laminate for forming an electronic circuit that can prevent the occurrence of short circuits and circuit width defects.
  • the inventors of the present invention added the process of forming the EF layer to a process as close as possible to the etching process for forming a circuit, that is, a process in which the EF layer formed by the subsequent processing is not removed. It was found that the problem can be solved by adjusting the etching in the thickness direction of the layer to effectively form a uniform circuit with a small circuit width.
  • the present invention is based on this finding, 1) A copper or copper alloy layer (A) formed on one or both sides of a resin substrate, a copper or copper alloy layer (B) formed on a part or the entire surface of the (A) layer, the (B ) A layered body composed of a layer (C) having a slower etching rate than copper with respect to a copper etchant formed on a part or the entire surface of the layer, the layer (A), the layer (B) and (C) Provided is an electronic circuit comprising a copper circuit formed by etching and removing a part of a laminated portion of a layer to the surface of a resin substrate.
  • the (A) layer may be a copper foil provided in advance with a layer (C ′) having an etching rate slower than that of copper with respect to the copper etchant.
  • the laminate includes the (A) layer, the ( A) A laminate composed of the (C ′) layer formed on a part or the entire surface of the layer, the (B) layer, and the (C) layer may be used.
  • the present invention also provides: 2) Copper or copper alloy layer (A) formed on one or both sides of a resin substrate, and an etching rate slower than copper with respect to a copper etching solution formed on a part or the entire surface of the (A) layer A layered product composed of layer (C), comprising a copper circuit formed by etching and removing a part of the layered portion of layers (A) and (C) to the surface of the resin substrate.
  • An electronic circuit is provided.
  • the copper foil used for the (A) layer may be a copper foil having a layer corresponding to the (C) layer in advance, but is formed on the surface as necessary.
  • the treatment layer (such as a rust prevention layer and a heat-resistant layer) including the (C) layer may be removed by etching or the like in the process in order to adjust the thickness of the (A) layer. In any case, the effect is not changed by forming the (C) layer before etching for circuit formation.
  • the present invention also provides: 3)
  • the layer (C) having an etching rate slower than that of copper with respect to the copper etchant is any one of nickel, cobalt, iron, platinum group elements, gold, silver, a combination thereof, or a combination thereof.
  • An electronic circuit according to any one of 1) and 2), which is an alloy containing a main component, is provided.
  • the present invention also provides: 4) deposition of the layer (C) is an electronic circuit according to any one of 3) to be 1), characterized in that it is 50 ⁇ g / dm 2 ⁇ 3000 ⁇ g / dm 2, provided.
  • the present invention also provides: 5)
  • the surface of the copper or copper alloy layer (A) opposite to the surface in contact with the resin is a surface treated by at least one of pickling treatment, soft etching, or surface roughening treatment.
  • An electronic circuit according to any one of 1) to 4) is provided.
  • the surface of the copper or copper alloy layer (A) that is opposite to the surface in contact with the resin is a surface that has been reduced by one or more pickling, soft etching, or one or more treatments that roughen the surface.
  • An electronic circuit according to any one of 1) to 5) is provided.
  • the present invention also provides: 7) A copper or copper alloy layer (A) on one or both sides of the resin substrate, then a copper or copper alloy layer (B) on a part or the entire surface of the (A) layer, and the (B ) A layer (C) having a slower etching rate than copper is formed on a part or the entire surface of the layer to produce a copper-clad laminate, and then the copper-clad laminate (( A method of forming an electronic circuit comprising a step of forming a copper circuit by etching and removing a part of the laminated portion composed of the A) layer, the (B) layer, and the (C) layer to the surface of the resin substrate I will provide a.
  • the present invention also provides: 8) A copper or copper alloy layer (A) is formed on one side or both sides of a resin substrate to produce a copper clad laminate, a through hole is formed in the copper clad laminate, and further on the (A) layer. After a plating layer made of a copper or copper alloy layer (B) is formed in a part or the entire surface and in the through hole, a part or the entire surface of the (B) layer is more than copper for the copper etching solution.
  • a copper circuit is formed by forming a layer (C) having a slow etching rate, and further etching and removing a part of the laminate composed of the (A) layer, the (B) layer, and the (C) layer to the resin substrate surface.
  • a method for forming an electronic circuit comprising the steps of forming.
  • the present invention also provides: 9) A layer of copper or copper alloy (A) on one or both sides of the resin substrate, and then a layer having a slower etching rate than copper with respect to the copper etchant on a part or the whole of the layer (A) ( C) is formed to produce a copper clad laminate, and then a part of the laminate composed of the (A) layer and (C) layer of this copper clad laminate is etched and removed to the resin substrate surface.
  • a method for forming an electronic circuit characterized by comprising a step of forming a copper circuit.
  • the present invention also provides: 10) The thickness of the copper or copper alloy layer (A) is adjusted by etching the copper or copper alloy layer (A) formed on one or both sides of the resin substrate, and the thickness of these layers is adjusted. Next, a layer (C) whose etching rate is slower than that of copper is formed to produce a copper-clad laminate, and then a part of the layered portion of the layers (A) and (C) is removed to the resin substrate surface by etching.
  • a method for forming an electronic circuit is provided.
  • the present invention also provides: 11) A copper or copper alloy layer (A) on one or both sides of the resin substrate has a slower etching rate than copper on the copper foil surface in advance with respect to a copper etching solution as a copper foil used when forming the layer.
  • the present invention also provides: 12) The method for forming an electronic circuit according to any one of 7) to 11), wherein a heat-resistant layer and / or a rust-proof layer is formed on the (C) or (C ′) layer, provide.
  • the present invention also provides: 13) As a layer (C) or a layer (C ′) whose etching rate is slower than copper with respect to the copper etching solution, any one metal of nickel, cobalt, iron, platinum group element, gold, silver, or A method of forming an electronic circuit according to any one of 7) to 12), characterized by using a combination thereof or an alloy containing these as a main component.
  • the present invention also provides: 14) The deposition amount of the layer (C) or layer (C'), the electronic circuit according to any one of 7), characterized in that adjusting the 50 ⁇ g / dm 2 ⁇ 3000 ⁇ g / dm 2 13) A forming method is provided.
  • the present invention also provides: 15) The electronic circuit according to any one of 7) to 14), wherein the layer (A) of copper or copper alloy is treated by one or more of pickling treatment, soft etching, or surface roughening treatment.
  • a forming method is provided.
  • the present invention also provides: 16) The thickness of the copper or copper alloy layer (A layer) is reduced by pickling, soft etching, or one or more treatments for roughening the surface, according to any one of 7) to 15), A method of forming an electronic circuit is provided.
  • the present invention also provides: 17) A copper or copper alloy layer (A) is formed on one or both sides of a resin substrate to produce a copper clad laminate, a through hole is formed in the copper clad laminate, and further on the layer (A). After a plating layer made of a copper or copper alloy layer (B) is formed in part or the entire surface and in the through hole, etching is performed on the part or the entire surface of the (B) layer with respect to a copper etching solution rather than copper. A slow-speed layer (C) is formed, and a copper circuit is formed by etching and removing a part of the laminated portion composed of the layers (A), (B), and (C) to the resin substrate surface.
  • a copper-clad laminate for forming an electronic circuit wherein a copper or copper alloy layer (A) is formed on one or both sides of a resin substrate before through-hole formation, and a copper or copper alloy layer (B) formed thereafter Pickling at least one of the plating layer (through-hole plating layer) made of Providing a copper-clad laminate, for electronic circuit formation, characterized by being the thickness reduction processing by the / and soft etching.
  • etching a copper circuit as an electronic circuit on a copper clad laminate was taken as an example.
  • the purpose is to obtain a more prominent shape by etching, a copper bump that is a form of an electronic circuit It can be applied to all related technologies such as formation.
  • the present invention has an effect that when a circuit is formed by etching a copper layer of a copper clad laminate, a circuit having a more uniform circuit width can be formed. Further, there is an effect that the occurrence of sagging due to etching can be prevented. This has the remarkable effect that it is possible to provide an excellent method for forming an electronic circuit capable of improving the etching property by pattern etching and preventing the occurrence of a short circuit or a defective circuit width.
  • the present invention relates to an electronic circuit and a method for forming the circuit by etching, and a copper clad laminate used in the method.
  • a copper or copper alloy layer (B) layer is formed on a copper or copper alloy layer (A) formed on a resin substrate. That is, this copper layer (B) is a copper layer newly formed on the copper-clad laminate by through-hole plating or the like.
  • the thickness of the layer (A) is reduced by soft etching or the like.
  • the copper or copper alloy layer (A) may be a plating layer directly formed on a resin substrate or a copper or copper alloy layer made of an adhered foil. That is, for the layer (A), a copper clad laminate in which a copper layer is directly formed after a surface treatment such as a plasma treatment on a resin film such as polyimide can be used without using a copper foil. . In this case, as in the case where the foil to be bonded is a foil not previously provided with an EF layer, the surface does not have an EF layer at this stage.
  • the formation of the (B) layer is mainly performed by a wet plating method, but has a feature that a new copper surface is formed. Further, when the thickness of the layer (A) is reduced by soft etching, a new copper surface appears in the same manner.
  • (A) layer reduced in thickness by soft etching, or (A) layer using a copper foil in which an EF layer has not been formed in advance copper is added to the copper etching solution.
  • a layer (C) layer having a slower etching rate is formed.
  • a material having a slower etching rate than copper is selected for the copper etchant.
  • any one metal of nickel, cobalt, iron, platinum group, gold and silver, a combination thereof, or an alloy containing these as a main component is suitable.
  • any one metal of nickel, platinum group, and gold, or a combination thereof, or an alloy containing these as a main component is desirable.
  • the nickel or nickel alloy layer will be specifically described by way of example.
  • the nickel or nickel alloy layer is located close to the resist portion on the copper foil, and the etching rate of the copper foil on the resist side is suppressed by this nickel or nickel alloy layer.
  • the copper etching proceeds at a normal rate as the distance from the nickel alloy layer increases.
  • etching proceeds substantially vertically from the resist side of the side surface of the copper circuit toward the resin substrate side, and a rectangular copper foil circuit is formed.
  • the nickel or nickel alloy layer or the like mainly suppresses the occurrence of sagging and forms a circuit with a uniform circuit width.
  • etching solution with a ferric chloride aqueous solution having a high etching rate. This is because there is a problem that the etching rate decreases due to circuit miniaturization.
  • An etching solution using a ferric chloride aqueous solution is an effective means for preventing this. However, this does not prevent the use of other etchants.
  • the etching solution can be changed as necessary.
  • the space on the resin substrate formed between the copper circuits can be adjusted to a width corresponding to the thickness (T) of the copper layer including the (A) layer and the (B) layer.
  • T thickness of the copper layer including the (A) layer and the (B) layer.
  • the circuit width can be arbitrarily designed according to the application.
  • An organic rust preventive layer such as a chrome layer or a chromate layer and / or a silane treatment can be further formed on the (C) layer.
  • this amount by appropriately selecting this amount, the oxidation of the surface of the (C) layer can be similarly suppressed, so that the stability is further stabilized.
  • a circuit width pattern can be formed.
  • discoloration resistance means a function capable of suppressing discoloration during storage and thermal discoloration during solder mounting.
  • the load of the C layer removal step increases during soft etching, and a processing residue may occur depending on the case. This hinders circuit design. Therefore, it is necessary to set the above range.
  • chromium amount when providing the said chromium layer or chromate layer, chromium amount shall be 100 microgram / dm ⁇ 2 > or less in conversion of metal chromium. Moreover, when forming the said silane treatment layer, it is desirable that it is 20 microgram / dm ⁇ 2 > or less in conversion of silicon simple substance. This is to suppress the difference in etching rate with respect to the pattern etching solution. However, an appropriate amount is effective to prevent oxidation of the (C) layer.
  • silane treatment Select from various series of silanes such as: Silane dissolved in alcohol is diluted with water to a predetermined concentration and applied to the copper foil surface. Concentration: 0.01 wt% to 2 wt% Type: Olefin silane, Epoxy silane, Acrylic silane, Amino silane, Mercapto silane
  • Chromium adhesion analysis method In order to analyze the treated surface, the opposite surface is pressed with FR-4 resin and masked. The sample is boiled in hydrochloric acid having a concentration of 10% for 3 minutes to dissolve the treatment layer, and the solution is quantitatively analyzed for zinc and chromium by atomic absorption analysis.
  • a resist pattern for forming a circuit is formed on the layer (C), and an etching solution made of a cupric chloride solution or a ferric chloride solution is used, and a portion other than the portion to which the resist pattern is attached Unnecessary portions of the laminated portion of the (A) layer, (B) layer, and (C) layer on the resin substrate are removed to the surface of the resin substrate. Next, the resist is removed, and if necessary, the remaining (C) layer is removed by soft etching. The removal of the unnecessary copper foil from the formation of the resist pattern is a commonly performed technique, and therefore, it is not necessary to explain much and is omitted.
  • the present invention for example, it is possible to form a circuit having a space of 2 times or less, further 1.5 times or less of the thickness (T) of the copper layer including the (A) layer and the (B) layer.
  • T thickness of the copper layer including the (A) layer and the (B) layer.
  • More preferable implementation conditions are as follows. After the (A) layer is formed by plating or pasting as described above, the copper foil on the exposed surface of the A layer, which is a copper foil, is protected before the (B) layer is formed. Therefore, it is desirable to remove the layer applied for this purpose by etching or the like in advance. This is to improve the subsequent plating adhesion.
  • copper foil When copper foil is used as the copper or copper alloy layer formed on the resin substrate, it can be similarly applied to the roughened surface (M surface) or glossy surface (S surface) of the electrolytic copper foil, but the surface to be etched is Usually use the glossy side.
  • a rolled copper foil When using a rolled copper foil, a high purity rolled copper foil or a rolled alloy copper foil with improved strength can also be used.
  • the present invention includes all of these copper foils.
  • the etching factor is defined as the point of intersection between the perpendicular line from the upper surface of the copper foil and the resin substrate, assuming that the circuit is etched vertically when etching is performed in a divergent manner (when sagging occurs).
  • the ratio of this a to the thickness b of the copper foil: b / a is shown.
  • the larger this value the greater the inclination angle and the etching. It means that no residue remains and dripping is reduced.
  • a present Example is an example for making an understanding easy, and is not restrict
  • the copper plating solution and conditions are the same as those described in Japanese Patent Application Laid-Open No. 2004-107786.
  • Example 1 An electrolytic copper foil having a foil thickness of 18 ⁇ m was used. This electrolytic copper foil was bonded to a polyimide resin substrate to obtain a copper-clad laminate. Next, a copper plating layer of 20 ⁇ m was formed on this copper clad laminate. The copper plating was performed as described above. As a result, the total thickness of the electrolytic copper foil and the copper plating layer on the resin substrate was 38 ⁇ m. Next, a gold sputter layer having an adhesion amount of 400 ⁇ g / dm 2 was formed on the copper plating layer under the above-mentioned gold sputtering conditions, and a chromate layer was formed under the above-mentioned chromate conditions.
  • the closest width of the space on the resin substrate formed between the copper circuits was 1.8 times the thickness of the copper layer including the (A) layer and the (B) layer.
  • the soft etching property was good, and no processing residue occurred.
  • Example 2 In Example 2, a rolled copper foil having a thickness of 12 ⁇ m was used, and the rolled copper foil was bonded to a polyimide resin substrate to obtain a copper-clad laminate. Next, this copper clad laminate was soft etched to remove a portion of the copper layer. This resulted in a copper thickness of 5 ⁇ m.
  • a platinum plating layer having a platinum adhesion amount of 75 ⁇ g / dm 2 was formed on the copper-clad laminate under the above platinum sputtering conditions.
  • ten circuits were printed by the resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
  • the closest width of the space on the resin substrate formed between the copper circuits was 3.6 times the thickness of the copper layer.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 80 ° in Example 2, and a good result was obtained.
  • the etching factor (EF) was 5.5, which was also good.
  • Example 3 In this example, a 12 ⁇ m-rolled copper alloy (Cu-0.2 wt% Cr-0.1 wt% Zr) foil in which a Ni plating layer having a Ni adhesion amount of 700 ⁇ g / dm 2 is formed in advance is bonded to a resin substrate (polyimide resin). Thus, a copper-clad laminate was produced. After forming a through hole in this copper clad laminate, a total of 26 ⁇ m of copper was plated by combining electroless plating and electroplating. The total thickness of the copper alloy and the copper plating layer was 38 ⁇ m.
  • a Pd sputter layer having a Pd adhesion amount of 700 ⁇ g / dm 2 was formed on the copper clad laminate on which the copper plating layer was formed under the above Pd sputtering conditions.
  • 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
  • the closest width of the space on the resin substrate formed between the copper circuits was 1.9 of the thickness of the copper layer.
  • the results of evaluation of 10 circuits showed little processing residue and good soft etching property ( ⁇ ).
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 81 ° in Example 3, and a good result was obtained.
  • the etching factor (EF) was 6.5, and this result was also good.
  • Example 4 In this example, a 12 ⁇ m-rolled copper alloy (Cu-0.2 wt% Cr-0.1 wt% Zr) foil in which a Ni plating layer having a Ni adhesion amount of 700 ⁇ g / dm 2 was previously formed on a resin substrate (polyimide resin) was used. A copper clad laminate was produced by bonding. After forming a through hole in this copper clad laminate, a total of 26 ⁇ m of copper was plated by combining electroless plating and electroplating. The total thickness of the copper alloy and the copper plating layer was 38 ⁇ m.
  • a Pt—Pd sputtered layer having a Pt—Pd deposition amount of 800 ⁇ g / dm 2 was formed on the copper clad laminate on which the copper plating layer was formed under the above Pt—Pd sputtering conditions.
  • 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
  • the results of evaluation of 10 circuits showed little processing residue and good soft etching property ( ⁇ ).
  • the closest width of the space on the resin substrate formed between the copper circuits was 1.9 times the thickness of the copper layer.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 82 ° in Example 4, and a good result was obtained.
  • the etching factor (EF) was 6.8, and this result was also good.
  • Example 5 In this embodiment, a resin substrate (polyimide resin) is preliminarily plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 ⁇ copper layer is formed by electroplating. A copper resin laminate was produced. Next, a 30 ⁇ m copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 ⁇ m. Further, a nickel plating layer having an adhesion amount of 1200 ⁇ g / dm 2 was formed on the copper layer under the above nickel plating conditions.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 76 ° in Example 5, and a good result was obtained.
  • the results of evaluation of 10 circuits showed little processing residue and good soft etching property ( ⁇ ).
  • the etching factor (EF) was 4, and this result was also good.
  • a resin substrate (polyimide resin) is preliminarily plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 ⁇ copper layer is formed by electroplating.
  • a copper resin laminate was produced.
  • a 30 ⁇ m copper plating layer was formed on this copper resin laminate.
  • the total copper layer thickness was 38 ⁇ m.
  • a nickel-cobalt plating layer having an adhesion amount of 1800 ⁇ g / dm 2 was formed on the copper layer under the above nickel-cobalt plating conditions.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 76 ° in Example 6, and a good result was obtained.
  • the results of evaluation of 10 circuits showed little processing residue and good soft etching property ( ⁇ ).
  • the etching factor (EF) was 4, and this result was also good.
  • Example 7 a resin substrate (polyimide resin) is preliminarily plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 ⁇ copper layer is formed by electroplating. A copper resin laminate was produced. Next, a 30 ⁇ m copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 ⁇ m. Further, a nickel plating layer having an adhesion amount of 2500 ⁇ g / dm 2 was formed on the copper layer under the above nickel plating conditions.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 77 ° in Example 7, and a good result was obtained.
  • the results of evaluation of 10 circuits were that there was little processing residue and soft etching property was good ( ⁇ ).
  • the etching factor (EF) was 4.5, and this result was also good.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, in this comparative example 1, it is 52 °, and the sagging of the circuit is observed, resulting in a failure.
  • EF etching factor
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 54 ° in the present comparative example 2, and the sagging of the circuit is observed, resulting in a failure.
  • the etching factor (EF) was 1.4 and was unsatisfactory.
  • Comparative Example 3 In Comparative Example 3, a resin substrate (polyimide resin) was previously plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer were formed by sputtering, and then an 8 ⁇ copper layer was formed by electroplating. The formed copper resin laminate was manufactured. Next, a 30 ⁇ m copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 ⁇ m.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 52 ° in the present comparative example 3, which causes sagging and becomes defective.
  • the etching factor (EF) was 1.3 and was unsatisfactory.
  • Comparative Example 4 In this comparative example 4, a resin substrate (polyimide resin) is preliminarily plasma-treated, then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 ⁇ copper layer is formed by electroplating. The formed copper resin laminate was manufactured. Next, a 30 ⁇ m copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 ⁇ m. Further, a nickel plating layer having an adhesion amount of 3200 ⁇ g / dm 2 was formed on the copper layer under the above nickel plating conditions.
  • the inclination angle of the circuit was observed by FIB-SIM. Although it can be said that the inclination angle is 63 ° or more, it is a good result, but in Comparative Example 3, it was 78 °.
  • the etching factor (EF) was 4.6, which was good. However, when an attempt was made to remove the nickel layer by soft etching, a processing residue occurred.
  • the present invention is a copper-clad laminate, and by adding a step of forming a thin layer having a slower etching rate than copper to a series of steps of forming a circuit by etching a copper foil, the intended circuit width is made more uniform.
  • This has the effect that a simple circuit can be formed, there is no processing residue due to etching, the occurrence of sagging is prevented, and the time for circuit formation by etching can be shortened.
  • This can improve the etching performance in pattern etching and prevent the occurrence of short circuits and circuit width defects, so it can be used as a copper-clad laminate (for rigid and flexible) and used for the formation of electronic circuits on printed circuit boards. It is.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

La présente invention a trait à un circuit électronique constitué de circuits de cuivre qui ont une couche (A) constituée de cuivre ou d'un alliage de cuivre, une autre couche (B) constituée de cuivre ou d'un alliage de cuivre, et encore une autre couche (C), et qui sont formés en supprimant des parties de la couche (A), de la couche (B) et de la couche (C) au moyen d'un processus d'attaque chimique. La couche (A) est formée sur une surface d'un côté ou sur des surfaces des deux côtés d'un substrat de résine. La couche (B) est formée sur une partie ou sur la totalité de la surface de la couche (A). La couche (C) est formée sur une partie ou sur la totalité de la surface de la couche (B) et fournit une vitesse d'attaque chimique plus lente que le cuivre lors d'une attaque chimique au moyen d'une solution d'attaque chimique de cuivre. Le circuit électronique est caractérisé en ce que des espaces sur le substrat de résine, qui sont formés entre les circuits de cuivre, sont ajustés de manière à avoir une largeur en fonction de l'épaisseur de cuivre correspondant à une association de la couche (A) et de la couche (B). Le circuit électronique permet de former des circuits ayant des largeurs de circuit uniformes, d'améliorer la performance d'attaque chimique dans la gravure de motifs et d'empêcher le court-circuitage et l'occurrence de largeurs de circuit inappropriées.
PCT/JP2010/059947 2009-06-18 2010-06-11 Circuit électronique, son procédé de formation et stratifié cuivré pour la formation de circuit électronique WO2010147059A1 (fr)

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WO2012128009A1 (fr) * 2011-03-18 2012-09-27 Jx日鉱日石金属株式会社 Feuille de cuivre pour cartes à câblage imprimé, et stratifié utilisant cette feuille de cuivre
JP2012186211A (ja) * 2011-03-03 2012-09-27 Jx Nippon Mining & Metals Corp プリント配線板用銅箔及びそれを用いた積層板
WO2013027444A1 (fr) * 2011-08-24 2013-02-28 Jx日鉱日石金属株式会社 Feuille de cuivre pour carte de circuits imprimés et corps stratifié l'utilisant
JP2013080735A (ja) * 2011-09-30 2013-05-02 Jx Nippon Mining & Metals Corp 生産性に優れたプリント配線板用銅箔及びそれを用いた積層板
CN106341942A (zh) * 2016-11-18 2017-01-18 东莞市五株电子科技有限公司 一种快充电池的电路板

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012186211A (ja) * 2011-03-03 2012-09-27 Jx Nippon Mining & Metals Corp プリント配線板用銅箔及びそれを用いた積層板
WO2012128009A1 (fr) * 2011-03-18 2012-09-27 Jx日鉱日石金属株式会社 Feuille de cuivre pour cartes à câblage imprimé, et stratifié utilisant cette feuille de cuivre
WO2013027444A1 (fr) * 2011-08-24 2013-02-28 Jx日鉱日石金属株式会社 Feuille de cuivre pour carte de circuits imprimés et corps stratifié l'utilisant
JP2013045881A (ja) * 2011-08-24 2013-03-04 Jx Nippon Mining & Metals Corp プリント配線板用銅箔及びそれを用いた積層板
JP2013080735A (ja) * 2011-09-30 2013-05-02 Jx Nippon Mining & Metals Corp 生産性に優れたプリント配線板用銅箔及びそれを用いた積層板
CN106341942A (zh) * 2016-11-18 2017-01-18 东莞市五株电子科技有限公司 一种快充电池的电路板

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TWI487437B (zh) 2015-06-01
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JP5676443B2 (ja) 2015-02-25
TW201116174A (en) 2011-05-01
JPWO2010147059A1 (ja) 2012-12-06

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