WO2010147059A1

WO2010147059A1 - Electronic circuit, method for forming same, and copper-clad laminate for electronic circuit formation

Info

Publication number: WO2010147059A1
Application number: PCT/JP2010/059947
Authority: WO
Inventors: 敬亮山西; 賢吾神永; 亮福地
Original assignee: Jx日鉱日石金属株式会社
Priority date: 2009-06-18
Filing date: 2010-06-11
Publication date: 2010-12-23
Also published as: JPWO2010147059A1; TWI487437B; JP5738964B2; TW201116174A; JP2014053636A; JP5676443B2

Abstract

Provided is an electronic circuit formed of copper circuits which have a layer (A) made of copper or a copper alloy, another layer (B) made of copper or a copper alloy, and still another layer (C), and which are formed by removing parts of the layer (A), the layer (B) and the layer (C) through an etching process. The layer (A) is formed on a surface in one side or surfaces in both sides of a resin substrate. The layer (B) is formed on a part or the entirety of the surface of the layer (A). The layer (C) is formed on a part or the entirety of the surface of the layer (B) and gives an etching rate slower than copper in etching with a copper etching solution. The electronic circuit is characterized in that spaces on the resin substrate, which are formed between the copper circuits, are adjusted so as to have a width according to a thickness of copper corresponding to a combination of the layer (A) and the layer (B). The electronic circuit addresses the possibility of forming circuits having uniform circuit widths, improvement of etching performance in pattern etching, and prevention of short-circuiting and occurrence of inadequate circuit widths.

Description

Electronic circuit, method for forming the same, and copper-clad laminate for forming electronic circuit

The present invention relates to an electronic circuit for forming a circuit by etching, a method for forming the same, and a copper-clad laminate for forming an electronic circuit.

Copper foil for printed circuits is widely used in electronic and electrical equipment, but this copper foil for printed circuits is generally used with a base material such as a synthetic resin board or film with or without an adhesive. Bonding under high temperature and high pressure to produce a copper clad laminate, then printing the circuit by resist coating and exposure process to form the desired circuit, and further through an etching process to remove unnecessary portions of the copper foil Further, various elements are soldered to form a printed circuit for an electro device.

Copper foils used in such printed circuits are broadly divided into electrolytic copper foils and rolled copper foils depending on the type of manufacturing method, both of which are used according to the types of printed circuit boards and quality requirements. Yes.
These copper foils have a surface to be bonded to the resin base material and a non-bonded surface, and are each subjected to a special surface treatment (treating treatment). In some cases, the copper foil used for the inner layer of the multilayer printed wiring board has a function of adhering to the resin on both sides (double treatment).

In general, electrolytic copper foil is produced by electrodepositing copper onto a rotating drum and continuously peeling it to produce a copper foil. At this time, the surface that contacts the rotating drum is a glossy surface and the opposite surface. Has many irregularities (rough surface). However, in order to further improve the adhesion to the resin substrate even on such a rough surface, it is common to deposit copper particles of about 0.2 to 3 μm.
Furthermore, a thin plating layer may be formed in order to prevent such copper particles from falling off while enhancing such unevenness. A series of these steps is called roughening treatment. Such a roughening treatment is required not only for the electrolytic copper foil but also for the rolled copper foil, and the same roughening treatment is also carried out for the rolled copper foil.

Copper-clad laminates are manufactured by hot pressing and continuous processes using the above copper foil. For example, taking the hot press method as an example, this laminated plate is produced by synthesize epoxy resin, impregnate paper substrate with phenol resin, and dry it to produce a prepreg, and further combine this prepreg and copper foil with a combination press. It is manufactured through processes such as hot pressing. In addition to this, there is a method of forming a polyimide resin layer on the copper foil by drying and solidifying the polyimide precursor solution on the copper foil. There is also a method in which after a surface treatment such as plasma treatment is applied to a resin film such as polyimide, a copper layer having a thickness equivalent to that of the copper foil is directly formed through an adhesive layer such as Ni—Cr as required. In the present invention, the above-described one in which a copper layer is formed on a resin layer will be collectively referred to as a “copper-clad laminate”.

The copper-clad laminate produced in this way is printed by a resist coating and exposure process to form the target circuit, and further undergoes an etching process to remove unnecessary portions of the copper layer. When the circuit is formed, there is a problem that the circuit does not have the width as the mask pattern previously formed on the surface.
This is because the copper circuit formed by etching is etched from the surface of the copper layer downward, that is, toward the resin layer (sagging). If a large “sag” occurs, the copper circuit may short-circuit near the resin substrate, resulting in a defective product.

Such “sag” needs to be made as small as possible. For example, in order to prevent a short circuit of the copper circuit in the vicinity of the resin substrate, it has been considered that the “sag” is reduced by extending the etching time and increasing the etching time.
However, in this case, if there is a part that has already reached the predetermined width dimension, it will be further etched, so that the circuit width will be reduced accordingly, and the uniform line width (circuit width) that is intended for circuit design will be reduced. ) Cannot be obtained, and heat is generated particularly in that portion (thinned portion), and in some cases, there is a problem of disconnection.
As the fine patterning of electronic circuits further progresses, the problem due to such etching failure still appears more strongly and still becomes a big problem in circuit formation.

In order to improve these, the present inventors have proposed a copper foil in which a metal or alloy layer (hereinafter referred to as an EF layer) having a slower etching rate than copper is formed on a copper foil on the etching surface side (Patent Literature). 1). In this case, the metal or alloy is nickel, cobalt, or an alloy thereof. By forming the metal or the alloy with a thickness sufficiently smaller than the copper circuit thickness, the formed circuit can be etched with little sagging without being too thin. is there.
That is, when designing a circuit, the etching solution penetrates from the resist coating side that becomes a mask pattern, that is, from the surface of the copper foil. Therefore, by forming an EF layer in a predetermined adhesion amount range immediately below the resist, Since the etching of the foil portion is suppressed and the etching of the other copper foil portion proceeds, the “sag” is reduced, and an effect that a circuit with a more uniform width can be formed is brought about. This result is a significant advance from the prior art.

Here are some problems that emerged during further improvements. One is the problem that the circuit shape improvement effect does not reach the copper plating layer formed on the EF layer when the copper plating step is further included on the EF layer as a pre-process of circuit formation. there were. Further, when the thickness of the copper layer is reduced by soft etching or half etching before the circuit is formed, or when the surface is roughened, the EF layer is removed, so that there is a problem that the circuit shape cannot be improved. Furthermore, there is a problem that the effect of improving the circuit shape cannot be obtained in the first place in a laminated board using a copper foil in which an EF layer is not formed or a laminated board in which a copper layer is formed on a resin film.

JP 2002-176242 A

The present invention, when performing circuit formation by etching the copper layer of the copper-clad laminate, prevents sagging due to etching, can form a uniform circuit of the desired circuit width, and further improve the etchability by pattern etching, It is an object of the present invention to obtain an electronic circuit, a method for forming the same, and a copper-clad laminate for forming an electronic circuit that can prevent the occurrence of short circuits and circuit width defects.

The inventors of the present invention added the process of forming the EF layer to a process as close as possible to the etching process for forming a circuit, that is, a process in which the EF layer formed by the subsequent processing is not removed. It was found that the problem can be solved by adjusting the etching in the thickness direction of the layer to effectively form a uniform circuit with a small circuit width.

The present invention is based on this finding,
1) A copper or copper alloy layer (A) formed on one or both sides of a resin substrate, a copper or copper alloy layer (B) formed on a part or the entire surface of the (A) layer, the (B ) A layered body composed of a layer (C) having a slower etching rate than copper with respect to a copper etchant formed on a part or the entire surface of the layer, the layer (A), the layer (B) and (C) Provided is an electronic circuit comprising a copper circuit formed by etching and removing a part of a laminated portion of a layer to the surface of a resin substrate.
Here, the (A) layer may be a copper foil provided in advance with a layer (C ′) having an etching rate slower than that of copper with respect to the copper etchant. In this case, the laminate includes the (A) layer, the ( A) A laminate composed of the (C ′) layer formed on a part or the entire surface of the layer, the (B) layer, and the (C) layer may be used.

The present invention also provides:
2) Copper or copper alloy layer (A) formed on one or both sides of a resin substrate, and an etching rate slower than copper with respect to a copper etching solution formed on a part or the entire surface of the (A) layer A layered product composed of layer (C), comprising a copper circuit formed by etching and removing a part of the layered portion of layers (A) and (C) to the surface of the resin substrate. An electronic circuit is provided.

In 1) and 2), the copper foil used for the (A) layer may be a copper foil having a layer corresponding to the (C) layer in advance, but is formed on the surface as necessary. The treatment layer (such as a rust prevention layer and a heat-resistant layer) including the (C) layer may be removed by etching or the like in the process in order to adjust the thickness of the (A) layer. In any case, the effect is not changed by forming the (C) layer before etching for circuit formation.

The present invention also provides:
3) The layer (C) having an etching rate slower than that of copper with respect to the copper etchant is any one of nickel, cobalt, iron, platinum group elements, gold, silver, a combination thereof, or a combination thereof. An electronic circuit according to any one of 1) and 2), which is an alloy containing a main component, is provided.

The present invention also provides:
4) deposition of the layer (C) is an electronic circuit according to any one of 3) to be 1), characterized in that it is ^{50μg / dm 2 ~ 3000μg / dm} 2, provided.

The present invention also provides:
5) The surface of the copper or copper alloy layer (A) opposite to the surface in contact with the resin is a surface treated by at least one of pickling treatment, soft etching, or surface roughening treatment. An electronic circuit according to any one of 1) to 4) is provided.

6) The surface of the copper or copper alloy layer (A) that is opposite to the surface in contact with the resin is a surface that has been reduced by one or more pickling, soft etching, or one or more treatments that roughen the surface. An electronic circuit according to any one of 1) to 5) is provided.

The present invention also provides:
7) A copper or copper alloy layer (A) on one or both sides of the resin substrate, then a copper or copper alloy layer (B) on a part or the entire surface of the (A) layer, and the (B ) A layer (C) having a slower etching rate than copper is formed on a part or the entire surface of the layer to produce a copper-clad laminate, and then the copper-clad laminate (( A method of forming an electronic circuit comprising a step of forming a copper circuit by etching and removing a part of the laminated portion composed of the A) layer, the (B) layer, and the (C) layer to the surface of the resin substrate I will provide a.

The present invention also provides:
8) A copper or copper alloy layer (A) is formed on one side or both sides of a resin substrate to produce a copper clad laminate, a through hole is formed in the copper clad laminate, and further on the (A) layer. After a plating layer made of a copper or copper alloy layer (B) is formed in a part or the entire surface and in the through hole, a part or the entire surface of the (B) layer is more than copper for the copper etching solution. A copper circuit is formed by forming a layer (C) having a slow etching rate, and further etching and removing a part of the laminate composed of the (A) layer, the (B) layer, and the (C) layer to the resin substrate surface. There is provided a method for forming an electronic circuit comprising the steps of forming.

The present invention also provides:
9) A layer of copper or copper alloy (A) on one or both sides of the resin substrate, and then a layer having a slower etching rate than copper with respect to the copper etchant on a part or the whole of the layer (A) ( C) is formed to produce a copper clad laminate, and then a part of the laminate composed of the (A) layer and (C) layer of this copper clad laminate is etched and removed to the resin substrate surface. There is provided a method for forming an electronic circuit, characterized by comprising a step of forming a copper circuit.

The present invention also provides:
10) The thickness of the copper or copper alloy layer (A) is adjusted by etching the copper or copper alloy layer (A) formed on one or both sides of the resin substrate, and the thickness of these layers is adjusted. Next, a layer (C) whose etching rate is slower than that of copper is formed to produce a copper-clad laminate, and then a part of the layered portion of the layers (A) and (C) is removed to the resin substrate surface by etching. Thus, a method for forming an electronic circuit is provided.

The present invention also provides:
11) A copper or copper alloy layer (A) on one or both sides of the resin substrate has a slower etching rate than copper on the copper foil surface in advance with respect to a copper etching solution as a copper foil used when forming the layer. A method for forming an electronic circuit according to any one of 7) to 10), wherein a copper foil provided with a layer (C ′) is used.

The present invention also provides:
12) The method for forming an electronic circuit according to any one of 7) to 11), wherein a heat-resistant layer and / or a rust-proof layer is formed on the (C) or (C ′) layer, provide.

The present invention also provides:
13) As a layer (C) or a layer (C ′) whose etching rate is slower than copper with respect to the copper etching solution, any one metal of nickel, cobalt, iron, platinum group element, gold, silver, or A method of forming an electronic circuit according to any one of 7) to 12), characterized by using a combination thereof or an alloy containing these as a main component.

The present invention also provides:
14) The deposition amount of the layer (C) or layer (C'), the electronic circuit according to any one of 7), characterized in that adjusting the ^{50μg / dm 2 ~ 3000μg / dm} 2 13) A forming method is provided.

The present invention also provides:
15) The electronic circuit according to any one of 7) to 14), wherein the layer (A) of copper or copper alloy is treated by one or more of pickling treatment, soft etching, or surface roughening treatment. A forming method is provided.

The present invention also provides:
16) The thickness of the copper or copper alloy layer (A layer) is reduced by pickling, soft etching, or one or more treatments for roughening the surface, according to any one of 7) to 15), A method of forming an electronic circuit is provided.

The present invention also provides:
17) A copper or copper alloy layer (A) is formed on one or both sides of a resin substrate to produce a copper clad laminate, a through hole is formed in the copper clad laminate, and further on the layer (A). After a plating layer made of a copper or copper alloy layer (B) is formed in part or the entire surface and in the through hole, etching is performed on the part or the entire surface of the (B) layer with respect to a copper etching solution rather than copper. A slow-speed layer (C) is formed, and a copper circuit is formed by etching and removing a part of the laminated portion composed of the layers (A), (B), and (C) to the resin substrate surface. A copper-clad laminate for forming an electronic circuit, wherein a copper or copper alloy layer (A) is formed on one or both sides of a resin substrate before through-hole formation, and a copper or copper alloy layer (B) formed thereafter Pickling at least one of the plating layer (through-hole plating layer) made of Providing a copper-clad laminate, for electronic circuit formation, characterized by being the thickness reduction processing by the / and soft etching.

Here, an example of etching a copper circuit as an electronic circuit on a copper clad laminate was taken as an example. However, if the purpose is to obtain a more prominent shape by etching, a copper bump that is a form of an electronic circuit It can be applied to all related technologies such as formation.

The present invention has an effect that when a circuit is formed by etching a copper layer of a copper clad laminate, a circuit having a more uniform circuit width can be formed. Further, there is an effect that the occurrence of sagging due to etching can be prevented.
This has the remarkable effect that it is possible to provide an excellent method for forming an electronic circuit capable of improving the etching property by pattern etching and preventing the occurrence of a short circuit or a defective circuit width.

It is a schematic explanatory drawing of the calculation method of an etching factor (EF).

The present invention relates to an electronic circuit and a method for forming the circuit by etching, and a copper clad laminate used in the method.
As one mode for achieving the object of the present invention, first, a copper or copper alloy layer (B) layer is formed on a copper or copper alloy layer (A) formed on a resin substrate. That is, this copper layer (B) is a copper layer newly formed on the copper-clad laminate by through-hole plating or the like. As another form, the thickness of the layer (A) is reduced by soft etching or the like.

Here, the copper or copper alloy layer (A) may be a plating layer directly formed on a resin substrate or a copper or copper alloy layer made of an adhered foil. That is, for the layer (A), a copper clad laminate in which a copper layer is directly formed after a surface treatment such as a plasma treatment on a resin film such as polyimide can be used without using a copper foil. . In this case, as in the case where the foil to be bonded is a foil not previously provided with an EF layer, the surface does not have an EF layer at this stage. The formation of the (B) layer is mainly performed by a wet plating method, but has a feature that a new copper surface is formed. Further, when the thickness of the layer (A) is reduced by soft etching, a new copper surface appears in the same manner.

Next, on this (B) layer, (A) layer reduced in thickness by soft etching, or (A) layer using a copper foil in which an EF layer has not been formed in advance, copper is added to the copper etching solution. A layer (C) layer having a slower etching rate is formed. As this (C) layer, a material having a slower etching rate than copper is selected for the copper etchant. As this material, any one metal of nickel, cobalt, iron, platinum group, gold and silver, a combination thereof, or an alloy containing these as a main component is suitable. In particular, any one metal of nickel, platinum group, and gold, or a combination thereof, or an alloy containing these as a main component is desirable.

The nickel or nickel alloy layer will be specifically described by way of example. The nickel or nickel alloy layer is located close to the resist portion on the copper foil, and the etching rate of the copper foil on the resist side is suppressed by this nickel or nickel alloy layer. Alternatively, the copper etching proceeds at a normal rate as the distance from the nickel alloy layer increases.
As a result, etching proceeds substantially vertically from the resist side of the side surface of the copper circuit toward the resin substrate side, and a rectangular copper foil circuit is formed.
The nickel or nickel alloy layer or the like mainly suppresses the occurrence of sagging and forms a circuit with a uniform circuit width.

形成 In forming a fine circuit, it is preferable to use an etching solution with a ferric chloride aqueous solution having a high etching rate. This is because there is a problem that the etching rate decreases due to circuit miniaturization. An etching solution using a ferric chloride aqueous solution is an effective means for preventing this. However, this does not prevent the use of other etchants. The etching solution can be changed as necessary.

Thereby, the space on the resin substrate formed between the copper circuits can be adjusted to a width corresponding to the thickness (T) of the copper layer including the (A) layer and the (B) layer. For example, it is possible to accurately form a circuit having a space not more than twice the thickness (T) of the copper layer, and further not more than 1.5 times. On the other hand, the circuit width can be arbitrarily designed according to the application.

クロム An organic rust preventive layer such as a chrome layer or a chromate layer and / or a silane treatment can be further formed on the (C) layer. In this case, there may be a difference in etching rate with respect to the pattern etching solution. However, by appropriately selecting this amount, the oxidation of the surface of the (C) layer can be similarly suppressed, so that the stability is further stabilized. A circuit width pattern can be formed.

Further, the (C) nickel contained in the layer, the platinum group, gold, the amount of ^{silver, 50μg / dm 2 ~ 3000μg /} dm 2, preferably from 2250μg / dm ² or less, it is desirable to further 1500μg / dm ² or less . This is an amount necessary to suppress the occurrence of sagging during circuit etching and to etch a uniform circuit.
If it is less than 50 μg / dm ² , there is no effect. Preferably it is 100 microgram / dm < ² > or more, More preferably, it is 200 microgram / dm < ² > or more.

In addition, if it is 200 microgram / dm < ² > or more, discoloration resistance also arises, and since heat resistance (discoloration resistance) improves as thickness increases, it can be said that the larger one is better. In this case, discoloration resistance means a function capable of suppressing discoloration during storage and thermal discoloration during solder mounting.
On the other hand, if the amount of C layer needs to be removed due to the post-process, the load of the C layer removal step increases during soft etching, and a processing residue may occur depending on the case. This hinders circuit design. Therefore, it is necessary to set the above range.

Moreover, in the rolled copper foil or electrolytic copper foil for electronic circuits of this invention, when providing the said chromium layer or chromate layer, chromium amount shall be 100 microgram / dm < ² > or less in conversion of metal chromium. Moreover, when forming the said silane treatment layer, it is desirable that it is 20 microgram / dm < ² > or less in conversion of silicon simple substance. This is to suppress the difference in etching rate with respect to the pattern etching solution. However, an appropriate amount is effective to prevent oxidation of the (C) layer.

Examples of typical and preferable plating conditions are shown below.
(Copper plating)
Cu: 90 g / L
H ₂ SO ₄ : 80 g / L
Cl: 60ppm
Liquid temperature: 55-57 ° C
Additives: Bis (3-sulfopropyl) disulfide disodium (CPS manufactured by RASCHIG), dibenzylamine modified product

(Nickel plating)
Ni: 10-40g / L
pH: 2.5-3.5
Temperature: normal temperature to 60 ° C
Current density Dk: 2 to 50 A / dm ²
Time: 1 to 4 seconds

(Cobalt plating)
Co: 10-40 g / L
pH: 2.5-3.5
Temperature: normal temperature to 60 ° C
Current density Dk: 2 to 50 A / dm ²
Time: 1 to 4 seconds

(Iron plating)
Fe: 20 to 25 g / L
pH: 2.5-3.5
Temperature: 50-60 ° C
Current density Dk: 4 to 10 A / dm ²
Time: 1 to 4 seconds

(Platinum group, gold, silver sputtering conditions)
Device: ULVAC MNS-6000
Degree of vacuum: 0.2Pa
Power: DC20-50W
Time: 5 to 150 seconds

(Conditions for chromate treatment)
(A) Immersion chromate treatment K ₂ Cr ₂ O ₇ (Na ₂ Cr ₂ O ₇ or CrO ₃ ): 0.1 to 5 g / liter pH: 2 to 13
Temperature: Normal temperature to 60 ° C
Time: 5 to 30 seconds (B) Electrolytic chromate treatment K ₂ Cr ₂ O ₇ (Na ₂ Cr ₂ O ₇ or CrO ₃ ): 2 to 10 g / liter NaOH or KOH: 10 to 50 g / liter pH: 7 to 13
Bath temperature: 20-80 ° C
Current density D _k : 0.05 to 5 A / dm ²
Time: 5-30 seconds Anode: Pt-Ti plate, lead plate, etc.

(Conditions for silane treatment)
Select from various series of silanes such as: Silane dissolved in alcohol is diluted with water to a predetermined concentration and applied to the copper foil surface.
Concentration: 0.01 wt% to 2 wt%
Type: Olefin silane, Epoxy silane, Acrylic silane, Amino silane, Mercapto silane

(Method of analyzing the amount of adhesion of nickel, etc.)
In order to analyze the nickel-treated surface, the opposite surface is pressed with FR-4 resin and masked. The sample is dissolved in nitric acid with a concentration of 30% until the surface treatment film is dissolved, the solution in the beaker is diluted 10 times, and quantitative analysis of nickel is performed by atomic absorption analysis.

(Chromium adhesion analysis method)
In order to analyze the treated surface, the opposite surface is pressed with FR-4 resin and masked. The sample is boiled in hydrochloric acid having a concentration of 10% for 3 minutes to dissolve the treatment layer, and the solution is quantitatively analyzed for zinc and chromium by atomic absorption analysis.

As described above, a resist pattern for forming a circuit is formed on the layer (C), and an etching solution made of a cupric chloride solution or a ferric chloride solution is used, and a portion other than the portion to which the resist pattern is attached Unnecessary portions of the laminated portion of the (A) layer, (B) layer, and (C) layer on the resin substrate are removed to the surface of the resin substrate. Next, the resist is removed, and if necessary, the remaining (C) layer is removed by soft etching. The removal of the unnecessary copper foil from the formation of the resist pattern is a commonly performed technique, and therefore, it is not necessary to explain much and is omitted.

According to the present invention, for example, it is possible to form a circuit having a space of 2 times or less, further 1.5 times or less of the thickness (T) of the copper layer including the (A) layer and the (B) layer.
The above can be realized by the combination of the (A) layer, (B) layer, and (C) layer described above, and is one of the excellent features of the present invention.

More preferable implementation conditions are as follows. After the (A) layer is formed by plating or pasting as described above, the copper foil on the exposed surface of the A layer, which is a copper foil, is protected before the (B) layer is formed. Therefore, it is desirable to remove the layer applied for this purpose by etching or the like in advance. This is to improve the subsequent plating adhesion.

When copper foil is used as the copper or copper alloy layer formed on the resin substrate, it can be similarly applied to the roughened surface (M surface) or glossy surface (S surface) of the electrolytic copper foil, but the surface to be etched is Usually use the glossy side. When using a rolled copper foil, a high purity rolled copper foil or a rolled alloy copper foil with improved strength can also be used. The present invention includes all of these copper foils.

(Etching factor measurement conditions)
The etching factor is defined as the point of intersection between the perpendicular line from the upper surface of the copper foil and the resin substrate, assuming that the circuit is etched vertically when etching is performed in a divergent manner (when sagging occurs). When the distance of the length of sagging from a is a, the ratio of this a to the thickness b of the copper foil: b / a is shown. The larger this value, the greater the inclination angle and the etching. It means that no residue remains and dripping is reduced.
An outline of the calculation method of the etching factor (EF) is shown in FIG. As shown in FIG. 1, calculation is performed with EF = b / a. By using this etching factor, it is possible to easily determine whether the etching property is good or bad.

Next, examples and comparative examples of the present invention will be described. In addition, a present Example is an example for making an understanding easy, and is not restrict | limited to the following example. That is, the present invention encompasses all aspects or modifications other than the examples shown below within the scope of the technical idea described in the present specification.
In these examples, the copper plating solution and conditions are the same as those described in Japanese Patent Application Laid-Open No. 2004-107786.

However, other copper plating solutions and conditions may be used.

Example 1
An electrolytic copper foil having a foil thickness of 18 μm was used. This electrolytic copper foil was bonded to a polyimide resin substrate to obtain a copper-clad laminate. Next, a copper plating layer of 20 μm was formed on this copper clad laminate. The copper plating was performed as described above. As a result, the total thickness of the electrolytic copper foil and the copper plating layer on the resin substrate was 38 μm.
Next, a gold sputter layer having an adhesion amount of 400 μg / dm ² was formed on the copper plating layer under the above-mentioned gold sputtering conditions, and a chromate layer was formed under the above-mentioned chromate conditions.

On the copper clad laminate on which the gold sputter layer was formed, 10 circuits were printed by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.

(Etching conditions)
Ferric chloride aqueous solution: (37 wt%, Baume degree: 40 °)
Liquid temperature: 50 ° C
Spray pressure: 0.15 MPa

(Circuit formation conditions)
Circuit pitch: 2 types, 30 μm pitch and 100 μm pitch, which are changed depending on the thickness of the copper foil. In the case of the present Example 1, since the 18-micrometer-thick copper foil was used, the sum total of the thickness of a copper layer is 38 micrometers. On the other hand, a circuit was formed under the following conditions.
(100 μm pitch circuit formation)
Resist L (line) / S (space) = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds

(Observation of etching factor)
The tilt angle of the circuit was observed by FIB-SIM (focused ion beam-scanning ion microscope). Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 79 ° in Example 1, which is a good result. The etching factor (EF) was 5, and this result was also good.

The closest width of the space on the resin substrate formed between the copper circuits was 1.8 times the thickness of the copper layer including the (A) layer and the (B) layer. The soft etching property was good, and no processing residue occurred.

(Example 2)
In Example 2, a rolled copper foil having a thickness of 12 μm was used, and the rolled copper foil was bonded to a polyimide resin substrate to obtain a copper-clad laminate. Next, this copper clad laminate was soft etched to remove a portion of the copper layer. This resulted in a copper thickness of 5 μm.

(Soft etching conditions)
A sulfuric acid-hydrogen peroxide mixed solution (165 g / L of sulfuric acid, 21 g / L of hydrogen peroxide solution) was immersed and stirred at 35 ° C. to reduce the thickness of the copper layer.

A platinum plating layer having a platinum adhesion amount of 75 μg / dm ² was formed on the copper-clad laminate under the above platinum sputtering conditions.
Next, ten circuits were printed by the resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed. The closest width of the space on the resin substrate formed between the copper circuits was 3.6 times the thickness of the copper layer.

The circuit formation conditions were a 30 μm pitch circuit, resist L / S = 25 μm / 5 μm, finished circuit top (upper) width: 10 μm, etching time: around 76 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 80 ° in Example 2, and a good result was obtained. The etching factor (EF) was 5.5, which was also good.

Etching was performed under the above conditions to form a circuit, and after removing the resin, soft etching was performed.
The results of evaluation of 10 circuits showed little processing residue and good soft etching property (◯).

(Example 3)
In this example, a 12 μm-rolled copper alloy (Cu-0.2 wt% Cr-0.1 wt% Zr) foil in which a Ni plating layer having a Ni adhesion amount of 700 μg / dm ² is formed in advance is bonded to a resin substrate (polyimide resin). Thus, a copper-clad laminate was produced. After forming a through hole in this copper clad laminate, a total of 26 μm of copper was plated by combining electroless plating and electroplating. The total thickness of the copper alloy and the copper plating layer was 38 μm.

A Pd sputter layer having a Pd adhesion amount of 700 μg / dm ² was formed on the copper clad laminate on which the copper plating layer was formed under the above Pd sputtering conditions. Next, 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed.
The closest width of the space on the resin substrate formed between the copper circuits was 1.9 of the thickness of the copper layer. The results of evaluation of 10 circuits showed little processing residue and good soft etching property (◯).

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 81 ° in Example 3, and a good result was obtained. The etching factor (EF) was 6.5, and this result was also good.

Example 4
In this example, a 12 μm-rolled copper alloy (Cu-0.2 wt% Cr-0.1 wt% Zr) foil in which a Ni plating layer having a Ni adhesion amount of 700 μg / dm ² was previously formed on a resin substrate (polyimide resin) was used. A copper clad laminate was produced by bonding. After forming a through hole in this copper clad laminate, a total of 26 μm of copper was plated by combining electroless plating and electroplating. The total thickness of the copper alloy and the copper plating layer was 38 μm.

A Pt—Pd sputtered layer having a Pt—Pd deposition amount of 800 μg / dm ² was formed on the copper clad laminate on which the copper plating layer was formed under the above Pt—Pd sputtering conditions. Next, 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed. The results of evaluation of 10 circuits showed little processing residue and good soft etching property (◯).
The closest width of the space on the resin substrate formed between the copper circuits was 1.9 times the thickness of the copper layer.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 82 ° in Example 4, and a good result was obtained.
The etching factor (EF) was 6.8, and this result was also good.

(Example 5)
In this embodiment, a resin substrate (polyimide resin) is preliminarily plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 μ copper layer is formed by electroplating. A copper resin laminate was produced. Next, a 30 μm copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 μm.
Further, a nickel plating layer having an adhesion amount of 1200 μg / dm ² was formed on the copper layer under the above nickel plating conditions.

Next, 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed. The closest width of the space on the resin substrate formed between the copper circuits was 1.7 times the thickness of the copper layer.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 76 ° in Example 5, and a good result was obtained.
The results of evaluation of 10 circuits showed little processing residue and good soft etching property (◯). The etching factor (EF) was 4, and this result was also good.

(Example 6)
In this embodiment, a resin substrate (polyimide resin) is preliminarily plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 μ copper layer is formed by electroplating. A copper resin laminate was produced. Next, a 30 μm copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 μm.
Further, a nickel-cobalt plating layer having an adhesion amount of 1800 μg / dm ² was formed on the copper layer under the above nickel-cobalt plating conditions.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 76 ° in Example 6, and a good result was obtained.
The results of evaluation of 10 circuits showed little processing residue and good soft etching property (◯). The etching factor (EF) was 4, and this result was also good.

(Example 7)
In this embodiment, a resin substrate (polyimide resin) is preliminarily plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 μ copper layer is formed by electroplating. A copper resin laminate was produced. Next, a 30 μm copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 μm.
Further, a nickel plating layer having an adhesion amount of 2500 μg / dm ² was formed on the copper layer under the above nickel plating conditions.

Next, 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed. The closest width of the space on the resin substrate formed between the copper circuits was 1.8 times the thickness of the copper layer.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 77 ° in Example 7, and a good result was obtained.
The results of evaluation of 10 circuits were that there was little processing residue and soft etching property was good (◯). The etching factor (EF) was 4.5, and this result was also good.

(Comparative Example 1)
An electrolytic copper foil having a foil thickness of 18 μm was used and adhered to a resin substrate. Next, a 20 μm copper plating layer was formed on the copper clad laminate. The copper plating conditions were the above copper plating conditions. As a result, the total thickness of the electrolytic copper foil and the copper plating layer on the resin substrate was 38 μm.

Next, 10 circuits were printed thereon by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed. The closest width of the space on the resin substrate formed between the copper circuits was 0.7 times the thickness of the copper layer.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, in this comparative example 1, it is 52 °, and the sagging of the circuit is observed, resulting in a failure.
About the above, although it was an evaluation result of 10 circuits, there were few process remainders and soft etching property was favorable, but the etching factor (EF) was 1.3 and was unsatisfactory.

(Comparative Example 2)
A rolled copper foil having a foil thickness of 12 μm was used and adhered to a resin substrate. Next, this copper clad laminate was etched to remove a part of the copper layer. This resulted in a copper thickness of 5 μm.
On this copper-clad laminate, an Ni plating layer having an adhesion amount of 25 μg / dm ² was formed under the Ni plating conditions.

Next, 10 circuits were printed by a resist coating and exposure process, and an etching process for removing unnecessary portions of the copper foil was performed. The closest width of the space on the resin substrate formed between the copper circuits was 2.6 times the thickness of the copper layer.

The circuit formation conditions were a 30 μm pitch circuit, resist L / S = 25 μm / 5 μm, finished circuit top (upper) width: 10 μm, etching time: around 76 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 54 ° in the present comparative example 2, and the sagging of the circuit is observed, resulting in a failure.
About the above, although it was an evaluation result of 10 circuits, there were few process remainders and soft etching property was favorable, but the etching factor (EF) was 1.4 and was unsatisfactory.

(Comparative Example 3)
In Comparative Example 3, a resin substrate (polyimide resin) was previously plasma-treated, and then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer were formed by sputtering, and then an 8 μ copper layer was formed by electroplating. The formed copper resin laminate was manufactured.
Next, a 30 μm copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 μm.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that a good result is obtained when the inclination angle is 63 ° or more, it is 52 ° in the present comparative example 3, which causes sagging and becomes defective.
About the above, although it was an evaluation result of 10 circuits, there were few process remainders and soft etching property was favorable, but the etching factor (EF) was 1.3 and was unsatisfactory.

(Comparative Example 4)
In this comparative example 4, a resin substrate (polyimide resin) is preliminarily plasma-treated, then a tie coat (Ni-20 wt% Cr) layer and a metal seed layer are formed by sputtering, and then an 8 μ copper layer is formed by electroplating. The formed copper resin laminate was manufactured.
Next, a 30 μm copper plating layer was formed on this copper resin laminate. As a result, the total copper layer thickness was 38 μm.
Further, a nickel plating layer having an adhesion amount of 3200 μg / dm ² was formed on the copper layer under the above nickel plating conditions.

The circuit formation conditions were a 100 μm pitch circuit, resist L / S = 73 μm / 27 μm, finished circuit top (upper) width: 15 μm, etching time: around 210 seconds.
The inclination angle of the circuit was observed by FIB-SIM. Although it can be said that the inclination angle is 63 ° or more, it is a good result, but in Comparative Example 3, it was 78 °. The etching factor (EF) was 4.6, which was good. However, when an attempt was made to remove the nickel layer by soft etching, a processing residue occurred.

The present invention is a copper-clad laminate, and by adding a step of forming a thin layer having a slower etching rate than copper to a series of steps of forming a circuit by etching a copper foil, the intended circuit width is made more uniform. This has the effect that a simple circuit can be formed, there is no processing residue due to etching, the occurrence of sagging is prevented, and the time for circuit formation by etching can be shortened. This can improve the etching performance in pattern etching and prevent the occurrence of short circuits and circuit width defects, so it can be used as a copper-clad laminate (for rigid and flexible) and used for the formation of electronic circuits on printed circuit boards. It is.

Claims

A copper or copper alloy layer (A) formed on one or both surfaces of a resin substrate, a copper or copper alloy layer (B) formed partially or entirely on the (A) layer, and the (B) layer A layered body composed of a layer (C) having an etching rate slower than that of copper with respect to a copper etching solution formed on a part or the entire surface of the upper layer, the layer (A), the layer (B) and An electronic circuit comprising a copper circuit formed by etching and removing a part of the laminated portion of the layer to the surface of the resin substrate.
Layer (A) of copper or copper alloy formed on one side or both sides of the resin substrate, a layer having a slower etching rate than copper with respect to a copper etching solution formed on a part or the whole of the layer (A) ( C), and a copper circuit formed by etching and removing a part of the layered portion of the layers (A) and (C) to the surface of the resin substrate. An electronic circuit.
The layer (C) whose etching rate is slower than copper with respect to the copper etchant is any one metal of nickel, cobalt, iron, platinum group element, gold, palladium group element, silver, or a combination thereof. 3. The electronic circuit according to claim 1, wherein the electronic circuit is an alloy containing these as main components.
The electronic circuit according to any one of claims 1 to 3, wherein the deposition amount of the layer (C) is 50 袖 g / dm 2 to 3000 袖 g / dm 2 .
The surface opposite to the surface in contact with the resin of the copper or copper alloy layer (A) is a surface treated by at least one of pickling treatment, soft etching, or surface roughening treatment. The electronic circuit according to any one of 1 to 4.
The surface of the copper or copper alloy layer (A) layer opposite to the surface in contact with the resin is a surface that is reduced by pickling, soft etching, or one or more treatments that roughen the surface. The electronic circuit according to any one of claims 1 to 5.
A copper or copper alloy layer (A) on one or both sides of the resin substrate, then a copper or copper alloy layer (B) on a part or the entire surface of the (A) layer, and the (B) layer A layer (C) having a slower etching rate than copper is formed on a part or the entire surface of the copper etchant to produce a copper-clad laminate, and then the copper-clad laminate (A) A method of forming an electronic circuit comprising a step of forming a copper circuit by etching and removing a part of a laminated portion composed of a layer, a (B) layer, and a (C) layer to the resin substrate surface.
A copper-clad laminate is formed by forming a copper or copper alloy layer (A) on one or both sides of a resin substrate, a through-hole is formed in the copper-clad laminate, and a part on the (A) layer Alternatively, after a plating layer made of a copper or copper alloy layer (B) is formed on the entire surface and in the through-hole, a part or the entire surface of the (B) layer is etched more than copper with respect to the copper etching solution. A slow layer (C) is formed, and a part of the layered portion composed of the (A) layer, the (B) layer, and the (C) layer is etched and removed to the surface of the resin substrate to form a copper circuit. A method of forming an electronic circuit comprising the steps.
A layer of copper or copper alloy (A) on one or both sides of the resin substrate, and then a layer (C) having an etching rate slower than that of copper with respect to the copper etchant on a part or the whole of the layer (A) By forming a copper-clad laminate, and then etching and removing a part of the laminate part composed of the layers (A) and (C) of the copper-clad laminate to the resin substrate surface. A method of forming an electronic circuit comprising the step of forming a copper circuit.
By etching the copper or copper alloy layer (A) formed on one side or both sides of the resin substrate, the thickness of the copper or copper alloy layer (A) is adjusted, and the thickness of these layers is adjusted, A layer (C) whose etching rate is slower than that of copper is formed to produce a copper-clad laminate, and then a part of the layered portion of the layers (A) and (C) is removed by etching to the resin substrate surface. A method of forming an electronic circuit, comprising forming a copper circuit.
As the copper foil used when the copper or copper alloy layer (A) forms a layer on one side or both sides of the resin substrate, a layer having a slower etching rate than copper on the copper foil surface in advance with respect to the copper etchant ( The method for forming an electronic circuit according to claim 7, wherein a copper foil provided with C ′) is used.
12. The method of forming an electronic circuit according to claim 7, wherein a heat-resistant layer and / or a rust-proof layer is formed on the (C) or (C ′) layer.
As a layer (C) or a layer (C ′) whose etching rate is slower than copper with respect to the copper etchant, any one metal of nickel, cobalt, iron, platinum group element, gold, palladium group element, and silver The method for forming an electronic circuit according to any one of claims 7 to 12, wherein a combination thereof or an alloy containing these as a main component is used.
The deposition amount of the layer (C) or layer (C'), the electronic circuit according to any one of claims 7 to 13, characterized in that adjusting the 50μg / dm 2 ~ 3000μg / dm 2 Forming method.
The electronic circuit according to any one of claims 7 to 14, wherein the layer (A) of copper or copper alloy is treated by one or more of pickling treatment, soft etching or surface roughening treatment. Forming method.
The thickness of the copper or copper alloy layer (A layer) is reduced by one or more of pickling treatment, soft etching, or surface roughening treatment, according to any one of claims 7 to 15. Method for forming an electronic circuit.
A copper-clad laminate is formed by forming a copper or copper alloy layer (A) on one or both sides of a resin substrate, a through-hole is formed in the copper-clad laminate, and a part on the (A) layer Or after forming the plating layer which consists of a layer (B) of copper or a copper alloy in the whole surface and a through hole, an etching rate is more than copper with respect to a copper etching liquid in part or the whole surface on this (B) layer. Electrons forming a copper circuit by forming a slow layer (C) and further etching and removing a part of the layered portion composed of the layers (A), (B) and (C) to the surface of the resin substrate A copper clad laminate for circuit formation, comprising a copper or copper alloy layer (A) on one or both sides of a resin substrate before through-hole formation, and a copper or copper alloy layer (B) formed thereafter At least one of the plating layers (through-hole plating layer) is pickled or And electronic circuit-forming copper-clad laminate characterized in that it is thickness reduction processing by soft etching.