JP2008251596A - Wiring pattern of printed wiring substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring pattern of a printed wiring substrate wherein burr can be prevented from occurring in a connection electrode formed by dicing. <P>SOLUTION: The wiring pattern of a printed wiring substrate includes a copper foil layer 22a that is formed in the specified pattern on an insulation substrate 21, a copper plating layer 22b that is formed on the copper foil layer 22a by electrolytic plating, an electroless nickel plating layer 22c that is formed on the copper plating layer 22b by electroless plating, an electroless gold plating layer 22d that is formed on the electroless nickel plating layer 22c by electroless plating, and a surface gold plating layer 22e that is formed on the electroless gold plating layer 22d by electrolytic plating. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring pattern of a printed wiring board obtained by performing plating on the upper surface of a metal layer formed in a predetermined pattern.

  Since the light source of the backlight of the mobile phone device is required to be miniaturized, for example, a surface mount type light emitting device as shown in FIG. 5 is used. The light emitting device 100 shown in FIG. 5 is a side view type LED in which a light emitting element mounted on a substrate 101 is sealed with a resin package 102. When the light emitting device 100 is soldered to the mounting substrate, the connection electrodes 103 formed on the substrate 101 are arranged so as to be perpendicular to the mounting substrate. When the light emitting device 100 is manufactured, the light emitting element is mounted on a collective substrate on which a plurality of wiring patterns are formed, and the light emitting device is cut individually.

  More specifically, when the light emitting device 100 shown in FIG. 5 is manufactured, a resin package is formed on the collective substrate 105 shown in FIGS. More specifically, a wiring pattern 108 for conducting and mounting the light emitting element 107 and a wiring pattern 110 for conducting the light emitting element 107 and the wire 109 are formed on the mounting surface 106 of the collective substrate 105. The wiring patterns 108 and 110 are formed from the mounting surface 106 to the back surface 111 opposite to the mounting surface 106, and are formed so as to straddle one substrate 101 (see FIG. 5) as a single piece. ing.

  In order to obtain the light emitting device 100 in which the collective substrate 105 on which such light emitting elements 107 are mounted is used as a single piece, the light emitting elements 107 are first sealed with a resin to form the resin package 102 and formed on the mounting surface 106 side. With the resin package 102 facing up, a back surface 111 opposite to the mounting surface 106 is attached to the adhesive sheet. Then, at the position of the cutting line C, the light emitting device 100 shown in FIG. 5 is obtained by dicing from the mounting surface 106 side and dividing each piece into pieces. That is, the wiring pattern 110 of the collective substrate 105 is cut at the cutting line C and cut off to become the connection electrode 103.

Patent Document 1 discloses a conventional surface-mount semiconductor device that cuts such a collective substrate into individual pieces and connects the connection electrodes so as to face the connection wiring pattern provided on the mounting substrate. Has been.
JP-A-10-150138

  The connection electrode 103 formed by cutting the collective substrate 105 generates burrs on the cut surface. A state in which burrs are generated in the connection electrode 103 is shown in FIG.

  As shown in FIG. 7, when the substrate 101 is cut, the burrs 112 generated on the connection electrode 103 are in the opposite direction to the substrate 101 because the substrate is cut from the mounting surface 106 side (see FIG. 6A). It occurs to face.

  In such a state, when cream solder is applied to the wiring pattern 114 of the mounting substrate 113 and the light emitting device 100 is placed thereon and reflow processing is performed, the burr 112 becomes a solder barrier and a solder fillet is formed. Hateful. Further, if the connection electrode 103 is made of, for example, copper or nickel as a base material and the surface thereof is plated with gold, the gold plating is turned over at the portion where the burr 112 is formed, and the base material is exposed. The gold plating on the surface has good wettability with respect to the solder, but the exposed nickel of the base material has low wettability, so that the solder is repelled by the nickel exposed on the burr 112 of the connection electrode 103. Fillet is hardly formed.

  In this case, not only connection failure occurs between the mounting substrate 113 and the light emitting device 100 but also the connection strength cannot be secured, and the light emitting device 100 may be peeled off.

  Accordingly, an object of the present invention is to provide a wiring pattern of a printed wiring board capable of suppressing the generation of burrs in connection electrodes formed by dicing.

  The wiring pattern of the printed wiring board of the present invention includes a metal layer formed in a predetermined pattern, an electroless plating layer formed by electroless plating on the upper surface of the metal layer, and an upper surface side of the electroless plating layer And a surface plating layer formed by electrolytic plating.

  According to the present invention, burrs that are generated when the metal layer is stretched and torn during dicing can be prevented by the electroless plating layer acting so as to suppress this stretching.

  The first invention of the present application includes a metal layer formed in a predetermined pattern, an electroless plating layer formed by electroless plating on the upper surface of the metal layer, and an electroplating treatment on the upper surface side of the electroless plating layer. And a surface plating layer formed by the method described above.

  In the wiring pattern of the present invention, an electroless plating layer formed by electroless plating is provided on the upper surface of the metal layer. The electroless plating layer has a higher Vickers hardness than the electrolytic plating layer. Therefore, burrs that are generated when the metal layer is stretched and torn during dicing can be prevented by the electroless plating layer acting to suppress this stretching.

  In the second invention of the present application, the metal layer is one or both of a copper foil layer formed in a predetermined pattern by an etching process and a copper plating layer formed by an electrolytic plating process, and the surface plating layer is The gold plating layer is formed by electrolytic plating, and the electroless plating layer is a nickel plating layer.

  The nickel plating layer formed by the electroless plating process has a Vickers hardness of 400 to 500, which is about 4 to 5 times higher than the nickel plating layer formed by the electrolytic plating process. Therefore, by making the electroless plating layer a nickel plating layer, one or both of the copper foil layer and / or the copper plating layer as a metal layer can be prevented from expanding and becoming burrs during dicing. Can do.

  The third invention of the present application is characterized in that a gold plating layer formed by an electroless plating process is provided between the electroless plating layer and the surface plating layer.

  As the wiring pattern of the present invention, by providing a gold plating layer formed by electroless plating treatment between the electroless plating layer and the surface plating layer, the electroless plating layer can be uniformly covered without unevenness. It is possible to effectively protect the electroless plating layer that prevents the generation of burrs from oxidation.

(Embodiment)
A wiring pattern according to an embodiment of the present invention will be described with reference to the drawings. First, a light emitting device wired using a wiring pattern according to an embodiment of the present invention will be described with reference to FIG. 1A and 1B are diagrams of a light-emitting device using a wiring pattern according to an embodiment of the present invention, where FIG. 1A is a perspective view, FIG. 1B is a front view, FIG. 1C is a plan view, and FIG. FIG.

  As shown in FIG. 1A to FIG. 1D, the light emitting device 10 is a side view type LED, and includes a printed wiring board 20, a light emitting element 30, and a resin package 40. The assembled substrate on which the resin package 40 that is mounted and sealing the light emitting element 30 is formed is diced into individual pieces.

  The printed wiring board 20 has a wiring pattern 22 formed on an insulating substrate 21 made of BT resin (bismaleimide triazine resin thermosetting resin). The wiring pattern 22 includes a cathode electrode 221 and an anode electrode 222 as connection electrodes formed by dicing as described above.

  The cathode electrode 221 is integrally formed with an upper surface cathode electrode portion 221x on which the light emitting element 30 is conductively mounted, a side surface cathode electrode portion 221y, and a lower surface cathode electrode portion 221z. In the anode electrode 222, an upper surface anode electrode part 222x having a bonding pad electrically connected to the light emitting element 30 by a wire 31, a side surface anode electrode part 222y, and a lower surface anode electrode part 222z are integrally formed. A resist film 23 that functions as a polarity display is provided on the back surface side opposite to the mounting surface of the printed wiring board 20.

  In the light emitting element 30, an n electrode is provided on a lower surface of a conductive substrate, an n layer, a light emitting layer, and a p layer are sequentially stacked on the upper surface of the substrate, and a p electrode is provided on the p layer.

  The resin package 40 is an epoxy resin formed by a transfer molding method or the like in order to seal the light emitting element 30 and the wire 31.

  Here, the wiring pattern 22 will be described in detail with reference to FIGS. FIG. 2 is an enlarged cross-sectional view of a part A in FIG. FIG. 3 is an enlarged cross-sectional view of a portion B in FIG.

  As shown in FIGS. 2 and 3, the upper surface anode electrode part 222x and the lower surface anode electrode part 222z of the wiring pattern 22 are a copper foil layer 22a which is a metal layer as a base, a copper plating layer 22b, and an electroless nickel plating layer. 22c, electroless gold plating layer 22d, and surface gold plating layer 22e.

  The copper foil layer 22a is a metal layer having a predetermined pattern by forming a copper foil layer having a thickness of 12 μm on the entire insulating substrate 21 and then removing unnecessary portions by etching.

  The copper plating layer 22b is a metal layer having a thickness of 10 μm to 15 μm formed on the copper foil layer 22a by electrolytic plating.

  The electroless nickel plating layer 22c is an electroless plating layer formed on the upper surface of the copper plating layer 22b to a thickness of 10 μm to 15 μm by an electroless plating process. Since the electroless nickel plating layer 22c is formed by an electroless plating process, the thickness can be formed almost uniformly, so that the copper plating layer 22b can be protected from corrosion due to oxidation.

  The electroless gold plating layer 22d is a plating layer having a thickness of 0.03 μm to 0.08 μm formed on the upper surface of the electroless nickel plating layer 22c by an electroless plating process.

  The surface gold plating layer 22e is an electrolytic plating layer formed to a thickness of 0.3 μm to 0.8 μm by electrolytic plating.

  The side surface anode electrode part 222y of the wiring pattern 22 is obtained by omitting the copper foil layer 22a from the upper surface anode electrode part 222x or the lower surface anode electrode part 222z. That is, after the copper foil layer 22a is formed on the upper surface and the lower surface of the insulating substrate 21, the copper plating layer 22b is formed to connect the copper foil layer 22a to the upper surface and the lower surface, respectively. Becomes the base metal layer. Then, the electroless nickel plating layer 22c, the electroless gold plating layer 22d, and the surface gold plating layer 22e are sequentially formed on the upper surface of the copper plating layer 22b, thereby forming the side surface anode electrode portion 222y and forming a substantially U-shaped cross section. The formed anode electrode 222 can be formed. The wiring pattern 22 shown in FIGS. 2 and 3 is the anode electrode 222, but the cathode electrode 221 is the same.

  As described above, the light emitting device 10 is formed by dicing the aggregate substrate into individual pieces. At that time, by cutting the insulating substrate 21 while the blade rotates at a high speed, a stress that extends the wiring pattern 22 acts in the rotation direction of the blade. However, since the electroless nickel plating layer 22c is formed on the upper surface of the copper plating layer 22b, the expansion of the copper plating layer 22b can be suppressed.

  This is because the electroless nickel plating layer 22c has a high hardness of 400 to 500, whereas the Vickers hardness of the copper plating layer 22b is 80 to 150.

  Here, for comparison, the configuration of a conventional wiring pattern will be described with reference to FIG. FIG. 4 is a cross-sectional view showing a conventional wiring pattern. In FIG. 4, the same components as those in FIG. FIG. 4 shows a top anode electrode part and a side anode electrode part.

  As shown in FIG. 4, the conventional wiring pattern 51 is provided with an electrolytic nickel plating layer 51x formed by electrolytic plating on the upper surface of a copper plating layer 22b formed by electrolytic plating. A surface gold plating layer 22e is formed for the purpose of protecting the electrolytic nickel plating layer 51x.

  The electrolytic nickel plating layer 51x is formed by electrolytic plating, and is nickel of the same material as the electroless nickel plating layer 22c according to the present embodiment, but has a low Vickers hardness of 100 to 250. That is, the electroless nickel plating layer 22c is formed to have a Vickers hardness of about 4 to 5 times as hard as that of the electrolytic nickel plating layer 51x.

  Therefore, in the conventional wiring pattern 51, when the conventional wiring pattern 51 is cut so as to be torn during dicing, the copper foil layer 22a and the copper plating layer 22b are expanded, and the electrolytic nickel plating layer 51x is formed. It stretches and becomes burr. Due to the occurrence of this burr, the exposed copper foil layer 22a and the copper plating layer 22b are oxidized and the solder wettability is lowered. Therefore, the copper foil layer 22a and the copper plating layer 22b having a lowered solder wettability, Originally, connection failure occurred due to the influence of the electrolytic nickel plating layer 51x having low solder wettability.

  In the wiring pattern 22 according to the present embodiment, an electroless nickel plating layer 22c whose Vickers hardness is harder than the electrolytic nickel plating layer 51x is formed on the upper surface of the copper plating layer 22b instead of the electrolytic nickel plating layer 51x. Therefore, burrs that are generated when the copper foil layer 22a and the copper plating layer 22b are stretched and torn during dicing are prevented by the electroless nickel plating layer 22c acting to suppress this expansion.

  2 and 3, since the electroless gold plating layer 22d is formed on the upper surface of the electroless nickel plating layer 22c by electroless plating, the surface of the electroless nickel plating layer 22c such as a hole is exposed. It is possible to prevent the occurrence of an opening that would cause the opening to occur. Therefore, the electroless gold plating layer 22d can effectively prevent the electroless nickel plating layer 22c that prevents the generation of burrs from being oxidized. In the wiring pattern 22 of the present embodiment, the electroless gold plating layer 22d is formed. However, an economical effect can be obtained by simplifying the manufacturing process, or the surface gold plating layer 22e which is a surface plating layer can be obtained. If it is determined that the electroless nickel plating layer 22c is sufficiently protected by being formed, the electroless gold plating layer 22d may be omitted.

  In addition, the wiring pattern 22 is formed by electrolytic plating as a surface plating layer, so that the surface gold plating layer 22e formed so as to keep the Vickers hardness low is provided. Therefore, the wire 31 (see FIG. 1) is bonded. It is possible to ensure the bonding property when performing. Therefore, the wiring pattern 22 can perform good wire bonding.

  In the present embodiment, in order to connect the copper foil layers 22a formed on the upper surface and the lower surface of the insulating substrate 21, a copper plating layer 22b serving as a base between the side cathode electrode portion 221y and the side anode electrode portion 222y. Is formed. However, if the side surface cathode electrode portion 221y and the side surface anode electrode portion 222y can be omitted by connecting the copper foil layers 22a formed on the upper surface and the lower surface of the insulating substrate 21 with through holes or the like, the copper plating layer It is also possible to omit 22b. Therefore, the electroless nickel plating layer 22c is directly formed on the upper surface of the copper foil layer 22a, which is a metal layer serving as a base, by electroless plating.

  Since the present invention can suppress the generation of burrs in the connection electrode formed by dicing, it is suitable for the wiring pattern of the printed wiring board in which the upper surface of the metal layer formed in the predetermined pattern is plated. is there.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure of the light-emitting device using the wiring pattern which concerns on embodiment of this invention, (A) is a perspective view, (B) is a front view, (C) is a top view, (D) is a rear view. Section A enlarged sectional view in FIG. Section B enlarged sectional view in FIG. Sectional view showing a conventional wiring pattern A perspective view of a conventional light emitting device It is a figure explaining the aggregate substrate of the conventional light-emitting device, (A) is the figure seen from the mounting surface side, (B) is the figure seen from the back surface side which is the other side of a mounting surface. The figure explaining the state at the time of mounting and soldering the conventional light-emitting device on a mounting substrate

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light-emitting device 20 Board | substrate 21 Insulation board | substrate 22 Wiring pattern 22a Copper foil layer 22b Copper plating layer 22c Electroless nickel plating layer 22d Electroless gold plating layer 22e Surface gold plating layer 23 Resist film 30 Light emitting element 31 Wire 40 Resin package 51 Conventional wiring pattern 51x Electrolytic nickel plating layer 221 Cathode electrode 221x Upper surface cathode electrode portion 221y Side cathode electrode portion 221z Lower surface cathode electrode portion 222 Anode electrode 222x Upper surface anode electrode portion 222y Side surface anode electrode portion 222z Lower surface anode electrode portion

Claims (3)

A metal layer formed in a predetermined pattern;
On the upper surface of the metal layer, an electroless plating layer formed by an electroless plating process,
A wiring pattern of a printed wiring board, comprising a surface plating layer formed by electrolytic plating on the upper surface side of the electroless plating layer. The metal layer is one or both of a copper foil layer formed in a predetermined pattern by an etching process or a copper plating layer formed by an electrolytic plating process,
The surface plating layer is a gold plating layer formed by an electrolytic plating process,
2. The printed wiring board wiring pattern according to claim 1, wherein the electroless plating layer is a nickel plating layer. The printed wiring board wiring pattern according to claim 1 or 2, further comprising a gold plating layer formed by an electroless plating process between the electroless plating layer and the surface plating layer.

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