JP2018067669A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can satisfactorily form a solder fret when a leadless surface mounting type semiconductor device is mounted on a circuit boards, and can easily confirm a mounting situation from the above of the semiconductor device.SOLUTION: A semiconductor device I is formed by integrally sealing a metal layer 5 mounted with a semiconductor element 7 and a plurality of electrode layers 6, 6 that are arranged on both sides in one direction of the metal layer 5, are connected to the semiconductor element 7 via wires 8, 8, and of which an end face in an opposite side to the metal layer 5 in one direction is exposed, with a resin 9. The semiconductor device I has metal plating layers 4 which are exposed from the rear faces of the metal layer 5 and the electrode layers 5 and are individually formed, and the metal plating layers 4 of the electrode layers 5 are continuously integrally formed up to the end face of the electrode layer 6.SELECTED DRAWING: Figure 15

Description

  The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and is particularly useful when applied to a case where an end surface of an electrode layer of each semiconductor device is exposed when each semiconductor device is separated from an assembly of a plurality of semiconductor devices. Is.

  In the semiconductor device II according to the prior art, in particular, the resin-sealed semiconductor device II of the leadless surface mounting method, as shown in FIG. 16, the metal layer 02 on which the semiconductor element 01 is mounted, In the figure of the metal layer 02, it has a plurality of electrode layers 04 disposed on both sides along the X direction and connected to the semiconductor element 01 by wires 03 and 03, and the whole is sealed with a resin 05. There is. This type of semiconductor device is mounted by bonding the metal layer 02 and the electrode layer 04 to the circuit board 09 with the solder 06. In such mounting, gold plating layers 07, 08, and 08 are applied to the exposed surfaces of the metal layer 02 and the electrode layer 04 in order to maintain good wettability of the solder 06. Here, the end face 04A on the opposite side of the metal layer 02 of the electrode layer 04 in the semiconductor device II is exposed.

  As described above, there is Patent Document 1 (see FIG. 7) as a known document disclosing a leadless surface mounting type resin-encapsulated semiconductor device in which the end surface 04A opposite to the metal layer 02 of the electrode layer 04 is exposed. To do.

JP 2002-09196 A

  As described above, in the leadless surface mounting type semiconductor device II in which the end surface 04A opposite to the metal layer 02 of the electrode layer 04 in the X direction is exposed, when the semiconductor device II is mounted on the circuit board 09, FIG. As shown in FIG. 16, the fillet of the solder 06 may become a recess at both end portions in the X direction of the semiconductor device II. In this manner, when the concave portion is formed on the frets of the solder 06, it is difficult to judge whether the bonding is good or not when the bonding state of the semiconductor device II to the circuit board 07 by the solder 06 is observed from above the semiconductor device II. That is, it is ideal that the fillet by the solder 06 in this case has a curved shape that gradually rises from the front end portion toward the end surface of the semiconductor device II, and in this case, good bonding by the solder 06 is ensured.

  In view of the above prior art, the present invention can satisfactorily form solder frets when a semiconductor device of a leadless surface mounting method is mounted on a circuit board, and can easily confirm the mounting state from above the semiconductor device. An object is to provide a method for manufacturing a semiconductor device and a semiconductor device.

A method of manufacturing a semiconductor device according to the first aspect of the present invention that achieves the above object
A method of manufacturing a semiconductor device by mounting a plurality of semiconductor elements on a conductive base material and obtaining a plurality of semiconductor devices in which the semiconductor elements are integrated with a resin by singulation,
A first step of forming a first resist pattern layer subjected to predetermined patterning on at least one surface side of the base material;
A second step of etching a region of the base material other than the region where the first resist pattern is formed by a predetermined depth;
A third step of applying a resist to the etching region of the base material;
A fourth step of exposing the resist to form a second resist pattern layer;
A fifth step of forming a metal plating layer on the base material where the conductive surface is exposed on the one surface side;
A sixth step of independently forming a metal layer for mounting a semiconductor element and one or more electrode layers on the base material by electrodepositing a conductive metal on the metal plating layer;
A seventh step of removing the first and second resist pattern layers;
An eighth step of mounting a semiconductor element on the metal layer and electrically connecting the semiconductor element and the electrode layers;
A ninth step of forming a semiconductor device in which a plurality of parts are integrated by sealing the entire mounting part including the semiconductor element mounted on the metal layer on the base material with a resin;
A tenth step of peeling the base material from the semiconductor device in which a plurality are integrated to expose the metal plating layer on the back surface of the semiconductor device;
The semiconductor in which the base material is peeled off with a cutting tool having a blade thickness equal to or smaller than the width of the contact portion along a cutting line passing through the contact portion between the first resist pattern layer and the base material And an eleventh step of separating the device into individual pieces.

The second aspect is
In the sixth step, the conductive metal is electrodeposited beyond the surfaces of the first and second resist pattern layers, whereby the first and the second are formed on the periphery of the upper ends of the metal layer and the electrode layer. An overhang portion is formed on the upper surface side of the second resist pattern layer.

According to a third aspect of the semiconductor device,
A metal layer on which a semiconductor element is mounted, and disposed on both sides along one direction of the metal layer and connected to the semiconductor element by a wire, and an end surface opposite to the metal layer along the one direction is exposed. A plurality of electrode layers integrally sealed with a resin,
The metal plating layer is formed separately and exposed from the back surfaces of the metal layer and the electrode layer, and the metal plating layer of the electrode layer is continuously and integrally formed up to the end surface of the electrode layer. It is characterized by.

  According to the present invention, when the metal plating layer applied to the back surface of the electrode layer is continuously and integrally formed up to the end surface of the electrode layer, and the semiconductor device is soldered to the circuit board, the end surface of the semiconductor device is A curved solder fillet that rises continuously from the adjacent tip to the end face is well formed. As a result, the formation state of the fret can be easily visually recognized from above the semiconductor device, and the quality of solder bonding can be easily and reliably inspected.

It is a schematic diagram which shows the 1st process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 2nd process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 3rd process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 4th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 5th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 6th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 7th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 8th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 9th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 10th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 11th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the 12th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram which shows the state which looked at FIG. 12 from the back surface side. It is a schematic diagram which shows the 13th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 1 is a schematic view showing a single semiconductor device according to an embodiment of the present invention. FIG. It is a schematic diagram which divides the semiconductor device which concerns on a prior art into pieces, and shows the one.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  1 to 14 are schematic views showing each step of this embodiment. As shown in these drawings, the semiconductor device according to this embodiment is manufactured through the following steps. Details will be sequentially described below.

<First step>
As shown in FIG. 1, a resist 2 </ b> A is applied to both surfaces of a flat base material 1. Here, the base material 1 is not particularly limited as long as it is a conductive material, but SUS is preferable. The resist 2A may be applied to at least one surface side (the upper surface side in the drawing) of the base material 1. However, when it is applied to both the upper and lower surfaces, the resist 2A on the other surface side (the lower surface side in the figure) can be used as a protective layer of the base material 1 in a later step (this will be described in detail later). .

<Second step>
As shown in FIG. 2, the resist 2A is subjected to predetermined patterning and exposed to form a first resist pattern layer 2B having a predetermined pattern. In this embodiment, the resist 2A is applied also to the lower surface side of the base material 1, but the resist 2A on the lower surface side functions as a protective layer of the base material 1 by being cured by the exposure.

<Third step>
As shown in FIG. 3, a region (region where the base material 1 is exposed) other than the region where the first resist pattern layer 2B is formed on the upper surface side of the base material 1 is etched by a predetermined depth. As a result, the portion where the first resist pattern layer 2B is formed on the surface side of the base material 1 remains as the convex portion 1A. Thus, a region for forming one semiconductor device I (see FIG. 15) is formed in the region between the convex portions 1A adjacent in the X direction by singulation. In addition, the two-dot chain line of FIG. 3 has shown the surface position of the base material 1 before an etching. Here, as the etching method of the base material 1, two types of methods, a physical etching method and a chemical etching method, are known, and any of them may be applied. In the case of the chemical etching method, the resist 2A on the back side serves as a protective layer for the base material 1.

<4th process>
As shown in FIG. 4, a resist 3A is applied to the etching region of the base material 1 so as to be flush with the surface of the first resist pattern layer 2B. Thus, it is not essential to apply the resist 3A flush. However, when the resist 3A is applied flush as in the present embodiment, the metal layer 5 and electrodes to be formed in the subsequent process (seventh process) are used. The height position of the layer 6 can be easily aligned. In particular, when the overhang portions 5A and 6A are formed as in the seventh step of this embodiment, the height positions of the overhang portions 5A and 6A can be easily aligned.

<Fifth step>
As shown in FIG. 5, the resist 3A is exposed to form a second resist pattern layer 3B. Therefore, a region between the resist pattern layers 3B adjacent in the X direction is a region for forming a metal layer 5 (see, for example, FIG. 7) described later. In addition, a region between the convex portion 1A adjacent in the X direction and the resist pattern layer 3B adjacent thereto is a formation region of the electrode layer 6 (see, for example, FIG. 7).

<Sixth step>
As shown in FIG. 6, on one side (front side) of the base material 1, metal is applied to the base material 1 where the conductive surface is exposed without being covered by the first resist pattern layer 2B and the second resist pattern layer 3B. A plating layer 4 is formed. Here, the metal plating layer 4 is not particularly limited as long as it is a metal plating layer having high wettability with the solder, but a gold plating layer having high corrosion resistance and being chemically stable is optimal.

<Seventh step>
As shown in FIG. 7, by depositing a conductive metal on the metal plating layer 4, a metal layer 5 for mounting a semiconductor element and one or more electrode layers 6 are independently formed on the base material 1. Form. The conductive metal in this embodiment is nickel. This is because when gold is used for the metal plating layer 4 in the previous step, nickel has the best adhesion to the gold plating layer. In addition, as the conductive metal for electrodeposition, nickel cobalt alloy, copper and the like can be considered.

  In the electrodeposition step in this embodiment, the first resist is formed on the periphery of the upper end portions of the metal layer 5 and the electrode layer 6 by electrodepositing a conductive metal beyond the surfaces of the first and second resist pattern layers 2B and 3B. An overhang portion 5A projecting on the upper surface side of the pattern layer 2B was formed, and an overhang portion 6A projecting on the upper surface side of the second resist pattern layer 3B was formed. Thus, it is not essential to form the overhang portions 5A and 6A. However, in the resin sealing step (see FIG. 11) after removing the first and second resist pattern layers 2B and 3B by forming the overhang portions 5A and 6A, the resin 9 (see FIG. 11; hereinafter) Since each of the overhang portions 5A and 6A has a shape that bites into the same), the base material 1 is pulled from the sealing portion side by the resin 9 by a peeling operation (see FIG. 12) that is a subsequent process due to the biting effect. When stripping and removing, the metal layer 5 and the electrode layer 6 do not stick to and separate from the base material side, but reliably remain on the sealing portion side by the resin 9, effectively preventing misalignment, chipping, etc. The reliability of the device I (see FIG. 15; the same applies hereinafter) can be improved. Further, the boundary between the metal layer 5 and the electrode layer 6 and the resin 9 from the back surface side of the semiconductor device I due to the shape of the overhang portions 5A and 6A that are formed over the entire periphery of the upper edge of the metal layer 5 and the electrode layer 6. It is possible to prevent moisture or the like entering through the portion from entering upward and to have excellent water resistance.

<Eighth process>
As shown in FIG. 8, the first and second resist pattern layers 2B and 3B are peeled and removed. Here, all the resist 2A applied to the back surface of the base material 1 is also removed.

<9th process>
As shown in FIG. 9, a semiconductor element 7 is mounted on and bonded to the metal layer 5.

<Tenth step>
As shown in FIG. 10, an electrode (not shown) of the semiconductor element 7 and each electrode layer 6 are electrically connected by wires 8 and 8. A wire bonding method can be suitably applied to the connection of the wires 8 and 8.

<Eleventh step>
As shown in FIG. 11, the entire mounting portion including the semiconductor element 7 mounted on the metal layer 5 on the base material 1 is sealed with a resin 9 to form a semiconductor device I in which a plurality are integrated. .

<Twelfth step>
As shown in FIG. 12, the base material 1 is peeled from the semiconductor device I in which a plurality is integrated, and the metal plating layer 4 on the back surface of the semiconductor device I is exposed. As a result of the peeling of the base material 1 in this step, a space 1C serving as a recess is formed at the position of the convex portion 1A (for example, see FIG. 11) of the base material 1.

  FIG. 13 is a schematic view showing a plurality of integrated semiconductor devices I before singulation, as viewed from the back surface in a state where the process is completed. As shown in the figure, the metal layer 5 and the electrode layer 6 are formed on the metal plating layer 4 having the same shape as these, and a space 1C shown as a halftone dot region in the figure is formed. In addition, a region A surrounded by a thick solid line in the figure is one semiconductor device I formed by being separated into pieces in the next process. Such singulation is performed by cutting along predetermined cutting lines in the X direction and the Y direction. Here, the center lines of the cutting lines in the Y direction at the time of singulation are shown as L1 and L2 in the figure, and the center lines of the cutting lines in the X direction are shown as L3 and L4 in the figure.

<13th process>
As shown in FIG. 14, the blade thickness is equal to the width of the contact portion along the cutting line passing through the center of the contact portion between the first resist pattern layer 2B (for example, see FIG. 7) and the base material 1 or By cutting along the cutting lines L1 to L4 shown in FIG. 12 with a cutting tool 10 smaller than the width, a plurality of semiconductor devices I from which the base material 1 has been peeled are separated. A dicing saw is optimal as the cutting tool 10 in this case. Thus, a plurality of individual semiconductor devices I are obtained. In this semiconductor device I, the metal plating 4 is also formed on the end face of the electrode layer 6. The semiconductor device I formed in this way will be described in more detail with reference to FIG.

  FIG. 15 is a schematic diagram showing a single semiconductor device I according to an embodiment of the present invention. As shown in the figure, the semiconductor device I is formed by integrally sealing a metal layer 5 on which a semiconductor element 7 is mounted and a plurality of electrode layers 6 with a resin 9. Here, the electrode layer 6 is disposed on both sides of the metal layer 5 along the X direction and is connected to the semiconductor element 7 by the wires 8 and 8 and the end surface opposite to the metal layer 5 along the X direction is exposed. Yes. Further, the metal plating layer 4 is individually formed on the back surfaces of the metal layer 5 and the electrode layer 6, and in particular, the metal plating layer 4 of the electrode layer 6 is integrally formed continuously to the end surface of the electrode layer 6. .

  Thus, when the semiconductor device I is mounted on the circuit board 11 by bonding with the solder 12, the metal plating layer 4 applied to the back surface of the electrode layer 6 is continuously and integrally formed up to the end surface of the electrode layer 6. Therefore, the fillet of the curved solder 12 that rises continuously from the tip end adjacent to the end face of the semiconductor device I toward the end face is well formed. As a result, the formation state of the fret can be easily visually recognized from above the semiconductor device I, and the quality of the solder joint can be easily and reliably inspected.

  The present invention can be effectively used in the industrial field of manufacturing and selling semiconductor devices.

I Semiconductor device 1 Base material 1A Convex part 2A, 3A Resist
2B First resist layer 3B Second resist layer 4 Metal plating layer 5 Metal layers 5A, 6A Overhang portion
6 Electrode layer 7 Semiconductor element 8 Wire 9 Resin
10 Cutting tool 11 Circuit board 12 Solder

Claims (3)

A method of manufacturing a semiconductor device by mounting a plurality of semiconductor elements on a conductive base material and obtaining a plurality of semiconductor devices in which the semiconductor elements are integrated with a resin by singulation,
A first step of forming a first resist pattern layer subjected to predetermined patterning on at least one surface side of the base material;
A second step of etching a region of the base material other than the region where the first resist pattern is formed by a predetermined depth;
A third step of applying a resist to the etching region of the base material;
A fourth step of exposing the resist to form a second resist pattern layer;
A fifth step of forming a metal plating layer on the base material where the conductive surface is exposed on the one surface side;
A sixth step of independently forming a metal layer for mounting a semiconductor element and one or more electrode layers on the base material by electrodepositing a conductive metal on the metal plating layer;
A seventh step of removing the first and second resist pattern layers;
An eighth step of mounting a semiconductor element on the metal layer and electrically connecting the semiconductor element and the electrode layers;
A ninth step of forming a semiconductor device in which a plurality of parts are integrated by sealing the entire mounting part including the semiconductor element mounted on the metal layer on the base material with a resin;
A tenth step of peeling the base material from the semiconductor device in which a plurality are integrated to expose the metal plating layer on the back surface of the semiconductor device;
The semiconductor in which the base material is peeled off with a cutting tool having a blade thickness equal to or smaller than the width of the contact portion along a cutting line passing through the contact portion between the first resist pattern layer and the base material And an eleventh step of dividing the device into individual pieces. In the manufacturing method of the semiconductor device according to claim 1,
In the sixth step, the conductive metal is electrodeposited beyond the surfaces of the first and second resist pattern layers, whereby the first and the second are formed on the periphery of the upper ends of the metal layer and the electrode layer. A method of manufacturing a semiconductor device, comprising: forming an overhang portion projecting on an upper surface side of the resist pattern layer 2. A metal layer on which a semiconductor element is mounted, and disposed on both sides along one direction of the metal layer and connected to the semiconductor element by a wire, and an end surface opposite to the metal layer along the one direction is exposed. A plurality of electrode layers integrally sealed with a resin,
The metal plating layer is formed separately and exposed from the back surfaces of the metal layer and the electrode layer, and the metal plating layer of the electrode layer is continuously and integrally formed up to the end surface of the electrode layer. A semiconductor device characterized by that.

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