JP6867671B2 - Manufacturing method of semiconductor devices and semiconductor devices - Google Patents

Manufacturing method of semiconductor devices and semiconductor devices Download PDF

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JP6867671B2
JP6867671B2 JP2016206411A JP2016206411A JP6867671B2 JP 6867671 B2 JP6867671 B2 JP 6867671B2 JP 2016206411 A JP2016206411 A JP 2016206411A JP 2016206411 A JP2016206411 A JP 2016206411A JP 6867671 B2 JP6867671 B2 JP 6867671B2
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木村　浩
浩 木村
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トレックス・セミコンダクター株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明は半導体装置の製造方法および半導体装置に関し、特に複数の半導体装置の集合体から各半導体装置を個片化した場合に各半導体装置の電極層の端面が露出する場合に適用して有用なものである。 The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and is particularly useful when applied to a case where the end face of the electrode layer of each semiconductor device is exposed when each semiconductor device is separated from an aggregate of a plurality of semiconductor devices. It is a thing.

従来技術に係る半導体装置II、特に、リードレス表面実装方式の樹脂封止された半導体装置IIの中には、図１６に示すように、半導体素子０１を搭載している金属層０２と、該金属層０２の図中、Ｘ方向に沿う両側に配設され半導体素子０１とワイヤ０３，０３で接続される複数の電極層０４とを有し、全体を樹脂０５で封止して形成したものがある。この種の半導体装置では、金属層０２および電極層０４を半田０６により回路基板０９に接合することにより実装される。かかる実装において、半田０６の濡れ性を良好に保持するため、金属層０２および電極層０４の露出面には金メッキ層０７，０８，０８が施される。 ここで、半導体装置IIにおける電極層０４の金属層０２と反対側の端面０４Ａは露出している。 As shown in FIG. 16, the semiconductor device II according to the prior art, particularly the resin-sealed semiconductor device II of the leadless surface mounting method, includes a metal layer 02 on which the semiconductor element 01 is mounted and the metal layer 02. In the drawing of the metal layer 02, a semiconductor element 01 and a plurality of electrode layers 04 connected by wires 03 and 03 are provided on both sides along the X direction, and the entire metal layer 02 is sealed with a resin 05. There is. In this type of semiconductor device, the metal layer 02 and the electrode layer 04 are mounted by joining them to the circuit board 09 with solder 06. In such mounting, in order to maintain the wettability of the solder 06 well, gold-plated layers 07, 08, 08 are applied to the exposed surfaces of the metal layer 02 and the electrode layer 04. Here, the end surface 04A of the electrode layer 04 on the opposite side of the metal layer 02 of the semiconductor device II is exposed.

上述の如く電極層０４の金属層０２と反対側の端面０４Ａが露出しているリードレス表面実装方式の樹脂封止された半導体装置を開示する公知文献として特許文献１（図７参照）が存在する。 As described above, Patent Document 1 (see FIG. 7) exists as a known document that discloses a resin-sealed semiconductor device of a leadless surface mount system in which the end surface 04A on the side opposite to the metal layer 02 of the electrode layer 04 is exposed. To do.

特開２００２−０９１９６号公報Japanese Unexamined Patent Publication No. 2002-09196

上述の如くＸ方向に関して電極層０４の金属層０２と反対側の端面０４Ａが露出しているリードレス表面実装方式の半導体装置IIにおいては、半導体装置IIを回路基板０９上に実装した場合、図１６に示すように、半田０６のフィレットが半導体装置IIのＸ方向に関する両端部では凹部となってしまう場合がある。このように半田０６のフレットに凹部が形成された場合、半導体装置IIの回路基板０７に対する半田０６による接合状態を半導体装置IIの上方から観察した場合、その接合の良否の判断が困難になる。すなわち、この場合の半田０６によるフィレットは先端部から半導体装置IIの端面に向かって徐々に立ち上る曲線形状となるのが理想であり、この場合に半田０６による良好な接合が担保される。 As described above, in the leadless surface mount type semiconductor device II in which the end surface 04A on the side opposite to the metal layer 02 of the electrode layer 04 is exposed in the X direction, when the semiconductor device II is mounted on the circuit board 09, the figure is shown in FIG. As shown in 16, the fillets of the solder 06 may become recesses at both ends of the semiconductor device II in the X direction. When the recess is formed in the fret of the solder 06 in this way, when the bonding state of the semiconductor device II with respect to the circuit board 07 by the solder 06 is observed from above the semiconductor device II, it becomes difficult to judge the quality of the bonding. That is, in this case, the fillet made of solder 06 ideally has a curved shape that gradually rises from the tip end toward the end face of the semiconductor device II, and in this case, good bonding with solder 06 is guaranteed.

本発明は、上記従来技術に鑑み、リードレス表面実装方式の半導体装置を回路基板に実装する際の半田フレットを良好に形成することができ、半導体装置の上方から実装状況を容易に確認し得る半導体装置の製造方法および半導体装置を提供することを目的とする。 In view of the above-mentioned prior art, the present invention can satisfactorily form solder frets when mounting a leadless surface mount semiconductor device on a circuit board, and the mounting status can be easily confirmed from above the semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device.

上記目的を達成する本発明の第１の態様に係る半導体装置の製造方法は、
導電性を有する母材上に複数の半導体素子を搭載するとともに、前記半導体素子を樹脂で一体化した複数の半導体装置を個片化により得る半導体装置の製造方法であって、
前記母材の少なくとも一面側に第１のレジストを塗布する第１の工程と、
前記第１のレジストに所定のパターニングを施した第1のレジストパターン層を形成する第２の工程と、
前記母材のうち前記第１のレジストパターン層が形成された領域以外の領域を所定の深さだけエッチングする第３の工程と、
前記母材のエッチング領域に第２のレジストを塗布する第４の工程と、
前記第２のレジストを露光して第2のレジストパターン層を形成する第５の工程と、
前記一面側において導電面が露出している前記母材に金属メッキ層を形成する第６の工程と、
前記金属メッキ層に重ねて導電性金属を電着することで、前記母材上に半導体素子搭載用の金属層と1以上の電極層とをそれぞれ独立して形成する第７の工程と、
前記第１および第2のレジストパターン層を除去する第８の工程と、
前記金属層に半導体素子を搭載するとともに、前記半導体素子と前記各電極層とを電気的に接続する第９の工程と、
前記母材上において前記金属層に載置された前記半導体素子を含む搭載部分の全体を樹脂で封止して複数個が一体となった半導体装置を形成する第１０の工程と、
複数個が一体となった前記半導体装置から前記母材を剥離して前記半導体装置の裏面の前記金属メッキ層を露出させる第１１の工程と、
前記第1のレジストパターン層と前記母材との当接部を通る切断線に沿い刃厚が前記当接部の幅と同等もしくは前記幅よりも小さい切断工具で前記母材を剥離した前記半導体装置を個片化する第１２の工程とを有することを特徴とする。 The method for manufacturing a semiconductor device according to the first aspect of the present invention that achieves the above object is
A method for manufacturing a semiconductor device in which a plurality of semiconductor elements are mounted on a conductive base material and a plurality of semiconductor devices in which the semiconductor elements are integrated with a resin are obtained by individualization.
The first step of applying the first resist to at least one surface side of the base material, and
A second step of forming a first resist pattern layer in which a predetermined patterning is applied to the first resist, and
A third step of etching a region of the base material other than the region where the first resist pattern layer is formed by a predetermined depth, and
A fourth step of applying the second resist to the etching region of the base material, and
A fifth step of exposing the second resist to form a second resist pattern layer, and
A sixth step of forming a metal plating layer on the base material whose conductive surface is exposed on one surface side, and
A seventh step of independently forming a metal layer for mounting a semiconductor element and one or more electrode layers on the base material by electrodepositing a conductive metal on the metal plating layer.
The eighth step of removing the first and second resist pattern layers and
A ninth step of mounting the semiconductor element on the metal layer and electrically connecting the semiconductor element and each of the electrode layers.
A tenth step of forming a semiconductor device in which a plurality of mounting portions are integrally formed by sealing the entire mounting portion including the semiconductor element mounted on the metal layer on the base material with a resin.
An eleventh step of peeling the base material from the semiconductor device in which a plurality of the devices are integrated to expose the metal plating layer on the back surface of the semiconductor device.
The semiconductor whose base material is peeled off with a cutting tool whose blade thickness is equal to or smaller than the width of the contact portion along a cutting line passing through the contact portion between the first resist pattern layer and the base material. It is characterized by having a twelfth step of disassembling the device.

第２の態様は、
前記第７の工程では、前記第１および第２のレジストパターン層の表面を超えて前記導電性金属を電着させることにより前記金属層および前記電極層の上端部周縁に前記第１および前記第２のレジストパターン層の上面側に張り出すオーバーハング部を形成することを特徴とする。 The second aspect is
In the seventh step , the conductive metal is electrodeposited over the surfaces of the first and second resist pattern layers so that the first and first edges of the upper end of the metal layer and the electrode layer are electrodeposited. It is characterized in that an overhang portion overhanging the upper surface side of the resist pattern layer of No. 2 is formed.

本発明によれば、電極層の裏面に施した金属メッキ層が前記電極層の端面にまで連続して一体的に形成され、当該半導体装置を回路基板に半田接合した場合、半導体装置の端面に隣接する先端部から前記端面に向けて連続的に立ち上がる曲線状の半田のフィレットが良好に形成される。この結果、半導体装置の上方から前記フレットの形成状態を容易に視認でき、半田接合の良否を容易かつ確実に検査することができる。 According to the present invention, when the metal plating layer applied to the back surface of the electrode layer is continuously and integrally formed up to the end face of the electrode layer and the semiconductor device is solder-bonded to the circuit board, the end face of the semiconductor device is formed. A curved solder fillet that continuously rises from an adjacent tip end toward the end face is well formed. As a result, the formed state of the frets can be easily visually recognized from above the semiconductor device, and the quality of the solder joint can be easily and surely inspected.

本発明の実施の形態に係る半導体装置の製造方法における第１の工程を示す模式図である。It is a schematic diagram which shows the 1st step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第２の工程を示す模式図である。It is a schematic diagram which shows the 2nd step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第３の工程を示す模式図である。It is a schematic diagram which shows the 3rd step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第４の工程を示す模式図である。It is a schematic diagram which shows the 4th step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第５の工程を示す模式図である。It is a schematic diagram which shows the 5th step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第６の工程を示す模式図である。It is a schematic diagram which shows the 6th step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第７の工程を示す模式図である。It is a schematic diagram which shows the 7th step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第８の工程を示す模式図である。It is a schematic diagram which shows the 8th step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第９の工程を示す模式図である。It is a schematic diagram which shows the 9th process in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第１０の工程を示す模式図である。It is a schematic diagram which shows the tenth step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第１１の工程を示す模式図である。It is a schematic diagram which shows the eleventh step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法における第１２の工程を示す模式図である。It is a schematic diagram which shows the twelfth step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 図１２を裏面側から見た状態で示す模式図である。FIG. 12 is a schematic view showing a state in which FIG. 12 is viewed from the back surface side. 本発明の実施の形態に係る半導体装置の製造方法における第１３の工程を示す模式図である。It is a schematic diagram which shows the thirteenth step in the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置を個片化してその一個を示す模式図である。It is a schematic diagram which shows one piece of the semiconductor device which concerns on embodiment of this invention. 従来技術に係る半導体装置を個片化してその一個を示す模式図である。It is a schematic diagram which shows one piece of the semiconductor device which concerns on the prior art in piece piece.

以下、本発明の実施の形態を図面に基づき詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図１〜図１４は本実施形態の各工程を示す模式図である。これらの図に示すように、本実施形態に係る半導体装置は、次のような各工程を経て製造される。以下、順次詳細に説明する。 1 to 14 are schematic views showing each process of the present embodiment. As shown in these figures, the semiconductor device according to the present embodiment is manufactured through the following steps. Hereinafter, detailed description will be given in order.

＜第１の工程＞
図１に示すように、平板状の母材１の両面にレジスト２Ａを塗布する。ここで、母材１は導電性を有する材料であれば特に限定はないが、ＳＵＳが好適である。また、レジスト２Ａは母材１の少なくとも一面側（図中、上面側）に塗布すれば良い。ただ、上下両面に塗布した場合には、他面側（図中、下面側）のレジスト２Ａを後工程における母材１の保護層とすることができる（この点に関しては、後に詳述する）。 <First step>
As shown in FIG. 1, the resist 2A is applied to both surfaces of the flat plate-shaped base material 1. Here, the base material 1 is not particularly limited as long as it is a conductive material, but SUS is preferable. Further, the resist 2A may be applied to at least one surface side (upper surface side in the drawing) of the base material 1. However, when applied to both the upper and lower surfaces, the resist 2A on the other surface side (lower surface side in the drawing) can be used as a protective layer for the base material 1 in the subsequent process (this point will be described in detail later). ..

＜第２の工程＞
図２に示すように、レジスト２Ａに所定のパターニングを施して露光することにより所定のパターンの第１のレジストパターン層２Ｂを形成する。本形態では、母材１の下面側にもレジスト２Ａを塗布しているが、下面側のレジスト２Ａは前記露光により硬化することで母材１の保護層として機能する。 <Second step>
As shown in FIG. 2, the resist 2A is subjected to a predetermined patterning and exposed to form a first resist pattern layer 2B having a predetermined pattern. In this embodiment, the resist 2A is also applied to the lower surface side of the base material 1, but the resist 2A on the lower surface side functions as a protective layer of the base material 1 by being cured by the exposure.

＜第３の工程＞
図３に示すように、母材１の上面側のうち第１のレジストパターン層２Ｂが形成された領域以外の領域（母材１が露出している領域）を所定の深さだけエッチングする。この結果、母材１の表面側のうち第１のレジストパターン層２Ｂが形成された部分が凸部１Ａとして残る。かくして、Ｘ方向で隣接する凸部１Ａ間の領域で、後述する個片化による一個の半導体装置Ｉ（図１５参照）の形成領域が形成される。なお、図３の二点鎖線はエッチング前の母材１の表面位置を示している。ここで、母材１のエッチング方法には、物理的エッチング法および化学的エッチング法の２種類の方法が知られているが、いずれを適用しても良い。化学的エッチング法の場合には、裏面側のレジスト２Ａが母材１の保護層となる。 <Third step>
As shown in FIG. 3, a region other than the region where the first resist pattern layer 2B is formed (the region where the base metal 1 is exposed) on the upper surface side of the base metal 1 is etched by a predetermined depth. As a result, the portion of the surface side of the base material 1 on which the first resist pattern layer 2B is formed remains as the convex portion 1A. Thus, in the region between the convex portions 1A adjacent to each other in the X direction, a region for forming one semiconductor device I (see FIG. 15) by individualization, which will be described later, is formed. The alternate long and short dash line in FIG. 3 indicates the surface position of the base material 1 before etching. Here, two types of etching methods for the base metal 1 are known, a physical etching method and a chemical etching method, and any of them may be applied. In the case of the chemical etching method, the resist 2A on the back surface side serves as a protective layer for the base material 1.

＜第４の工程＞
図４に示すように、第１のレジストパターン層２Ｂの表面と面一になるように母材１のエッチング領域にレジスト３Ａを塗布する。このようにレジスト３Ａを面一に塗布することは必須ではないが、本形態の如くレジスト３Ａを面一に塗布した場合には、後工程（第７の工程）において形成する金属層５および電極層６の高さ位置を容易に揃えることができる。特に本形態の第７の工程の如く、オーバーハング部５Ａ，６Ａを形成する場合には各オーバーハング部５Ａ，６Ａの高さ位置を容易に揃えることができる。 <Fourth step>
As shown in FIG. 4, the resist 3A is applied to the etching region of the base material 1 so as to be flush with the surface of the first resist pattern layer 2B. It is not essential to apply the resist 3A flush with each other in this way, but when the resist 3A is applied flush with each other as in this embodiment, the metal layer 5 and the electrode formed in the subsequent step (seventh step) are formed. The height positions of the layers 6 can be easily aligned. In particular, when the overhang portions 5A and 6A are formed as in the seventh step of the present embodiment, the height positions of the overhang portions 5A and 6A can be easily aligned.

＜第５の工程＞
図５に示すように、レジスト３Ａを露光して第2のレジストパターン層３Ｂを形成する。そこで、Ｘ方向で隣接するレジストパターン層３Ｂ間の領域が、後述する金属層５（例えば図７参照）の形成領域となる。また、Ｘ方向で隣接する凸部１Ａとこれに隣接するレジストパターン層３Ｂ間の領域が、電極層６（例えば図７参照）の形成領域となる。 <Fifth step>
As shown in FIG. 5, the resist 3A is exposed to form the second resist pattern layer 3B. Therefore, the region between the resist pattern layers 3B adjacent to each other in the X direction becomes the formation region of the metal layer 5 (see, for example, FIG. 7) described later. Further, the region between the convex portion 1A adjacent in the X direction and the resist pattern layer 3B adjacent thereto is the formation region of the electrode layer 6 (see, for example, FIG. 7).

＜第６の工程＞
図６に示すように、母材１の一面側（表面側）において第１のレジストパターン層２Ｂおよび第２のレジストパターン層３Ｂに覆われることなく導電面が露出している母材１に金属メッキ層４を形成する。ここで、金属メッキ層４としては半田との間で大きな濡れ性を有する金属のメッキ層であれば、特別な限定はないが、耐食性が大きく化学的に安定な金メッキ層が最適である。 <Sixth step>
As shown in FIG. 6, a metal is provided on the base material 1 whose conductive surface is exposed without being covered by the first resist pattern layer 2B and the second resist pattern layer 3B on one surface side (surface side) of the base material 1. The plating layer 4 is formed. Here, the metal plating layer 4 is not particularly limited as long as it is a metal plating layer having a large wettability with the solder, but a gold plating layer having a large corrosion resistance and being chemically stable is optimal.

＜第７の工程＞
図７に示すように、金属メッキ層４に重ねて導電性金属を電着することで、母材１上に半導体素子搭載用の金属層５と1以上の電極層６とをそれぞれ独立して形成する。本形態における導電性金属としてはニッケルとした。前工程において金属メッキ層４に金を用いた場合、ニッケルが金メッキ層との密着性が最も良好であるからである。また、電着を行う導電性金属としては他にもニッケルコバルト合金、銅等が考えられる。 <7th step>
As shown in FIG. 7, by superimposing a conductive metal on the metal plating layer 4, the metal layer 5 for mounting a semiconductor element and one or more electrode layers 6 are independently formed on the base material 1. Form. Nickel was used as the conductive metal in this embodiment. This is because when gold is used for the metal plating layer 4 in the previous step, nickel has the best adhesion to the gold plating layer. Further, as the conductive metal to be electrodeposited, nickel-cobalt alloy, copper and the like can be considered.

本形態における電着工程では、第１および第２のレジストパターン層２Ｂ，３Ｂの表面を超えて導電性金属を電着させることにより金属層５および電極層６の上端部周縁に第１のレジストパターン層２Ｂの上面側に張り出すオーバーハング部５Ａを形成するとともに、第２のレジストパターン層３Ｂの上面側に張り出すオーバーハング部６Ａを形成した。このように、オーバーハング部５Ａ，６Ａを形成することは必須ではない。ただ、オーバーハング部５Ａ，６Ａを形成することで、第１および第２のレジストパターン層２Ｂ，３Ｂを除去した後の樹脂封止工程（図１１参照）において、樹脂９（図１１参照；以下同じ）に対し各オーバーハング部５Ａ，６Ａが食い込んだ形状となるので、かかる食い込み効果により後の工程である剥離作業（図１２参照）等により母材１を樹脂９による封止部側から引き剥し除去をする際、金属層５および電極層６が母材側にくっついて引き離されることなく、確実に樹脂９による封止部側に残り、ズレや欠け等を効果的に防止して、半導体装置Ｉ（図１５参照；以下同じ）の信頼性を向上させることができる。また、金属層５および電極層６の上端部周縁全周にわたって形成される特有のオーバーハング部５Ａ，６Ａ形状により、半導体装置Ｉの裏面側から金属層５および電極層６と樹脂９との境界部分を通して侵入する水分等の上方への侵入を阻止し、耐水性にも優れたものとすることができる。 In the electrodeposition step in this embodiment, the conductive metal is electrodeposited over the surfaces of the first and second resist pattern layers 2B and 3B, so that the first resist is applied to the peripheral edges of the upper ends of the metal layer 5 and the electrode layer 6. An overhang portion 5A overhanging the upper surface side of the pattern layer 2B was formed, and an overhang portion 6A overhanging the upper surface side of the second resist pattern layer 3B was formed. As described above, it is not essential to form the overhang portions 5A and 6A. However, in the resin sealing step (see FIG. 11) after removing the first and second resist pattern layers 2B and 3B by forming the overhang portions 5A and 6A, the resin 9 (see FIG. 11; hereinafter Since each of the overhang portions 5A and 6A has a shape that bites into the same), the base material 1 is pulled from the sealing portion side by the resin 9 by a peeling operation (see FIG. 12), which is a later process, due to the biting effect. When the metal layer 5 and the electrode layer 6 are peeled off and removed, the metal layer 5 and the electrode layer 6 are not separated from each other by sticking to the base material side, but remain on the sealing portion side by the resin 9, effectively preventing misalignment and chipping, and the semiconductor. The reliability of device I (see FIG. 15; the same applies hereinafter) can be improved. Further, due to the unique shapes of the overhang portions 5A and 6A formed over the entire circumference of the upper end portion of the metal layer 5 and the electrode layer 6, the boundary between the metal layer 5 and the electrode layer 6 and the resin 9 from the back surface side of the semiconductor device I. It is possible to prevent the invasion of moisture or the like that invades through the portion upward, and to have excellent water resistance.

＜第８の工程＞
図８に示すように、第１および第2のレジストパターン層２Ｂ，３Ｂを剥離・除去する。ここで、母材１の裏面に塗布したレジスト２Ａもすべて同様に除去する。 <8th step>
As shown in FIG. 8, the first and second resist pattern layers 2B and 3B are peeled off and removed. Here, all the resist 2A applied to the back surface of the base material 1 is also removed in the same manner.

＜第９の工程＞
図９に示すように、金属層５に半導体素子７を搭載して接合する。 <9th step>
As shown in FIG. 9, the semiconductor element 7 is mounted on the metal layer 5 and joined.

＜第１０の工程＞
図１０に示すように、半導体素子７の電極（図示せず）と各電極層６とをワイヤ８，８により電気的に接続する。かかるワイヤ８，８の接続にはワイヤボンディング法を好適に適用し得る。 <10th step>
As shown in FIG. 10, the electrodes (not shown) of the semiconductor element 7 and the electrode layers 6 are electrically connected by wires 8 and 8. A wire bonding method can be preferably applied to the connection of the wires 8 and 8.

＜第１１の工程＞
図１１に示すように、母材１上において金属層５に載置された半導体素子７を含む搭載部分の全体を樹脂９で封止して複数個が一体となった半導体装置Ｉを形成する。 <11th step>
As shown in FIG. 11, the entire mounting portion including the semiconductor element 7 mounted on the metal layer 5 on the base material 1 is sealed with the resin 9 to form a semiconductor device I in which a plurality of the semiconductor devices I are integrated. ..

＜第１２の工程＞
図１２に示すように、複数個が一体となった半導体装置Ｉから母材１を剥離して半導体装置Ｉの裏面の金属メッキ層４を露出させる。当該工程における母材１の剥離の結果、母材１の凸部１Ａ（例えば、図１１参照）の位置には凹部となる空間１Ｃが形成される。 <12th step>
As shown in FIG. 12, the base material 1 is peeled off from the semiconductor device I in which a plurality of devices are integrated to expose the metal plating layer 4 on the back surface of the semiconductor device I. As a result of peeling of the base material 1 in the step, a space 1C to be a concave portion is formed at the position of the convex portion 1A (for example, see FIG. 11) of the base material 1.

図１３は、個片化前の一体となっている複数の半導体装置Ｉを、当該工程を終えた状態で裏面から見て示す模式図である。同図に示すように、金属層５および電極層６はこれらと同形状の金属メッキ層４上に形成されており、図中で網点領域として示す空間１Ｃが形成されている。また、図中に太い実線で囲んだ領域Ａが次工程で個片化して形成する一個の半導体装置Ｉである。かかる個片化は、Ｘ方向およびＹ方向に関する所定の切断線に沿って切断することにより行う。ここで、個片化の際のＹ方向に関する切断線の中心線を図中にＬ１，Ｌ２として、またＸ方向に関する切断線の中心線を図中にＬ３，Ｌ４として示す。 FIG. 13 is a schematic view showing a plurality of integrated semiconductor devices I before individualization as viewed from the back surface in a state where the process is completed. As shown in the figure, the metal layer 5 and the electrode layer 6 are formed on a metal plating layer 4 having the same shape as these, and a space 1C shown as a halftone dot region in the figure is formed. Further, the region A surrounded by a thick solid line in the figure is one semiconductor device I formed by individualizing in the next step. Such individualization is performed by cutting along predetermined cutting lines in the X and Y directions. Here, the center line of the cutting line in the Y direction at the time of individualization is shown as L1 and L2 in the figure, and the center line of the cutting line in the X direction is shown as L3 and L4 in the figure.

＜第１３の工程＞
図１４に示すように、第1のレジストパターン層２Ｂ（例えば図７参照）と母材１との当接部の中心を通る切断線に沿い刃厚が前記当接部の幅と同等もしくは前記幅よりも小さい切断工具１０で図１２に示す切断線Ｌ１〜Ｌ４に沿う切断を行うことにより、母材１を剥離した複数の半導体装置Ｉを個片化する。この場合の切断工具１０としてはダイシングソーが最適である。かくして個片化された複数の半導体装置Ｉを得る。この半導体装置Ｉは金属メッキ４が電極層６の端面にも形成されたものとなる。このようにして形成した半導体装置Ｉに関し、図１５に基づきさらに詳説する。 <13th step>
As shown in FIG. 14, the blade thickness is equal to or the width of the contact portion along the cutting line passing through the center of the contact portion between the first resist pattern layer 2B (see, for example, FIG. 7) and the base material 1. By cutting along the cutting lines L1 to L4 shown in FIG. 12 with a cutting tool 10 having a width smaller than the width, the plurality of semiconductor devices I from which the base material 1 has been peeled off are separated into individual pieces. The dicing saw is the most suitable cutting tool 10 in this case. In this way, a plurality of semiconductor devices I that have been separated are obtained. In this semiconductor device I, the metal plating 4 is also formed on the end face of the electrode layer 6. The semiconductor device I thus formed will be described in more detail with reference to FIG.

図１５は、本発明の実施の形態に係る半導体装置Ｉを個片化してその一個を示す模式図である。同図に示すように、半導体装置Ｉは、半導体素子７を搭載している金属層５と、複数の電極層６とを樹脂９で一体的に封止して形成したものである。ここで、電極層６は、金属層５のＸ方向に沿う両側に配設され半導体素子７とワイヤ８，８で接続されるとともにＸ方向に沿う金属層５と反対側の端面が露出している。また、金属層５および電極層６の裏面には個別に金属メッキ層４が形成され、特に電極層６の金属メッキ層４は電極層６の端面にまで連続して一体的に形成されている。 FIG. 15 is a schematic view showing one of the semiconductor devices I according to the embodiment of the present invention, which are separated into individual pieces. As shown in the figure, the semiconductor device I is formed by integrally sealing a metal layer 5 on which a semiconductor element 7 is mounted and a plurality of electrode layers 6 with a resin 9. Here, the electrode layer 6 is arranged on both sides of the metal layer 5 along the X direction and is connected to the semiconductor element 7 by wires 8 and 8, and the end face on the opposite side of the metal layer 5 along the X direction is exposed. There is. Further, a metal plating layer 4 is individually formed on the back surfaces of the metal layer 5 and the electrode layer 6, and in particular, the metal plating layer 4 of the electrode layer 6 is continuously and integrally formed up to the end surface of the electrode layer 6. ..

かくして半導体装置Ｉの回路基板１１に対する半田１２による接合により実装する際には、電極層６の裏面に施した金属メッキ層４が電極層６の端面にまで連続して一体的に形成されているので、半導体装置Ｉの端面に隣接する先端部から端面に向けて連続的に立ち上がる曲線状の半田１２のフィレットが良好に形成される。この結果、半導体装置Ｉの上方から前記フレットの形成状態を容易に視認でき、半田接合の良否を容易かつ確実に検査することができるようになっている。 Thus, when mounting the semiconductor device I to the circuit board 11 by soldering 12, the metal plating layer 4 applied to the back surface of the electrode layer 6 is continuously and integrally formed up to the end surface of the electrode layer 6. Therefore, the fillet of the curved solder 12 that continuously rises from the tip end portion adjacent to the end face of the semiconductor device I toward the end face is satisfactorily formed. As a result, the formed state of the frets can be easily visually recognized from above the semiconductor device I, and the quality of the solder joint can be easily and surely inspected.

本発明は半導体デバイスを製造販売する産業分野で有効に利用することができる。 The present invention can be effectively used in the industrial field of manufacturing and selling semiconductor devices.

Ｉ 半導体装置
１ 母材
１Ａ 凸部
２Ａ、３Ａ レジスト
２Ｂ 第１のレジスト層
３Ｂ 第２のレジスト層
４ 金属メッキ層
５ 金属層
５Ａ，６Ａ オーバーハング部
６ 電極層
７ 半導体素子
８ ワイヤ
９ 樹脂
１０ 切断工具
１１ 回路基板
１２ 半田


I Semiconductor device 1 Base material 1A Convex part 2A, 3A Resist
2B 1st resist layer 3B 2nd resist layer 4 Metal plating layer 5 Metal layers 5A, 6A Overhang
6 Electrode layer 7 Semiconductor element 8 Wire 9 Resin
10 Cutting tool 11 Circuit board 12 Solder

Claims (2)

導電性を有する母材上に複数の半導体素子を搭載するとともに、前記半導体素子を樹脂で一体化した複数の半導体装置を個片化により得る半導体装置の製造方法であって、
前記母材の少なくとも一面側に第１のレジストを塗布する第１の工程と、
前記第１のレジストに所定のパターニングを施した第1のレジストパターン層を形成する第２の工程と、
前記母材のうち前記第１のレジストパターン層が形成された領域以外の領域を所定の深さだけエッチングする第３の工程と、
前記母材のエッチング領域に第２のレジストを塗布する第４の工程と、
前記第２のレジストを露光して第2のレジストパターン層を形成する第５の工程と、
前記一面側において導電面が露出している前記母材に金属メッキ層を形成する第６の工程と、
前記金属メッキ層に重ねて導電性金属を電着することで、前記母材上に半導体素子搭載用の金属層と1以上の電極層とをそれぞれ独立して形成する第７の工程と、
前記第１および第2のレジストパターン層を除去する第８の工程と、
前記金属層に半導体素子を搭載するとともに、前記半導体素子と前記各電極層とを電気的に接続する第９の工程と、
前記母材上において前記金属層に載置された前記半導体素子を含む搭載部分の全体を樹脂で封止して複数個が一体となった半導体装置を形成する第１０の工程と、
複数個が一体となった前記半導体装置から前記母材を剥離して前記半導体装置の裏面の前記金属メッキ層を露出させる第１１の工程と、
前記第1のレジストパターン層と前記母材との当接部を通る切断線に沿い刃厚が前記当接部の幅と同等もしくは前記幅よりも小さい切断工具で前記母材を剥離した前記半導体装置を個片化する第１２の工程とを有することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device in which a plurality of semiconductor elements are mounted on a conductive base material and a plurality of semiconductor devices in which the semiconductor elements are integrated with a resin are obtained by individualization.
The first step of applying the first resist to at least one surface side of the base material, and
A second step of forming a first resist pattern layer in which a predetermined patterning is applied to the first resist, and
A third step of etching a region of the base material other than the region where the first resist pattern layer is formed by a predetermined depth, and
A fourth step of applying the second resist to the etching region of the base material, and
A fifth step of exposing the second resist to form a second resist pattern layer, and
A sixth step of forming a metal plating layer on the base material whose conductive surface is exposed on one surface side, and
A seventh step of independently forming a metal layer for mounting a semiconductor element and one or more electrode layers on the base material by electrodepositing a conductive metal on the metal plating layer.
The eighth step of removing the first and second resist pattern layers and
A ninth step of mounting the semiconductor element on the metal layer and electrically connecting the semiconductor element and each of the electrode layers.
A tenth step of forming a semiconductor device in which a plurality of mounting portions are integrally formed by sealing the entire mounting portion including the semiconductor element mounted on the metal layer on the base material with a resin.
An eleventh step of peeling the base material from the semiconductor device in which a plurality of the devices are integrated to expose the metal plating layer on the back surface of the semiconductor device.
The semiconductor whose base material is peeled off with a cutting tool whose blade thickness is equal to or smaller than the width of the contact portion along a cutting line passing through the contact portion between the first resist pattern layer and the base material. A method for manufacturing a semiconductor device, which comprises a twelfth step of disassembling the device. 請求項１に記載する半導体装置の製造方法において、
前記第７の工程では、前記第１および第２のレジストパターン層の表面を超えて前記導電性金属を電着させることにより前記金属層および前記電極層の上端部周縁に前記第１および前記第２のレジストパターン層の上面側に張り出すオーバーハング部を形成することを特徴とする半導体装置の製造方法。 In the method for manufacturing a semiconductor device according to claim 1,
In the seventh step, the conductive metal is electrodeposited over the surfaces of the first and second resist pattern layers so that the first and first edges of the upper end of the metal layer and the electrode layer are electrodeposited. 2. A method for manufacturing a semiconductor device, which comprises forming an overhang portion overhanging on the upper surface side of the resist pattern layer of 2.
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